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ADMC401BST
Single-Chip, DSP-Based High Performance Motor Controller
REV.B
Single-Chip, DSP-Based
High Performance Motor Controller
FUNCTIONAL BLOCK DIAGRAM
FEATURES
26 MIPS Fixed-Point DSP Core
Single Cycle Instruction Execution (38.5 ns)
ADSP-21xx Family Code Compatible
16-Bit Arithmetic and Logic Unit (ALU)
Single Cycle 16-Bit � 16-Bit Multiply and Accumulate
Into 40-Bit Accumulator (MAC)
32-Bit Shifter (Logical and Arithmetic)
Multifunction Instructions
Single Cycle Context Switch
Zero Overhead Looping
Conditional Instruction Execution
Two Independent Data Address Generators
Memory Configuration
2K � 24-Bit Internal Program Memory RAM
2K � 24-Bit Internal Program Memory ROM
1K � 16-Bit Internal Data Memory RAM
14-Bit Address Bus and 24-Bit Data Bus for External
Memory Expansion
High Resolution Multichannel ADC
12-Bit Pipeline Flash Analog-to-Digital Converter
Eight Dedicated Analog Inputs
Simultaneous Sampling Capability
All Eight Inputs Converted in <2 �s
4.0 V p-p Input Voltage Range
PWM Synchronized or External Convert Start
Internal or External Voltage Reference
Out-of-Range Detection
Voltage Reference
Internal 2.0 V � 2.0% Voltage Reference
Three-Phase 16-Bit PWM Generation Unit
Programmable Switching Frequency, Dead Time and
Minimum Pulsewidth
Edge Resolution of 38.5 ns
One or Two Updates per Switching Period
Hardware Polarity Control
Individual Enable/Disable of Each Output
High Frequency Chopping Mode
Dedicated Shutdown Pin (PWMTRIP)
Additional Shutdown Pins in I/O System
High Output Sink and Source Capability (10 mA)
Incremental Encoder Interface Unit
Quadrature Rates to 17.3 MHz
Programmable Filtering of Encoder Inputs
Alternative Frequency and Direction Mode
Two Registration Inputs to Latch Count Value
Optional Hardware Reset of Counter
Single North Marker Mode
Count Error Monitor Function
Dedicated 16-Bit Loop Timer (Periodic Interrupts)
Companion Encoder Event (1/T) Timer(Continued on Page 14)
RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICSNOTESBidirectional pins: D0–D23, RFS0, RFS1, TFS0, TFS1, SCLK0 and SCLK1, PIO0–PIO11.Input only pins: PWMTRIP, PWMPOL, PWMSR, RESET, EIA, EIB, EIZ, EIS, ETU0, ETU1, DR1A, DR1B, DR0, CLKIN, CONVST, MMAP, BMODE, BR
and PWD.Programmable I/O Pins (PIO0–PIO11).Output pins: PWMSYNC, AUX0, AUX1, CLKOUT, DT0, DT1, BG, BGH, PMS, DMS, BMS, RD, WR, PWDACK and A0–A13.Output pins: AH, AL, BH, BL, CH and CL.Although specified for TTL outputs, all ADMC401 outputs are CMOS-compatible and will drive to VDD–0.3 V and GND+0.3 V assuming no dc loads.Input only pins RESET, EIA, EIB, EIZ, EIS, ETU0, ETU1, DR1A, DR1B, DR0, CLKIN, CONVST, MMAP, BMODE, BR and PWD.Input pins with internal pull-down PIO0–PIO11 and PWMTRIP.Input pins with internal pull-up, PWMPOL and PWMSR.Three-statable pins: A0–A13, D0–D23, PMS, DMS, BMS, RD, WR, DT0, DT1, RFS0, RFS1, TFS0, TFS1, SCLK0, SCLK1.Idle refers execution of the IDLE instruction. Deasserted pins are driven to VDD or GND. Current reflects device operation with CLKOUT disabled.Current reflects device operating with no output loads.Guaranteed but not tested.Output Pin Capacitance is the capacitive load for any three-state output pin.
Specifications subject to change without notice.
(VDD = AVDD = 5 V � 5%, GND = AGND = 0 V, TAMB = –40�C to +85�C,
CLKIN = 13 MHz, unless otherwise noted)
ADMC401–SPECIFICATIONS
ANALOG-TO-DIGITAL CONVERTERNOTESExcludes Internal Voltage Reference Error.Analog Input Pins VIN0 to VIN7.
Typical values are neither tested nor guaranteed.
Specifications subject to change without notice.
VOLTAGE REFERENCENOTESRelative tolerance due to temperature change, TMIN to TMAX.
Specifications subject to change without notice.
POWER-ON RESETSpecifications subject to change without notice.
(VDD = AVDD = 5 V � 5%, GND = AGND = 0 V, TAMB = –40�C to +85�C, CLKIN = 13 MHz,
VIN0 to VIN7 = 4.0 V p-p, VREF = 2.0 V, unless otherwise noted)
(VDD = AVDD = 5 V � 5%, GND = AGND = 0 V, TAMB = –40�C to +85�C, CLKIN = 13 MHz, VIN0 to VIN7 =
4.0 V p-p, VREF = 2.0 V, unless otherwise noted)
(GND = AGND = 0 V, TAMB = –40�C to +85�C, CLKIN = 13 MHz, unless otherwise noted)
ADMC401
ADMC401
ABSOLUTE MAXIMUM RATINGS*Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
Input Voltage . . . . . . . . . . . . . . . . . . . . .–0.3 V to VDD + 0.3 V
Output Voltage Swing . . . . . . . . . . . . . .–0.3 V to VDD + 0.3 V
Operating Temperature Range (Ambient) . . . .–40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C
Lead Temperature (5 sec) . . . . . . . . . . . . . . . . . . . . . .+280°C
*Stresses above those listed under absolute maximum ratings may cause permanent
damage to the device. These are stresses only; functional operation of the device
at these or any other conditions above those indicated in the operational section of
this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADMC401 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDEADMC401-ADVEVALKIT
Timing Parameters
GENERAL NOTESUse the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results for
an individual device, the values given in this data sheet reflect
statistical variations and worst cases. Consequently, you cannot
meaningfully add up parameters to derive longer times.
TIMING NOTESSwitching characteristics specify how the processor changes its
signals. You have no control over this timing; it is dependent on
the internal design. Timing requirements apply to signals that
are controlled outside the processor, such as the data input for a
read operation.
Timing requirements guarantee that the processor operates
correctly with another device. Switching characteristics tell you
what the device will do under a given circumstance. Also, use
the switching characteristics to ensure any timing requirement
of a device connected to the processor (such as memory) is
satisfied.
MEMORY REQUIREMENTSThis chart links common memory device specification names
and ADMC401 timing parameters for your convenience.
with a frequency equal to half the instruction rate; a 13 MHz
clock (which is equivalent to 76.9 ns) yields a 38.5 ns processor
cycle (equivalent to 26 MHz). t
0.5t
parameters to obtain specification value.
Example: t
Timing Requirements:
Switching Characteristics:
Control SignalsTiming Requirement:
NOTEApplies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal
oscillator start-up time).
Figure 1.Clock Signals
ADMC401NOTESIf IRQx and FI inputs meet tIFS and tIFH setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on
the following cycle. (Refer to “Interrupt Controller Operation” in the Program Control chapter of the ADSP-2100 Family User’s Manual, Third Edition for further
information on interrupt servicing.)Edge-sensitive interrupts require pulsewidths greater than 10 ns; level-sensitive interrupts must be held low until serviced.IRQx = IRQ0 and IRQ1.Flag Output = FL1 and FO.
Figure 2.Interrupts and Flags
NOTESBR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized
on the following cycle. Refer to the ADSP-2100 Family User’s Manual, Third Edition for BR/BG cycle relationships.BGH is asserted when the bus is granted and the processor requires control of the bus to continue.
Figure 3.Bus Request–Bus Grant
ADMC401w = wait states × tCK.
Figure 4.Memory Read
w = wait states × tCK.
Figure 5.Memory Write
ADMC401Figure 6.Serial Ports
POWER DISSIPATIONTo determine total power dissipation in a specific application,
the following equation should be applied for each output:
C × VDD2
×f
C = load capacitance,f= output switching frequency.
Example:In an application where external data memory is used and no
other outputs are active, power dissipation is calculated as
follows:
Assumptions:External data memory is accessed every cycle with 50% of the
address pins switching.External data memory writes occur every other cycle with
50% of the data pins switching.Each address and data pin has a 10 pF total load at the pin.The application operates at VDD = 5.0 V and tCK = 38.5 ns.
Total Power Dissipation = PINT + (C × VDD2 ×f)
PINT = VDD × (IDD Digital + IDD Analog)
(C × VDD2
× f) is calculated for each output:Total power dissipation for this example is PINT + 91 mW.
TEST CONDITIONS
Output Disable TimeOutput pins are considered to be disabled when they have
stopped driving and started a transition from the measured
output high or low voltage to a high impedance state. The out-
put disable time (tDIS) is the difference of tMEASURED and tDECAY,
as shown in the Output Enable/Disable diagram. The time is the
interval from when a reference signal reaches a high or low
voltage level to when the output voltages have changed by 0.5 V
from the measured output high or low voltage. The decay time,
tDECAY, is dependent on the capacitative load, CL, and the cur-
rent load, iL, on the output pin. It can be approximated by the
following equation:
from which
is calculated. If multiple pins (such as the data bus) are dis-
abled, the measurement value is that of the last pin to stop
driving.
Figure 7.Voltage Reference Levels for AC Measure-
ments (Except Output Enable/Disable)
Output Enable TimeOutput pins are considered to be enabled when that have made
a transition from a high-impedance state to when they start
driving. The output enable time (tENA) is the interval from when
a reference signal reaches a high or low voltage level to when
the output has reached a specified high or low trip point, as
shown in the Output Enable/Disable diagram. If multiple pins
(such as the data bus) are enabled, the measurement value is
that of the first pin to start driving.
Figure 8.Output Enable/Disable
Figure 9.Equivalent Device Loading for AC Measure-
ments (Including All Fixtures)
ADMC401
PIN FUNCTION DESCRIPTIONNC: These pins must be left unconnected
PIN CONFIGURATION
ADMC401(Continued from Page 1)
Programmable Digital I/O (PIO) Port
12-Pin Configurable Digital I/O Port
Flexible Interrupt Generation
Four Dedicated PIO Interrupt Vectors
Each I/O Line Configurable as PWM Shutdown
Two 8-Bit Auxiliary PWM Outputs
Programmable Switching Frequency
Independent or Offset Modes
Two-Channel Event Timer (Capture) Unit
Configurable Event Definition
Single-Shot or Free-Running Modes
Peripheral Interrupt Controller
Manages Peripheral Interrupts
16-Bit Watchdog Timer
Internal Power-On Reset System
Programmable 16-Bit Interval Timer with Prescaler
Two Double Buffered Synchronous Serial Ports
Boot Load Protocols via SPORT1:
Synchronous E2PROM/SROM Booting
UART Boot Loader with Autobaud
Synchronous Master or Slave Boot Loader
Debugger Interface via SPORT1:
UART Interface with Autobaud
Synchronous Master or Slave Interface
Full Debugger for Program Development
Industrial Temperature Range –40�C to +85�C
Operating Voltage 5.0 V � 5%
Package: 144-Lead LQFP
GENERAL DESCRIPTIONThe ADMC401 is a single-chip DSP-based controller, suitable
for high performance control of ac induction motors (ACIM),
permanent magnet synchronous motors (PMSM), brushless dc
motors (BDCM) and switched reluctance (SR) motors in indus-
trial applications. The ADMC401 integrates a 26 MIPS, fixed-
point DSP core with a complete set of motor control peripherals
that permits fast motor control in a highly integrated environment.
The DSP core of the ADMC401 is the ADSP-2171 which is
completely code compatible with the ADSP-21xx DSP family
(as well as other members of the integrated motor controllers of
the ADMC3xx family) and combines three computational units,
data address generators and a program sequencer. The computa-
tional units comprise an ALU, a multiplier/accumulator (MAC)
and a barrel shifter. The DSP core also adds instructions for bit
manipulation, squaring (x2), biased rounding and global inter-
rupt masking. In addition, two flexible double-buffered, bidirec-
tional synchronous serial ports are included in the ADMC401.
The ADMC401 provides 2K × 24-bit internal program memory
RAM, 2K × 24-bit internal program memory ROM and 1K ×
16-bit internal data memory RAM. The program and data
memory RAM can be boot loaded through the serial port from
either a serial E2PROM, through a UART connection (either
from external host microprocessor or from the Motion Control
Debugger) or via a synchronous serial interface from a host
microprocessor. Alternatively, the internal program and data
memory RAM may be booted from an external device across the
address and data buses. The program memory ROM includes a
monitor that adds software debugging features through the serial
port.
Additionally, the ADMC401 device adds significant external
memory and peripheral expansion capabilities by making avail-
able the full address and data bus of the DSP core. This feature
permits expansion of both external program and data memory
and means that the DSP core can address up to 14K × 24 bits of
external program memory and up to 13K × 16 bits of external
data memory.
The ADMC401 contains a number of special purpose, motor
control peripherals. The first is a high performance, 8-channel,
12-bit ADC system with dual channel simultaneous sampling
ability across 4 pair of inputs. An internal precision voltage refer-
ence is also available as part of the ADC system. In addition, a
three-phase, 16-bit, center-based PWM generation unit can be
used to produce high-accuracy PWM signals with minimal pro-
cessor overhead. The ADMC401 also contains a flexible incre-
mental encoder interface unit for position sensor feedback;
two adjustable-frequency auxiliary PWM outputs, 12 lines of
digital I/O; a 2-channel event capture system; a 16-bit watchdog
timer; two 16-bit interval timers (one of which can be linked to
the encoder interface unit) and an interrupt controller that man-
ages all peripheral interrupts. Finally, the ADMC401 contains
an integrated power-on-reset (POR) circuit that can be used to
generate the required reset signal for the device on power-on.
Figure 10. DSP Core Block Diagram
ARCHITECTURE OVERVIEWFigure 10 is a functional block diagram of the DSP core of the
ADMC401. The DSP core is based on the fixed-point ADSP-
2171 core that is a member of the fixed-point ADSP-21xx
family of general purpose DSPs from Analog Devices Inc.
The ADSP-2171 flexible architecture and comprehensive in-
struction set allow the processor to perform multiple operations
in parallel.
In one processor cycle (38.5 ns with a 13 MHz crystal) the DSP
core can:
• Generate the next program address.
• Fetch the next instruction.
• Perform one or two data moves.
• Update one or two data address pointers.
• Perform a computational operation.
This all takes place while the ADMC401 continues to:
• Receive and transmit through the serial ports.
• Decrement the interval timers.
• Generate PWM signals.
• Convert the ADC input signals.
• Operate the encoder interface unit.
• Operate all other peripherals including the auxiliary PWM and
event timer subsystem.
The processor contains three independent computational units:
the arithmetic and logic unit (ALU), the multiplier/accumulator
(MAC) and the shifter. The computational units process 16-bit
data directly and have provisions to support multiprecision
computations. The ALU performs a standard set of arithmetic
and logic operations; division primitives are also supported. The
MAC performs single-cycle multiply, multiply/add, multiply/
subtract operations with 40 bits of accumulation. The shifter
performs logical and arithmetic shifts, normalization, denormal-
ization and derive exponent operations. The shifter can be used
to implement numeric format control efficiently, including
floating-point representations. The internal result (R) bus di-
rectly connects the computational units so that the output of
any unit may be the input of any unit on the next cycle.
A powerful program sequencer and two dedicated data address
generators ensure efficient delivery of operands to these compu-
tational units. The sequencer supports conditional jumps, sub-
routine calls and returns in a single cycle. With internal loop
counters and loop stacks, the ADMC401 executes looping code
with zero overhead; no explicit jump instructions are required to
maintain the loop.
ADMC401Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches from data memory and pro-
gram memory. Each DAG maintains and updates four address
pointers (I registers). Whenever the pointer is used to access
data (indirect addressing), it is post-modified by the value in
one of four modify (M) registers. A length value may be associ-
ated with each pointer (L registers) to implement automatic
modulo addressing for circular buffers. The circular buffering
feature is also used by the serial ports for automatic data trans-
fers to and from on-chip memory. DAG1 generates only data
memory addresses but provides an optional bit-reversal capabil-
ity. DAG2 may generate either program or data memory ad-
dresses, but has no bit-reversal capability.
Efficient data transfer is achieved with the use of five internal
buses:
• Program Memory Address (PMA) Bus.
• Program Memory Data (PMD) Bus.
• Data Memory Address (DMA) Bus.
• Data Memory Data (DMD) Bus.
• Result (R) Bus.
Program memory can store both instructions and data, permit-
ting the ADMC401 to fetch two operands in a single cycle, one
from internal program memory and one from internal data
memory. The ADMC401 can fetch an operand from on-chip
program memory and the next instruction in the same cycle.
The ADMC401 writes data from its 16-bit registers to the 24-
bit program memory using the PX register to provide the lower
eight bits. When it reads data (not instructions) from 24-bit
program memory to a 16-bit data register, the lower eight bits
are placed in the PX register.
The ADMC401 can respond to a number of distinct DSP core
and peripheral interrupts. The DSP core interrupts include
serial port receive and transmit interrupts, timer interrupts,
software interrupts and external interrupts. In addition, there is
a master RESET signal. The motor control peripherals also
produce interrupts to the DSP core.
The two serial ports (SPORTs) provide a complete synchronous
serial interface with optional companding in hardware and a
wide variety of framed and unframed data transmit and receive
modes of operation. Each SPORT can generate an internal
programmable serial clock or accept an external serial clock.
Boot loading of both the program and data memory RAM of the
ADMC401 can be through the serial port SPORT1. Alterna-
tively the ADMC401 can be boot loaded from an external byte-
wide memory connected to the external address and data buses.
After reset, seven wait states are automatically generated. This
permits, for example, a 38.5 ns ADMC401 to use an external
250 ns EPROM as boot memory. The internal boot address
generator provides the addresses for booting from an external
byte-wide memory.
A programmable interval counter is also included in the DSP
core and can be used to generate periodic interrupts. A 16-bit
count register (TCOUNT) is decremented every n processor
cycles, where n-1 is a scaling value stored in the 8-bit TSCALE
register. When the value of the counter reaches zero, an inter-
rupt is generated and the count register is reloaded from a 16-
bit period register (TPERIOD).
The ADMC401 instruction set provides flexible data moves and
multifunction (one or two data moves with a computation)
instructions. Each instruction is executed in a single 38.5 ns
processor cycle (for a 13 MHz crystal). The ADMC401 assem-
bly language uses an algebraic syntax for ease of coding and
readability. A comprehensive set of development tools supports
program development.
Serial PortsThe ADMC401 incorporates two complete synchronous serial
ports (SPORT0 and SPORT1) for serial communications and
multiprocessor communication. The following is a brief list of
the capabilities of the ADMC401 SPORTs. Refer to the ADSP-
2100 Family User’s Manual, Third Edition for further details. SPORTs are bidirectional and have a separate, double-
buffered transmit and receive section.SPORTs can use an external serial clock or generate their
own serial clock internally.SPORTs have independent framing for the receive and trans-
mit sections. Sections run in a frameless mode or with frame
synchronization signals internally or externally generated.
Frame synchronization signals are active high or inverted,
with either of two pulsewidths and timings.
SPORTs support serial data word lengths from 3 bits to 16
bits and provide optional A-law and µ-law companding.SPORT receive and transmit sections can generate unique
interrupts on completing a data word transfer.SPORTs can receive and transmit an entire circular buffer of
data with only one overhead cycle per data word. An inter-
rupt is generated after a data buffer transfer.SPORT0 has a multichannel interface to selectively receive
and transmit a 24-word or 32-word, time-division multi-
plexed, serial bitstream.SPORT1 can be configured to have two external interrupts
(IRQ0 and IRQ1), and the Flag In and Flag Out signals. The
internally generated serial clock may still be used in this
configuration.
The following are additional capabilities of the ADMC401
SPORTs that are not part of the ADSP-21xx products:SPORT1 is the input for single pin program and data
memory boot loading. The RFS1 pin can be configured
internally to the ADMC401 as an SROM/E2PROM reset
signal.SPORT1 has two data receive pins (DR1A and DR1B). The
DR1A pin is intended only for synchronous data receive
from the external E2PROM. The DR1B pin can be used as
the data receive pin for a general purpose SPORT after boot-
ing or as the data receive pin for other boot load modes or as
the UART/debugger interface. The DR1A and DR1B pins
are internally multiplexed onto the one data receive pin of
the SPORT. The particular data receive pin selected is deter-
mined by Bit 4 of the MODECTRL register.
PIN FUNCTION DESCRIPTIONThe ADMC401 is available in an 144-lead TQFP package. Table
I contains the pin descriptions.
Table I.Pin List
INTERRUPT OVERVIEWThe ADMC401 can respond to different interrupt sources, some
of which are internal DSP core interrupts and others from the
motor control peripherals. The DSP core interrupts include a:Power up (or RESET) interrupt.A peripheral (or IRQ2) interrupt.A SPORT0 receive and a SPORT0 transmit interrupt.A SPORT1 receive (or IRQ0) and a SPORT1 transmit (or
IRQ1) interrupt.Two software interrupts.An interval timer timeout interrupt.A power-down interrupt.
In addition, the motor control peripherals add other interrupts
that include:A PWMSYNC interrupt.An ADC end of conversion interrupt.An encoder loop timer timeout interrupt.Five peripheral input/output (PIO) interrupts.An event timer interrupt.An encoder count error interrupt.A PWM trip interrupt.
The interrupts are internally prioritized and individually maskable
except for the nonmaskable power-down interrupt.
Memory MapThe ADMC401 has two distinct memory types; program memory
and data memory (in addition to external boot memory). In
general, program memory contains user code and coefficients,
while the data memory is used to store variables and data during
program execution. Both program memory RAM and ROM is
provided internally on the ADMC401. The program memory
map of the ADMC401 can be altered depending on the state of
the MMAP and BMODE pins. The various program memory
maps are illustrated in Figure 11 for the permissible settings of
MMAP and BMODE. The state of these pins also impact the
way in which the internal memory of the ADMC401 is booted,
as described later.
There is 2K of internal ROM on the ADMC401. Setting the
ROMENABLE bit on the Data Memory Wait State Control
Register (at address DM (0x3FFE)) enables the ROM. When the
ROMENABLE bit is set to 1, addressing program memory in the
ROM range will access the on-chip ROM. When ROMENABLE
is set to zero, addressing program memory in this range will
access external program memory. The ROMENABLE bit is
initialized to zero after reset unless MMAP and BMODE = 1.
When MMAP = BMODE = 0, the ADMC401 provides 2K × 24
bits of internal program memory RAM starting at address
0x0000 that is booted from a byte-wide interface on the address
and data buses. Following boot loading, program execution
starts at address 0x0000. In this mode, the remainder of the
program memory space, a 12K × 24-bit block starting at address
0x1000, is assigned to external memory.
When MMAP = BMODE = 1, the program memory map is
identical to the previous case, but ROMENABLE defaults to 1 at
ADMC401When MMAP = 1 and BMODE = 0, the internal program
memory RAM is mapped to the top of the program memory space
(starting at address 0x3800) and no boot loading occurs. Program
execution starts from external program memory at address 0x0000.
Only with ROMENABLE = 1 are the internal ROM monitor
and debugger features of the ADMC401 available for program
development. Additionally, certain spaces of the memory map
have predefined functions as illustrated in Figure 12 where it
can be seen that address space 0x0000 to 0x005F is reserved for
the interrupt vector table.
Figure 12.Detailed View of Program Memory Map with
MMAP = BMODE = 1
The program memory interface can generate 0 to 7 wait states
for external memory devices. The program memory wait state
field (PWAIT) in the System Control Register controls the number
of inserted wait states and defaults to 7. The structure of the
System Control Register is shown at the end of the data sheet.
The data memory map of the ADMC401 is shown in Figure 13.
The internal data memory RAM of the ADMC401 is arranged
as a single 1K × 16-bit block starting at address 0x3800. In
addition, there are two 1K blocks of reserved data memory
space; one block starting at address 0x2000 that is reserved for
the peripheral registers and one starting at address 0x3C00 that
DWAIT3 and DWAIT4 fields of the Data Memory Wait State
Register (MEMWAIT) as illustrated in Figure 13. Following
reset, DWAIT0 = DWAIT1 = DWAIT2 = DWAIT 3 =
DWAIT4 = 7. However, in standalone mode with MMAP =
BMODE = 1, the internal monitor code writes 0 to these five
fields. For correct operation DWAIT2 must always be 0. The
configuration of the MEMWAIT register is shown at the end of
the data sheet.
Figure 13.Data Memory Map of the ADMC401
ROM CodeThe 2K × 24-bit block of internal program memory ROM start-
ing at address 0x800 contains a monitor function that can be
used to download and execute user programs via the serial port.
In addition, the monitor function supports an interactive mode
in which commands are received and processed from a host that
is configured as a UART device. An example of such a host is
the Windows-based Motion Control Debugger that is part of
the software development system for the ADMC401. In the
interactive mode, the host can access both the internal DSP and
peripheral motor control registers of the ADMC401, read and
write to both program and data memory, implement break-
points and perform single-step operation as part of the program
debugging cycle. Again, this debugging feature is only available
Figure 11.Program Memory Map of ADMC401
SYSTEM INTERFACE
CLOCK SIGNALSThe ADMC401 uses an input clock with a frequency equal to
half the instruction rate; a 13 MHz input clock yields a 38.5 ns
processor cycle (which is equivalent to 26 MHz). Normally
instructions are executed in a single processor cycle. All device
timing is relative to the internal instruction rate, which is indi-
cated by the CLKOUT signal (when enabled). Throughout this
data sheet, the period of the CLKIN signal is denoted by tCKI.
The DSP instruction period is tCK (the period of the CLKOUT
signal), and tCK = 0.5 × tCKI. For 26 MIPS operation, a 13 MHz
CLKIN signal is used, corresponding to tCKI = 76.9 ns and tCK
= 38.5 ns. Additionally, tCK is the fundamental time increment
of the motor control peripherals. Therefore, unless otherwise
specified, the motor control peripherals are clocked at a rate
equal to CLKOUT. The ADMC401 can be clocked by either a
crystal or by an external clock source. The CLKIN input cannot
be halted, changed in frequency, or operated below the specified
minimum frequency during normal operation.
If an external clock source is used, it should be a TTL-compatible
signal running at half the instruction rate. The signal is con-
nected to the CLKIN pin of the ADMC401. In this mode, with
an external clock signal, the XTAL pin must be left unconnected.
Because the ADMC401 includes an on-chip oscillator circuit,
an external crystal may be used instead of a clock source. The
crystal should be connected across the CLKIN and XTAL pins.
A parallel-resonant, fundamental frequency, microprocessor-
grade crystal should be used. The frequency value selected for
the crystal should be equal to half the desired instruction rate
for the processor. Figure 15 shows a 13 MHz crystal properly
connected to yield a 26 MHz processor rate.
The CLKOUT output can be enabled and disabled by the
CLKODIS bit of the SPORT0 Autobuffer Control Register,
DM (0x3FF3). However, extreme care must be exercised when
using this bit (and is thus discouraged) since disabling CLKOUT
effectively disables all motor control peripherals, except the
watchdog timer.
RESET AND POWER-ON RESET CIRCUITThe RESET pin initiates a complete hardware reset of the
ADMC401 when pulled low. The RESET signal must be asserted
when the device is powered up to assure proper initialization.
The ADMC401 contains an integrated power-on reset circuit
that provides an output reset signal, POR, from the ADMC401
on power up and if the power supply voltage falls below the
threshold level. The ADMC401 may be reset from an external
source using the RESET signal or alternatively the internal
power-on reset circuit may be used by connecting the POR pin
to the RESET pin. During power-up the RESET line must be
activated for long enough to allow the DSP core’s internal clock
to stabilize. The power-up sequence is defined as the total time
required for the crystal oscillator to stabilize after a valid VDD is
applied to the processor and for the internal phase locked loop
(PLL) to lock onto the specific crystal frequency. A minimum of
2000tCKI cycles will ensure that the PLL has locked (this does not
include the crystal oscillator start-up time).
voltage, VRST level. As soon as the threshold voltage is attained,
the power on reset circuit enables a 17-bit counter that is
clocked at the CLKOUT rate. While the counter is counting the
POR pin is held low. When the counter overflows, after a time:
the POR pin is brought high and if the POR and RESET pins
are connected, the device is brought out of reset.
The internal power-on reset circuit also acts as a power supply
monitor and puts the POR pin at a LO level if it detects a volt-
age less than VRST–VHYST, where VHYST is the hysteresis voltage
built into the POR circuit. The supply voltage must then exceed
VRST to initiate another power-on reset sequence.
Figure 14.Operation of Power-On Reset (POR) Circuit of
ADMC401
The master reset (RESET = LO) causes a Full System Reset,
which sets all internal stack pointers to the empty stack condi-
tion, masks all interrupts, clears the MSTAT register, restores
the program counter to its initial value and performs a full reset
of all of the motor control peripherals including the watchdog
timer. Following a power-up, it is possible to initiate a Full
System Reset by simply pulling the RESET low. For these
resets, there is no need to wait for PLL stabilization and the
RESET signal must meet the minimum pulsewidth specifica-
tion, tRSP. To generate the external RESET signal, it is recom-
mended to use either an RC circuit with a Schmitt trigger or a
commercially available reset IC.
Separate from a Full System Reset, a software controlled Periph-
eral Reset (excluding the watchdog timer) is achieved by toggling
the DSP FL2 flag with the following code segment:
PRESET:SET FL2;
TOGGLE FL2;
TOGGLE FL2;
RTS;
A full DSP and peripheral reset (except the watchdog timer
itself) will occur automatically on a watchdog trip.
EXTERNAL MEMORY INTERFACEThe ADMC401 can address 14K × 24 bits of external program
memory and up to 13K × 16 bits of external data memory. The
ADMC401 provides the address on a 14-bit address bus
(A13–A0). Instructions or data are transferred across the 24-bit
data bus (D23–D0) during program memory accesses. During
data memory accesses, data is transferred on the 16 most signifi-
cant bits (D23–D8) of the data bus. For a dual off-chip fetch,
the data from program memory is read first, then the data from
data memory. The program memory select pin, PMS, is acti-
vated during external program memory accesses and can be
used as a chip select signal for the external program memory
ADMC401Two control lines indicate the direction of the transfer. Memory
read, RD, is active low, signaling a read from external memory
and memory write; WR, is active low, signaling a write to exter-
nal memory. Typically, the PMS line is connected to the CE
(chip enable) of the external program memory and the RD line
is connected to the CE line of the external data memory. The
RD line is connected to the OE (output enable) and the WR
line is connected to the WE (write enable) of both memories.
On-chip accesses (to internal program memory RAM and ROM)
do not drive any of the external signals. The PMS, RD and the
WR lines remain high (deasserted) and the address and data
buses are three-stated during these internal accesses. Similarly,
internal accesses to data memory (including internal DM RAM
and peripheral and DSP core memory mapped registers) do not
drive external signals and the DMS, RD and the WR lines re-
main high (deasserted) and the address and data buses are also
three-stated.
External peripherals can also be connected externally and memory
mapped to the external memory space of the ADMC401. The
16 MSBs of the external data bus are connected internally to the
16 bits of the internal data memory bus. Therefore, the data
lines D23–D8 should be used for 16-bit peripherals.
BOOT LOADING
Standalone Mode (MMAP = BMODE = 1)Boot loading of the ADMC401 may occur in a number of differ-
ent ways and is determined by the state of both the MMAP and
BMODE pins. If both MMAP and BMODE are tied to VDD
(HI), the ADMC401 is placed in the so-called standalone mode
and execution starts from internal program memory ROM at
address 0x0800 following a power-on or reset. This starts execu-
tion of the internal monitor function that first performs some
initialization functions (including writing 0 to the three data
memory wait state fields) and copies a default interrupt vector
table to addresses 0x0000–0x005F of program memory RAM.
The monitor program next clears Bit 4 of the MODECTRL
register to connect the DR1A pin to the internal data receive
port (DR1) of SPORT1. In addition, Bit 5 of the MODECTRL
register is set. This connects the FL1 port of the DSP core to
the RFS1/SROM pin to act as a reset for a serial memory device.
The monitor next attempts to boot load from an external Serial
ROM (SROM) or Serial E2PROM on SPORT1 using the three
wire connection of Figure 15. This SROM or E2PROM should be
programmed with the protocol of the MAKEPROM utility
provided with the Motion Control Debugger. The monitor
program first toggles the RFS1/SROM pin of the ADMC401 to
reset the serial memory device with the following code segment:
SROMRESET:SET FL1;
TOGGLE FL1;
TOGGLE FL1;
RTS;
If a properly programmed SROM or E2PROM is connected to
SPORT1, data is clocked synchronously into the ADMC401 at
a rate of 1 Mb/s. Both internal and external program and data
memory RAM can be loaded from the SROM/E2PROM, up to
the available capacity of the serial memory device. After the
Figure 15.Basic System Configuration in Standalone
Mode
If boot loading from an SROM or E2PROM is unsuccessful, the
monitor code reconfigures SPORT1 as a UART (setting both
Bit 4 and Bit 5 of the MODECTRL register) and attempts to
receive commands from an external device on this serial port
using the DR1B pin. The monitor now waits for two bytes of
information. These bytes are received asynchronously so that no
clock is needed. The first byte is the autobaud byte and it is
used to calculate the baud rate at which data is being received.
This is known as the autobaud feature. The ADMC401 will
automatically lock onto the baud rate of the external device if
it is sent a byte of 0x70. The maximum baud rate that the
ADMC401 will lock onto is 300 kb/s for a 26 MHz CLKOUT.
The second byte of information received is the header byte that
uniquely identifies to the monitor which type of interface it is
connected to. There are six different interfaces supported on the
ADMC401. These includes:A UART boot loader such as from a Motorola 68HC11
communicating over its Serial Communications Interface
(SCI) port.A synchronous slave boot loader (the clock is external).A synchronous master boot loader (the ADMC401 provides
the clock).A UART debugger interface such as the Motion Control
Debugger from Analog Devices. The monitor then processes
commands received from the debugger over the UART
interface.A synchronous master debugger interface.A synchronous slave debugger interface.
Detailed information on these software interfaces can be
found in the “UART Boot Loader Protocol” and “UART
Debugger Protocol” appendices of the ADMC401 Developer’s
Reference Manual.
Byte-Wide EPROM Boot Mode (MMAP = BMODE = 0)If both the MMAP and BMODE pins are tied to GND, the
ADMC401 operates in the so-called EPROM Boot mode. In this
mode the entire internal program memory, or any portion of it,
can be loaded from an external source using a boot sequence
over the memory interface. To allow boot loading from inexpen-
sive 8-bit wide EPROM devices, the processor loads data one
byte at a time. The boot sequence can also be initiated after
reset by software.
Boot memory is organized into eight pages, each of which is 8k
The page length is read first and then bytes are loaded from the
top of the page downwards. This causes shorter booting times
for shorter pages. The length of the boot page is given as:
page length = (number of 24-bit PM words/8) – 1
That is, a page length of 0 causes the boot address generator to
generate byte addresses for eight words that reside in 32 sequen-
tial EPROM locations.
A PROM splitter utility (SPL21), part of the Motion Control
Debugger tool set, calculates the proper page length for your
program and orders the bytes of your program according to the
proper protocol. More detailed information about the use of
this PROM splitter utility can be found in the “Booting from
External EPROM with MMAP = BMODE = 0” chapter of the
ADMC401’s Developer’s Reference Manual.
Following a reset, if both MMAP and BMODE are LO, the
boot sequence always boot loads page 0. After reset, boot load-
ing can occur under program control from any one of up to
eight different boot pages. The boot page select field (BPAGE)
in the memory mapped System Control Register specifies which
boot page is to be loaded. To boot from a specific boot page,
first set the BPAGE bits to the desired value and set the boot
force bit (BFORCE) of the System Control Register to initiate a
boot sequence.
The ADMC401 can boot its internal program memory from a
single byte-wide CMOS EPROM such as the 27C64 or the
27C512. A low cost commodity-grade EPROM with an indus-
try-standard access time can be used. The number of wait states
for the boot memory access is selected in the BWAIT field of
the System Control Register. This field can be set to any value
from 0 to 7 to set the number of wait states. The default value
for the BWAIT field is 7 so that seven wait states are inserted
into the reset-initiated boot loading sequence.
Timing of the boot memory access is identical to that of external
program memory or external data memory accesses, except that
the active strobe is BMS rather than PMS or DMS. To address
eight pages of 8K bytes each, 16 address lines are needed. The
least significant 14 bits are output on the 14-bit address bus
(A13 to A0) while the most significant two bits are output on
the 2 MSBs of the data bus (D23 and D22) during boot memory
accesses. The data is read from the middle eight bits of the data
bus (D15 to D8).
The development tools for the ADMC401 support the creation
of EPROM target files capable of boot loading both internal and
external program and data memory.
External Memory Mode (BMODE = 0, MMAP = 1)In this mode, with BMODE tied to GND and MMAP tied to
VDD, the ADMC401 is placed in external memory mode and
there is no boot loading. The effect of this mode is that the
internal 2K bank of program memory RAM is relocated from
the bottom of memory (starting at address 0x0000) to the top of
the program memory space (at address 0x3800). In this mode,
program execution starts at external memory address 0x0000, at
which point the first instruction must be placed.
The mode in which BMODE = 1 and MMAP = 0 is not allowed
on the ADMC401 and is an illegal state. The operation of the
BUS REQUEST/GRANTThe ADMC401 can relinquish control of the external data and
address buses to an external device. The external device requests
the bus by asserting (low) the bus request signal BR. BR is an
asynchronous input and if the ADMC401 is not performing an
external access, it responds to the active BR input in the follow-
ing processor cycle by:Three-stating the data and address buses and the PMS,
DMS, BMS, RD and WR output drivers.Asserting the bus grant (BG) signal, andHalting program execution (unless Go Mode is enabled).
If Go Mode is enabled, (using the ENA G-MODE instruction)
the ADMC401 continues to execute instructions from its inter-
nal memory. It will not halt program execution until it encoun-
ters an instruction that requires an external access, which includes
an access to any motor control peripheral register. If Go Mode
is not enabled, the ADMC401 always halts before granting the
bus. The processor’s internal state is not affected by granting
the bus, and the serial ports remain active during a bus grant,
whether or not the processor core halts.
If the ADMC401 is performing an external access when the BR
signal is asserted, it will not grant the buses until the cycle after
the access completes. The entire instruction does not need to be
completed when the bus is granted. If a single instruction re-
quires two external accesses, the bus will be granted between the
two accesses. The second access is performed after BR is re-
moved. When the BR input is released, the ADMC401 releases
the BG signal, re-enables the output drivers and continues pro-
gram execution from the point where it stopped. BG is always
deasserted in the same cycle that the removal of BR is recognized.
The bus request feature operates at all times, including when
the ADMC401 is booting and when RESET is active. During
RESET, BG is asserted in the same cycle that BR is recognized.
During booting, the bus is granted after the completion of load-
ing of the current byte (including any wait states). Using the bus
request during booting is one way to bring the booting operation
under control of a host computer.
The ADMC401 has an additional output, Bus Grant Hang,
BGH, which lets it operate in a multiprocessor system with a
minimum number of wasted cycles. The BGH pin asserts when
the ADMC401 is ready to execute an instruction but is stopped
because the external bus is granted to another device. The other
device can release the bus by deasserting bus request. Once the
bus is released, the ADMC401 deasserts BG and BGH and
executes the external access.
POWER-DOWN MODESThe ADMC401 includes a power-down feature that allows the
device to enter a very low power dormant state through hard-
ware or software control. In the power-down mode:Internal clocks are disabledProcessor registers and memory contents are maintainedAbility to recover from power-down in less than 100tCKI
cyclesInterrupt support for housekeeping code before entering
ADMC401
Entering Power-DownThe power-down sequence is initiated by applying a high-to-low
transition on the PWD pin or by setting the power-down force
control bit (PDFORCE) of the SPORT1 autobuffer/power-
down control register. The DSP core then vectors to the non-
maskable power-down interrupt vector at address 0x002C. Care
must be taken to ensure that multiple power-down interrupts do
not occur or else stack overflow may result. The interrupt ser-
vice routine at address 0x002C can be used to execute any num-
ber of housekeeping instructions prior to the processor entering
the power-down mode. Typically, this is used to configure the
power-down state, disable on-chip peripherals and clear pending
interrupts. The DSP subsequently enters the power-down mode
when it executes the IDLE instruction (while PWD is asserted).
The processor may take either one or two cycles to power down,
depending on internal clock states during execution of the IDLE
instruction. All register and memory contents are maintained in
power-down. Also, all active outputs are held in whatever state
they are in before going into power-down. If an RTI instruction
is executed before the IDLE instruction, the processor returns
from the power-down interrupt and the power-down sequence is
aborted.
Exiting Power-DownThe power-down mode can be exited with the use of the PWD
pin or with the RESET pin. There are also several user-select-
able modes for startup from power-down which specify a start-
up delay as well as specify the program flow after startup. This
allows the program to resume from where it left off before
power-down, or for the program context to be cleared. Applying
a low-to-high transition on the PWD pin will take the processor
out of power-down. The amount of time it takes for the proces-
sor to come out of power-down is controllable with the delay
startup from power-down control bit (XTALDELAY, Bit 14 of
the Power-Down Control Register or SPORT1 Autobuffer
Control Register). If this bit is cleared, no additional delay over
the quick startup (100 cycles) is introduced. If this bit is set, a
delay of 4096 cycles is introduced.
The context for exiting power-down is set by Bit 12 (PUCR) of
the Power-Down Control Register. If this bit is cleared, after
exiting power-down the processor will continue to execute in-
structions following the IDLE instruction after the low-to-high
transition on the PWD pin. When the RTI instruction is en-
countered in the interrupt service routine for the power-down,
operation is returned to the main routine. If the PUCR bit is
set, for a “clear context”, the processor resumes operation from
power-down by clearing the PC, STATUS, LOOP and CNTR
registers. The IMASK and ASTAT registers are cleared and the
SSTAT goes to 0x55. The processor starts execution at address
0x0000.
Active output pins retain their states during power-down. In
addition, interrupts are latched and can be serviced if the
ADMC401 exits power-down with PUCR = 0. It is possible to
clock data into or out of the serial ports during power-down
by supplying an external serial clock. Data clocked into the
ADMC401 will remain in the RX registers. These activities
cause additional power consumption.
exiting power-down with RESET, the XTALDELAY control bit
is ignored.
Startup Time After Power-DownThe time required to exit the power-down state depends on the
method used to exit power-down. Unlike the standard ADSP-
21xx products, the XTALDIS bit of the Power-Down Register
has no effect on the ADMC401 so that it is not possible to avoid
the power drain caused by the XTAL pin toggling. When the
processor comes out of power-down by either the PWD or RESET
pins, it will begin executing after a maximum startup time of
100 CLKIN cycles as long as the clock oscillator is stable and at
the same frequency as before power-down.
If the external clock is unstable when the ADMC401 exits
power-down, the XTALDELAY control bit can be used to
insert an additional 4096 cycle delay into the startup time. This
delay can only be inserted when the ADMC401 is brought out
of power-down by the PWD pin.
If the processor is taken out of power-down by the RESET line,
and the clock is stable and at the same frequency as before
power-down, the RESET need only be held for five cycles.
The PWDACK PinThe PWDACK pin is an output that indicates when the ADMC401
is in the power-down mode. This pin is driven high by the pro-
cessor when it has powered down. It is driven low after the
processor has completed the power-up sequence. A low level on
the PWDACK pin also indicates that there is a valid CLKOUT
signal and that instruction execution has begun.
When power-down is terminated with the RESET pin or a start-
up delay is selected, a low level on the PWDACK pin only indi-
cates the start of oscillations on the CLKOUT pin. It will not
necessarily indicate the start of instruction execution.
The state of PWDACK and also the CLKOUT signal is unde-
fined during the first 100 cycles of the initial reset.
Using Power-Down as a Nonmaskable InterruptThe power-down interrupt is never masked. It is possible to use
this interrupt for other purposes, if desired. The ADMC401 does
not go into power-down until the IDLE instruction is executed.
If an RTI is executed instead, before an IDLE instruction, the
processor returns from the power-down interrupt service outline
and the power-down sequence is aborted.
THE ANALOG-TO-DIGITAL CONVERSION
SYSTEM
OVERVIEW OF ADC SYSTEMThe ADMC401 contains a fast, high accuracy, multiple-input
analog-to-digital conversion system with simultaneous sampling
capabilities. This A/D conversion system permits the fast, accu-
rate conversion of currents, voltages and other signals needed in
high performance motor control systems. A functional block
diagram of the entire ADC system is shown in Figure 16.
The ADC system permits up to eight dedicated analog inputs all
to be converted in under 2 µs (at 26 MHz) through a single 12-
bit pipeline flash ADC. The entire ADC system (including
multiplexing and the sample and hold amplifiers) operates at a
clock rate equal to a quarter of the DSP instruction rate. Analog
and BSHAN) to the inverting terminal of the two sample and
hold amplifiers (SHA) so that external signals can be correctly
biased about the nominal operating range of the ADC.
Figure 16.Functional Block Diagram of the ADC System
of the ADMC401
The basic architecture of the ADC system consists of a four-
stage pipeline architecture (the A/D core) with wideband input
sample and hold amplifiers. Excluding the last stage, each stage
of the pipeline consists of a low resolution flash A/D connected
to a switched capacitor DAC and interstage residue amplifier
(MDAC). The reside amplifier amplifies the difference between
the reconstructed DAC output and the flash input for the next
stage in the pipeline. The last stage of the pipeline simply con-
sists of a flash A/D. The pipeline architecture allows a greater
throughput rate at the expense of pipeline delay or latency. This
means that while the converter is capable of capturing a new
input sample every ADC clock cycle, it actually takes 3 1/2 ADC
clock cycles for the conversion process of any input to be fully
processed and appear at the output.
The ADC may operate in two basic conversion modes, Simulta-
neous Sampling or Sequential Sampling. The operating mode is
selected by dedicated bits in the ADCCTRL register. In the
Simultaneous Sampling mode, two analog inputs (one from each
bank) are sampled simultaneously so that VIN0 and VIN4,
VIN1 and VIN5, VIN2 and VIN6, VIN3 and VIN7 represent
four pairs of simultaneously sampled inputs. In the alternative
sequential operating mode, there is no simultaneous sampling,
and the analog inputs are sampled and converted one after the
other (i.e., VIN0 followed by VIN1 followed by VIN2, etc.). In
this mode, successive analog inputs are sampled an ADC clock
period (or four DSP clock cycles) apart.
The conversion sequence may be initiated either internally (syn-
chronized to the PWM generation) or from an external event on
the CONVST pin. In the default Simultaneous Sampling mode of
operation, the internal control logic simultaneously samples the
first pair of input signals (VIN0 and VIN4) following the con-
vert start command. Subsequently, these inputs are multiplexed
into the 12-bit analog-to-digital converter. After a delay of two
ADC clock cycles, the second pair of analog inputs (VIN1 and
VIN5) are sampled simultaneously and then multiplexed into
the ADC. This process continues until all four pairs of analog
inputs have been sampled and converted. As the conversion for
a given analog input channel is completed, the corresponding
digital number is written to a dedicated 16-bit, twos comple-
ment, left-aligned register that is memory mapped to the data
memory space of the DSP core. The ADC data register ADC0
stores the conversion result for the signal on VIN0, etc.
Following the end of conversion of each pair of analog inputs, a
dedicated bit is set in the ADCSTAT register. The result of this
highly efficient pipelined structure is that all eight ADC data
registers will contain valid conversion results less than 2 µs (at
26 MHz) after the convert start command. At this point a dedi-
cated ADC interrupt will be generated. Alternatively, if data is
required sooner, the ADCSTAT register can be polled to detect
when a given pair of analog inputs have been successfully con-
verted, except in Sequential Sampling mode.
Once the conversion sequence has been completed and all eight
ADC data registers have been updated, the entire ADC structure
automatically reverts to the Single Channel mode and continu-
ously converts the analog input on the VIN0 pin. The results of
this conversion are placed in the additional ADCXTRA register
and are updated once every ADC clock cycle. This feature could
be used to continuously monitor a single analog input on the
VIN0 pin.
There are two additional modes of operation of the ADC system
that may be used for offset and gain calibration of the entire
system. In the Offset Calibration mode, all analog inputs (VIN0
to VIN7, GAIN, ASHAN and BSHAN) are disconnected from
the inputs to the sample and hold amplifiers. Instead, both
terminals of each sample and hold amplifiers are connected
together and to the voltage reference. Following a conversion
sequence, the data in the ADC data register can be taken as a
measure of any offset in the sample and hold amplifiers and
ADC. Additionally, in the Gain Calibration mode, the dedicated
analog input GAIN is applied to the noninverting terminal of
both sample and hold amplifiers. Any number of precise exter-
nal voltages can be applied to this pin to measure and correct
for any gain errors, if required.
Along with each data output from the A/D converter, an Out-of-
Range (OTR) bit is set if the signal exceeds the permissible
input voltage span. In normal conversion, the eight OTR bits for
the eight analog inputs are stored in the ADCOTR register, with
one bit for each analog input. The OTR bit for the ADCXTRA
register is stored in the ADCSTAT register.
The ADC may use either an internally generated 2.0 V precision
reference voltage or an externally supplied reference voltage
level at the VREF pin. The operating mode is selected by the
ADMC401
CONVERT START COMMANDThe analog-to-digital conversion process of the ADMC401 may
be started by either an internal or an external command. Bit 0 of
the ADCCTRL register determines whether internal or external
convert start mode is enabled. If Bit 0 of the ADCCTRL regis-
ter is cleared, internal convert start mode is selected, and the
ADC conversion process is started on the rising edge of the
PWMSYNC signal. This results in one conversion sequence per
PWM switching period (at the start of each period) when the
PWM generation unit operates in the single update mode. In the
double update operating mode, there are two conversion se-
quences per PWM switching period (one at the start and one in
the middle of each period). In internal convert start mode, in
order to ensure correct synchronization and jitter-free operation,
it is essential that the value written to the PWMTM register be a
multiple of four. In other words, the two LSBs of the value
written to the PWMTM register must both be 0.
If Bit 0 of the ADCCTRL register is set, external convert start
mode is selected. In this mode, the conversion process is started
on the occurrence of a rising edge on the CONVST pin. Addi-
tionally, the start of conversion can be placed under software
control by externally connecting one of the programmable input/
output (PIO) lines to the CONVST pin and generating a rising
edge by writing to the appropriate bit of the PIODATA register.
By default, following reset, Bit 0 of the ADCCTRL register is
cleared so that internal convert start mode is selected.
ADC CLOCK SIGNALSThe ADC consists of a pipeline flash architecture and is clocked
at a quarter of the DSP instruction rate. All of the timing of the
ADC system (including control of the multiplexers and sample
and hold amplifiers) is regulated by this clock signal and it de-
termines the total conversion time for all of the channels as well
as the delay between sampling of successive pairs of analog
inputs. The ADC clock rate is internally fixed and may not be
changed. The period of the ADC clock, tCKADC is related to the
DSP CLKOUT period by:
A DSP rate of 26 MHz corresponds to a tCKADC of approxi-
mately 154 ns.
ANALOG INPUT CONFIGURATION AND OVERVIEWFigure 17 is a simplified model of the ADC input structure for
one channel (VIN0) of the ADC system of the ADMC401. This
model applies to all eight input channels. The internal multi-
plexers are used to switch the various analog inputs to the A/D
converter. For analog inputs VIN0 to VIN3, there is a single
common terminal (ASHAN) that is the inverting input to the
internal differential sample and hold amplifier. For the input
signals, VIN4 to VIN7, the equivalent input is BSHAN. The
value VREF (internally generated voltage reference or externally
applied voltage reference on the VREF pin) defines the maximum
input voltage to the A/D core. The minimum input voltage to
the A/D core is automatically defined as –VREF.
Figure 17.Equivalent Functional Input Circuit of ADC
System
The dc voltage on the VREF pin sets the common-mode voltage
of the A/D converter of the ADMC401. For example, when
using the internal 2.0 V reference, the input level will also be
centered about 2.0 V. The ADC inputs of the ADMC401 can
be configured for single ended operation, where the inverting
terminals (ASHAN and BSHAN) are connected directly to the
reference voltage level, and the analog inputs (VIN0 to VIN7)
are driven by analog signals with a 4.0 V p-p range. The VIN0
to VIN7 inputs are unipolar so that when operating from the
internal 2.0 V reference, these signals can range from 0 V to
4 V. The recommended single-ended input configuration for a
single analog input channel of the ADMC401 is shown in Fig-
ure 18. The input to the A/D converter must be driven by an
operational amplifier with sufficient drive strength so that the
A/D performance is not degraded. Sufficient drive strength is
the ability to drive a load of 6 pF static and 4 pF switched from
ground (capacitive) to settle within ±1.0 mV within 70 ns. In
Figure 18, the operational amplifier is shown configured as a
simple noninverting input buffer. Of course, the operational
amplifier stage could also be used to implement any necessary
level shifting and/or filtering of the input signal.
Figure 18.Typical Single-Ended Input Configuration for
ADMC401
From Figure 17, it is clear that the input to the A/D core is
simply given by:
which must satisfy the condition:
where VREF is the voltage at the VREF pin of the ADMC401
(either internally generated or externally supplied). There is an
additional limit placed on the valid operating range for the VIN0
and ASHAN inputs that is bounded by the power supply of the
ADMC401:
Simultaneous Sampling ModeThis operating mode is selected by clearing both Bits 3 and 4 of
the ADCCTRL register. In this mode, the eight analog inputs
are sampled as four pairs of simultaneously sampled inputs with
VIN0 and VIN4 being the first pair of sampled inputs, followed
by VIN1 and VIN5, followed by VIN2 and VIN6, followed by
VIN3 and VIN7. Following the rising edge of the convert start
command (either internally or externally derived), the internal
control logic simultaneously samples the VIN0 and VIN4 analog
inputs using the dual internal sample and hold amplifiers. The
internal control logic subsequently multiplexes these two signals
into the A/D core of the ADMC401. The conversion of each
signal requires 3 1/2 ADC clock cycles. Following the hold
operation, the VIN0 input is applied to the first stage of the
pipeline during the next ADC clock cycle. For the next clock
cycle, the VIN0 signal is applied to the second stage of the
pipeline and the VIN4 input is applied to the first stage of this
pipeline. In this clock cycle, the second pair of inputs is also
simultaneously sampled. This process continues to feed signals
into the A/D core until all eight channels have been converted.
The timing of this conversion sequence is shown in Figure 19.
Figure 19.ADC Timing for Simultaneous Sampling Oper-
ating Mode
In this operating mode, there is a unique status bit in the
ADCSTAT register that is set as soon as data is available for
each pair of simultaneously sampled signals. Bit 0 of the
Table II. Digital Data Format of ADCwhere AVSS is nominally at 0 V and AVDD is nominally at +5 V. Of
course, identical input constraints and requirements apply for
the other analog inputs VIN1 to VIN7 as well as the BSHAN
and GAIN inputs.
ADC DATA FORMAT AND OUT-OF-RANGE DETECTIONThe digital data from the A/D core that is stored in the dedi-
cated, memory mapped ADC registers (ADC0 to ADC7 as well
as ADCXTRA) is stored as left-aligned, twos complement data.
The output data format for normal operation in the single-
ended configuration of Figure 18 is given in Table II for one
analog input (VIN0 and ASHAN). Naturally, identical condi-
tions apply for all other analog inputs.
As well as the 12-bit data word, the A/D core produces an out-
of-range bit that is set when the analog input to the core exceeds
the allowable range (–VREF to +VREF). There is a dedicated 8-bit
ADCOTR register that stores the eight OTR bits for the A/D
conversions of the signals on the VIN0 to VIN7 inputs. There is
a single bit for each analog input; if Bit 0 of the ADCOTR register
is set, the VIN0 input has exceeded the permissible input range.
Therefore, following a complete conversion cycle, if this register
is zero, no signal has exceeded the input range. If the OTR bit
for a given analog input is set, it is possible to determine if the
signal has overranged (less than 2 × VREF) or underranged (less
than 0 V) by monitoring the MSB of the data word and the
OTR bit, as outlined in Table III.
Table III.Out-of-Range Truth Table
ADC OPERATING MODESThe A/D conversion system of the ADMC401 may be config-
ured to operate in four basic modes that are selected by Bits 3
and 4 of the ADCCTRL register. Following reset, the default
setting is that both of these bits are cleared and Simultaneous
Sampling mode is selected.Simultaneous Sampling Mode (ADCCTRL(4...3) = 00)
ADMC401ADC6 is valid and Bit 3 is set when the data in ADC3 and
ADC7 is valid. At the start of the next conversion sequence, all
bits of the ADCSTAT register are cleared. Additionally, at the
end of the complete conversion sequence (when the data in the
ADC7 register is valid), a dedicated ADC interrupt is generated.
This interrupt can be masked and controlled by the PIC block.
Depending on initial synchronization delays, the worst case total
conversion time (defined as the duration from the rising edge of
the convert start command to the generation of the ADC inter-
rupt) for all eight channels is:
tCONV = 49 × tCK
which corresponds to 1.88 µs for a DSP instruction rate of
26 MHz. Additionally, in this operating mode, the time delay
between sampling of successive pairs of analog inputs is 8tCK or
308 ns (at 26 MHz).
Sequential Sampling ModeThis operating mode is selected by setting Bit 3 and clearing
Bit 4 of the ADCCTRL register. In this operating mode, simul-
taneous sampling is abandoned and the A/D conversion se-
quence samples each analog input sequentially. Therefore, in
the first ADC clock period, VIN0 is sampled and held by the
first sample and hold amplifier. In the second clock period, the
held sample of VIN0 is applied to the first stage of the ADC
pipeline and the VIN1 signal is sampled. This process continues
until each of the analog inputs has been sequentially sampled
and converted (i.e., VIN0 followed by VIN1 followed by VIN2,
etc.). In this operating mode, the total conversion time is the
same as the Simultaneous Sampling mode. However, successive
channels are sampled at 4tCK (or 154 ns at 26 MHz) intervals.
In this mode, Bits 0 to 3 of the ADCSTAT register are all set
together when all eight conversions are complete. The interrupt
is generated, as before, when the data in the ADC7 register is valid.
Offset Calibration ModeIn order to maintain the high accuracy of the ADC system of
the ADMC401, it may be necessary to measure and compensate
for any intrinsic offset and/or gain errors in the A/D conversion
system. The Offset Calibration mode, which is selected by setting
Bit 4 and clearing Bit 3 of the ADCCTRL register, is intended
to be used for measuring any offsets in the sample and hold
amplifiers. When this mode is selected, all analog inputs (VIN0
to VIN7, ASHAN and BSHAN) are disconnected from the
inputs to the sample and hold amplifiers, and the SHA inputs
are internally connected together and to the reference voltage
(at the VREF pin). Since these connections are in effect only
during the conversion sequence, a complete conversion se-
quence must be initiated. Following the end of conversion,
the data in the ADC0 to ADC3 registers may be taken as four
separate measurements of the offset of the first sample and hold
amplifier. Similarly, the data in the ADC4 to ADC7 registers
may be taken as measurements of the offset associated with the
second sample and hold amplifier. These data values could be
averaged to obtain an offset value for each sample and hold
amplifier that could be stored and used to compensate all future
measurements. The end of conversion status bits are updated
and the interrupt is generated in a manner identical to the Si-
multaneous Sampling mode.
entire input voltage span of the A/D system. The Gain Calibra-
tion mode, selected by setting both Bits 3 and 4 of the ADCCTRL
register, is designed to offer significant user flexibility in deter-
mining the amount of gain compensation that may be required.
In this mode the dedicated GAIN input pin is internally con-
nected directly to the noninverting input of each sample and
hold amplifier. The user may apply different precise analog
voltages across the input voltage span to this pin to measure
gain errors over the operating range.
A complete conversion sequence for each different GAIN input
must be initiated. Following the end of conversion, the data in
the ADC0 to ADC3 registers may be used to calculate four
separate measurements of the gain error of the first sample and
hold amplifier. Similarly, the data in the ADC4 to ADC7 regis-
ters may be used to calculate the gain associated with the second
sample and hold amplifier. These data values could be averaged
to obtain gain error values for each sample and hold amplifier
that could be stored and used to compensate all future measure-
ments. The end of conversion status bits are updated and the
interrupt is generated in a manner identical to the Simulta-
neous Sampling mode.
ADCXTRA REGISTERFollowing the end of conversion sequence in any of the four
operating modes, the A/D system reverts to its Single Channel
mode. In this configuration, the multiplexers are set such that
the VIN0 input is continuously sampled and converted. The results
of these conversions are placed in the dedicated ADCXTRA
register that is updated with the results of a new conversion
every ADC clock period (or 154 ns at 26 MHz). This feature
permits the continuous tracking of a single analog input, if re-
quired. The OTR bit for these conversions is placed in Bit 4 of
the ADCSTAT register. No interrupt is generated following
these conversions and no other status bits are generated. The
ADCXTRA register is not updated during the conversion se-
quence of any of the four operating modes.
VOLTAGE REFERENCE OPERATIONThe ADMC401 contains an onboard bandgap reference that
can be used to provide a precise 2.0 V output for use by the A/D
system and externally on the VREF pin for biasing and level–
shifting functions. Additionally, the ADMC401 may be config-
ured to operate with an external reference applied to the VREF
pin. The SENSE pin is used to select between internal and
external references.
The actual reference voltages used by the internal ADC circuitry
of the ADMC401 appear on the CAPT and CAPB pins. For
correct operation of the internal voltage reference generation
circuitry, either with internal or external reference, it is neces-
sary to add a capacitor network between these pins, as shown in
Figure 20. A 10 µF tantalum capacitor in parallel with a 0.1 µF
ceramic is recommended as well as two 0.1 µF capacitors to
analog ground. The internal bias circuitry may take up to 15 ms
after power-up to settle. Any ADC conversions performed prior
to this may not be as accurate as possible. The start-up time
may be evaluated by measuring how long it takes for the voltage
difference between CAPT and CAPB to settle to VREF. Addi-
The SENSE pin controls whether the A/D system operates with
an internal or an external reference. For operation with the internal
reference, the SENSE pin should be tied to the REFCOM pin.
In this mode, the internally derived 2 V voltage reference ap-
pears at the VREF pin. To operate with an external voltage refer-
ence, the SENSE pin should be tied to the AVDD pin and the
external voltage reference may be applied at the VREF pin.
Figure 20.Recommended Capacitor Decoupling Networks
for the ADMC401
OPTIMIZING ADC PERFORMANCEThe optimum noise and dc linearity performance is achieved
with the largest input signal voltage span (i.e., 4 V input span)
and with matching impedance in series with each of the analog
inputs (VIN0 to VIN7, ASHAN and BSHAN). Additionally,
the operational amplifier must exhibit source impedance that is
both low and resistive, up to and beyond the sampling frequency.
When a capacitive load is switched onto the output of the opera-
tional amplifier, the output will momentarily drop, due to its
effective output impedance. As the output recovers, ringing may
occur. To remedy this situation, a series resistor can be inserted
between the op amp output and the ADC input (RS as shown in
Figure 18). Recommended configurations include using the
OP27 amplifiers with an RS of 20 Ω. Alternative recommended
op amps are the AD8051 and AD8054.
Figure 18 shows ASHAN driven by the internally generated
reference voltage at VREF. When driving ASHAN with an inter-
nally generated VREF, better performance will result if the driv-
ing impedance of ASHAN matches the driving impedance of the
other analog inputs. This can be implemented with the addition
of a second amplifier to Figure 18, between VREF and ASHAN,
to match the amplifier on VIN0.
For noise sensitive applications, it may also be beneficial to add
some shunt capacitance between the inputs (VIN0 and ASHAN
of Figure 18) and analog ground. Since this additional capaci-
tance combines with the equivalent input capacitance of the
analog inputs, a lower series resistance may be possible. The
input RC combination also provides some antialiasing filtering
on the analog inputs. To optimize performance when noise is
the primary consideration, increase the shunt capacitance as
much as the transient response of the input signal will allow.
Increasing the capacitance too much may adversely affect the
op amp’s settling time, frequency response and distortion
performance.
THE PWM CONTROLLER
OVERVIEWThe PWM generator block of the ADMC401 is a flexible, pro-
grammable, three-phase PWM waveform generator that can be
programmed to generate the required switching patterns to drive
a three-phase voltage source inverter for ac induction (ACIM)
or permanent magnet synchronous (PMSM) motor control. In
addition, the PWM block contains special functions that consid-
erably simplify the generation of the required PWM switching
patterns for control of the electronically commutated motor
(ECM) or brushless dc motor (BDCM). A special mode for
switched reluctance motors (SRM) exists as well, enabled by a
dedicated pin.
The PWM generator produces three pairs of PWM signals on
the six PWM output pins (AH, AL, BH, BL, CH and CL). The
six PWM output signals consist of three high side drive signals
(AH, BH and CH) and three low side drive signals (AL, BL and
CL). The polarity of the generated PWM signals may be pro-
grammed by the PWMPOL pin, so that either active HI or
active LO PWM patterns can be produced by the ADMC401.
The switching frequency, dead time and minimum pulsewidths
of the generated PWM patterns are programmable using respec-
tively, the PWMTM, PWMDT and PWMPD registers. In addi-
tion, three duty-cycle control registers (PWMCHA, PWMCHB
and PWMCHC) directly control the duty cycles of the three
pairs of PWM signals.
Each of the six PWM output signals can be enabled or disabled
by separate output enable bits of the PWMSEG register. In
addition, three control bits of the PWMSEG register permit
crossover of the two signals of a PWM pair for easy control of
ECM or BDCM. In crossover mode, the PWM signal destined
for the high side switch is diverted to the complementary low-
side output and the signal destined for the low side switch is
diverted to the corresponding high side output signal. In addi-
tion to ease of use of the PWM controller for ECM or BDCM,
this crossover mode can also be used to transition the PWM
signals into the overmodulation range with relative ease.
In many applications, there is a need to provide an isolation
barrier in the gate-drive circuits that turn on the power devices
of the inverter. In general, there are two common isolation tech-
niques, optical isolation using opto-isolators and transformer
isolation using pulse transformers. The PWM controller of the
ADMC401 permits mixing of the output PWM signals with a
high-frequency chopping signal to permit easy interface to such
pulse transformers. The features of this gate-drive chopping
mode can be controlled by the PWMGATE register. There is an
8-bit value within the PWMGATE register that directly controls
the chopping frequency. In addition, high frequency chopping
can be independently enabled for the high side and the low side
outputs using separate control bits in the PWMGATE register.
Also, all PWM outputs have sufficient sink and source capability
to directly drive most opto-isolators.
The PWM generator is capable of operating in two distinct
modes, single update mode or double update mode. In single
update mode the duty cycle values are programmable only once
per PWM period, so that the resultant PWM patterns are sym-
ADMC401lower harmonic distortion in three-phase PWM inverters. This
technique also permits closed loop controllers to change the
average voltage applied to the machine windings at a faster rate
and so permits faster closed loop bandwidths to be achieved.
The operating mode of the PWM block (single or double update
mode) is selected by a control bit in MODECTRL register.
The PWM generator of the ADMC401 also provides an output
pulse on the PWMSYNC pin, which is synchronized to the PWM
switching frequency. In single update mode a PWMSYNC pulse
is produced at the start of each PWM period. In double update
mode, an additional PWMSYNC pulse is produced at the mid-
point of each PWM period. The width of the PWMSYNC pulse is
programmable through the PWMSYNCWT register.
The PWM signals produced by the ADMC401 can be shut off
in a number of different ways. First, there is a dedicated asyn-
chronous PWM shutdown pin, PWMTRIP, that, when brought
LO, instantaneously places all six PWM outputs in the OFF
state (as determined by the state of the PWMPOL pin). In
addition, each of the PIO lines of the ADMC401 (PIO0 to
PIO11) can be configured to act as an additional PWM shut-
down. By setting the appropriate bit in the PIOPWM register,
the corresponding PIO line acts as an asynchronous PWM shut-
down source in a manner identical to the PWMTRIP pin. These
two hardware shutdown mechanisms are asynchronous so that
the associated PWM disable circuitry does not go through any
clocked logic, thereby ensuring correct PWM shutdown even in
the event of a loss of the DSP clock. In addition to the hardware
shutdown features, the PWM system may be shut down in soft-
ware by writing to the PWMSWT register.
Status information about the PWM system of the ADMC401 is
available to the user in the SYSSTAT register. In particular, the
state of the PWMTRIP and PWMPOL pins is available, as well
as status bits that indicates whether operation is in the first half
or the second half of the PWM period.
A functional block diagram of the PWM controller is shown in
Figure 21. The generation of the six output PWM signals on
pins AH to CL is controlled by four important blocks:The Three-Phase PWM Timing Unit, which is the core of
the PWM controller, generates three pairs of complemented
and dead time adjusted center based PWM signals.The Output Control Unit allows the redirection of the out-
puts of the Three-Phase Timing Unit for each channel to
either the high side or the low side output. In addition, the
Output Control Unit allows individual enabling/disabling of
each of the six PWM output signals.The Gate Drive Unit provides the correct polarity output
PWM signals based on the state of the PWMPOL pin. The
Gate Drive Unit also permits the generation of the high-
frequency chopping frequency and its subsequent mixing
with the PWM signals.The PWM Shutdown Controller takes care of the various
PWM shutdown modes (via the PWMTRIP pin, the PIO
lines or the PWMSWT register) and generates the correct
RESET signal for the Timing Unit.
The PWM controller is driven by a clock at the same frequency
occurrence of a rising edge of the PWMSYNC pulse and the
other is generated on the occurrence of any PWM shutdown
action.
Figure 21.Overview of the ADMC401 PWM Controller
THREE-PHASE TIMING UNITThe 16-bit three-phase timing unit is the core of the PWM
controller and produces three pairs of pulsewidth modulated
signals with high resolution and minimal processor overhead.
The outputs of this timing unit are active LO such that a low
level is interpreted as a command to turn ON the associated
power device. There are four main configuration registers
(PWMTM, PWMDT, PWMPD and PWMSYNCWT) that
determine the fundamental characteristics of the PWM outputs.
In addition, the operating mode of the PWM (single or double
update mode) is selected by Bit 6 of the MODECTRL register.
These registers, in conjunction with the three 16-bit duty cycle
registers (PWMCHA, PWMCHB and PWMCHC), control the
output of the three-phase timing unit.
PWM Switching Frequency, PWMTM RegisterThe PWM switching frequency is controlled by the 16-bit PWM
period register, PWMTM. The fundamental timing unit of the
PWM controller is tCK (DSP instruction rate). Therefore, for a
26 MHz CLKOUT, the fundamental time increment is 38.5 ns.
The value written to the PWMTM register is effectively the
number of tCK clock increments in half a PWM period. The
required PWMTM value as a function of the desired PWM
switching frequency (fPWM) is given by:
Therefore, the PWM switching period, Ts, can be written as:
For example, for a 26 MHz CLKOUT and a desired PWM
switching frequency of 10 kHz (TS = 100 µs), the correct value
to load into the PWMTM register is:
The largest value that can be written to the 16-bit PWMTM
register is 0xFFFF = 65,535, which corresponds to a minimum
PWM switching frequency of:
PWM Switching Dead Time, PWMDT RegisterThe second important parameter that must be set up in the
initial configuration of the PWM block is the switching dead
time. This is a short delay time introduced between turning off
one PWM signal (say AH) and turning on the complementary
signal, AL. This short time delay is introduced to permit the
power switch being turned off (AH in this case) to completely
recover its blocking capability before the complementary switch
is turned on. This time delay prevents a potentially destructive
short-circuit condition from developing across the dc link capacitor
of a typical voltage source inverter.
The dead time is controlled by the 10-bit PWMDT register.
There is one dead time register that controls the dead time
inserted into the three pairs of PWM output signals. The dead
time, TD, is related to the value in the PWMDT register by:
Therefore, for a 26 MHz CLKOUT, a PWMDT value of
0x00A (= 10) introduces a 770 ns delay between the turn-off
on any PWM signal (say AH) and the turn-on of its complemen-
tary signal (AL). The amount of the dead time can therefore be
programmed in increments of 2tCK (or 77 ns for a 26 MHz
CLKOUT). The PWMDT register is a 10-bit register so that its
maximum value is 0x3FF (= 1023) corresponding to a maximum
programmed dead time of:
for a CLKOUT rate of 26 MHz. Obviously, the dead time can
be programmed to be zero by writing 0 to the PWMDT register.
PWM Operating Mode, MODECTRL and SYSSTAT RegistersThe PWM controller of the ADMC401 can operate in two
distinct modes; single update mode and double update mode.
The operating mode of the PWM controller is determined by
the state of Bit 6 of the MODECTRL register. If this bit is
cleared, the PWM operates in the single update mode. Setting
Bit 6 places the PWM in the double update mode. By default,
following reset, Bit 6 of the MODECTRL register is cleared so
that the default operating mode is in single update mode.
In single update mode, a single PWMSYNC pulse is produced
in each PWM period. The rising edge of this signal marks the
start of a new PWM cycle and is used to latch new values from
the PWM configuration registers (PWMTM, PWMDT, PWMPD
and PWMSYNCWT) and the PWM duty cycle registers
duty cycles of the PWM signals can be updated only once per
PWM period at the start of each cycle. The result is that PWM
patterns that are symmetrical about the midpoint of the switch-
ing period are produced.
In double update mode, an additional PWMSYNC pulse is
produced at the midpoint of each PWM period. The rising edge
of this new PWMSYNC pulse is again used to latch new values
of the PWM configuration registers, duty cycle registers and the
PWMSEG register. As a result it is possible to alter the charac-
teristics (switching frequency, dead time, minimum pulsewidth
and PWMSYNC pulsewidth) as well as the output duty cycles
at the midpoint of each PWM cycle. Consequently, it is possible
with double update mode to produce PWM switching patterns
that are not symmetrical about the midpoint of the period (asym-
metrical PWM patterns).
In the double update mode, it may be necessary to know whether
operation at any point in time is in either the first half or the
second half of the PWM cycle. This information is provided by
Bit 3 of the SYSSTAT register, which is cleared during opera-
tion in the first half of each PWM period (between the rising
edge of the original PWMSYNC pulse and the rising edge of the
new PWMSYNC pulse introduced in double update mode). Bit
3 of the SYSSTAT register is set during operation in the second
half of each PWM period. This status bit allows the user to make a
determination of the particular half-cycle during implementation
of the PWMSYNC interrupt service routine, if required.
The advantage of the double update mode is that lower harmonic
voltages can be produced by the PWM process and faster
control bandwidths are possible. However, for a given PWM
switching frequency, the PWMSYNC pulses occur at twice the
rate in the double update mode. Since new duty cycle values
must be computed in each PWMSYNC interrupt service routine,
there is a larger computational burden on the DSP in the double
update mode. Alternatively, the same PWM update rate may be
maintained at half the switching frequency to give lower switch-
ing losses.
Width of the PWMSYNC Pulse, PWMSYNCWT RegisterThe PWM controller of the ADMC401 produces an output
PWM synchronization pulse at a rate equal to the PWM switch-
ing frequency in single update mode and at twice the PWM
frequency in the double update mode. This pulse is available
for external use at the PWMSYNC pin. The width of this
PWMSYNC pulse is programmable by the 8-bit read/write
PWMSYNCWT register. The width of the PWMSYNC pulse,
TPWMSYNC, is given by:
so that the width of the pulse is programmable from tCK to 256 ×
tCK (corresponding to 38.5 ns to 9.85 µs for a CLKOUT rate of
26 MHz). Following a reset, the PWMSYNCWT register con-
tains 0x27 (= 39) so that the default PWMSYNC width is
1.54 µs, again for a 26 MHz CLKOUT.
PWM Duty Cycles, PWMCHA, PWMCHB, PWMCHC
RegistersThe duty cycles of the six PWM output signals on Pins AH to
CL are controlled by the three 16-bit read/write duty cycle
ADMC401cycle of the signals on CH and CL. The duty cycle registers are
programmed in integer counts of the fundamental time unit,
tCK, and define the desired on-time of the high side PWM signal
produced by the three-phase timing unit over half the PWM pe-
riod. The switching signals produced by the three-phase timing
unit are also adjusted to incorporate the programmed dead time
value in the PWMDT register. The three-phase timing unit
produces active LO signals so that a LO level corresponds to a
command to turn on the associated power device.
A typical pair of PWM outputs (in this case for AH and AL)
from the timing unit are shown in Figure 22 for operation in
single update mode. All illustrated time values indicate the
integer value in the associated register and can be converted to
time by simply multiplying by the fundamental time increment,
tCK. First, it is noted that the switching patterns are symmetrical
about the midpoint of the switching period in this single up-
date mode since the same values of PWMCHA, PWMTM and
PWMDT are used to define the signals in both half cycles of the
period. It can be seen how the programmed duty cycles are
adjusted to incorporate the desired dead time into the resultant
pair of PWM signals. Clearly, the dead time is incorporated by
moving the switching instants of both PWM signals (AH and
AL) away from the instant set by the PWMCHA register. Both
switching edges are moved by an equal amount (PWMDT ×
tCK) to preserve the symmetrical output patterns. Also shown is
the PWMSYNC pulse whose width is set by the PWMSYNCWT
register and Bit 3 of the SYSSTAT register, which indicates
whether operation is in the first or second half cycle of the PWM
period.
Figure 22.Typical PWM Outputs of Three-Phase Timing
Unit in Single Update Mode (Active LO Waveforms)
The resultant on-times of the PWM signals over the full PWM
period (two half periods) produced by the PWM timing unit,
and illustrated in Figure 22, may be written as:
and the corresponding duty cycles are:
Obviously negative values of TAH and TAL are not permitted and
the minimum permissible value is zero, corresponding to a 0%
duty cycle. In a similar fashion, the maximum value is TS, corre-
sponding to a 100% duty cycle.
The output signals from the timing unit for operation in double
update mode are shown in Figure 23. This illustrates a com-
pletely general case where the switching frequency, dead time
and duty cycle are all changed in the second half of the PWM
period. Of course, the same value for any or all of these quanti-
ties could be used in both halves of the PWM cycle. However, it
can be seen that there is no guarantee that symmetrical PWM
signals will be produced by the timing unit in this double update
mode. Additionally, it is seen that the dead time is inserted into
the PWM signals in the same way as in the single update mode.
PWMCHA2
PWMCHA1
PWMSYNC
SYSSTAT (3)Figure 23.Typical PWM Outputs of Three-Phase Timing
Unit in Double Update Mode (Active LO Waveforms)
In general the on-times of the PWM signals over the full PWM
period in double update mode can be defined as:
where the subscript 1 refers to the value of that register during
the first half cycle and the subscript 2 refers to the value during
the second half cycle. The corresponding duty cycles are:
since for the completely general case in double update mode,
the switching period is given by:
Again, the values of TAH and TAL are constrained to lie between
zero and TS. Similar PWM signals to those illustrated in Figure
22 and Figure 23 can be produced on the BH, BL, CH and CL
outputs by programming the PWMCHB and PWMCHC registers
in a manner identical to that described for PWMCHA.
Special Consideration for PWM Operation in
OvermodulationThe PWM Timing Unit is capable of producing PWM signals
with variable duty cycle values at the PWM output pins. At the
extremities of the modulation process, both 0% and 100%
