ADMC201AP Fast Delivery |IC PHOENIX CO.,LIMITED

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ADMC201AP
Motion Coprocessor
FUNCTIONAL BLOCK DIAGRAM
Motion Coprocessor
FEATURES
Analog Input Block
11-Bit Resolution Analog-to-Digital (A/D) Converter
7 Single-Ended (SE) Analog Inputs
4 Simultaneously Sampled Analog Inputs
Expansion with 4 Multiplexed Inputs
3.2 �s Conversion Time/Channel
0 V–5 V Analog Input Range
Internal 2.5 V Reference
PWM Synchronized Sampling Capability
12-Bit PWM Timer Block
Three-Phase Center-Based PWM
1.5 kHz–25 kHz PWM Switching Frequency Range
Programmable Deadtime
Programmable Pulse Deletion
PWM Synchronized Output
External PWM Shutdown
Vector Transformation Block
12-Bit Vector Transformations
Forward and Reverse Clarke Transformations
Forward and Reverse Park Rotations
2.9 �s Transformation Time
Programmable Digital I/O Port
6-Bit Configurable Digital I/O
Change of State Interrupt Support
DSP & Microcontroller Interface
12 Bit Memory Mapped Registers
Twos Complement Data Format
6.25 MHz to 25 MHz Operating Clock Range
68-Pin PLCC Package
Single 5 V DC Power Supply
Industrial Temperature Range
GENERAL DESCRIPTION
The ADMC201 is a motion coprocessor that can be used with
either microcontrollers or digital signal processors (DSP). It
provides the functionality that is required to implement a digital
control system. In a typical application, the DSP or micro-
controller performs the control algorithms (position, speed,
torque and flux loops) and the ADMC201 provides the neces-
sary motor control functions: analog current data acquisition,
vector transformation, digital inputs/outputs, and PWM drive
signals.
PRODUCT HIGHLIGHTS
Simultaneous Sampling of Four Inputs
A four channel sample and hold amplifier allows three-phase
motor currents to be sampled simultaneously, reducing errors
from phase coherency. Sample and hold acquisition time is
1.6 µs and conversion time per channel is 3.2 µs (using a 12.5MHz
system clock).
Flexible Analog Channel Sequencing
The ADMC201 supports acquisition of 2, 3, or 4 channels per
group. Converted channel results are stored in registers and
the data can be read in any order. The sampling and conversion
time for two channels is 8 µs, three channels is 11.2 µs, and four
channels is 14.4 µs (using a 12.5 MHz system clock).
Embedded Control Sequencer
The embedded control sequencer off-loads the DSP or micro-
processor, reducing the instructions required to read analog
input channels, control PWM timers and perform vector trans-
formations. This frees the host processor for performing control
algorithms.
Fast DSP/Microprocessor Interface
The high speed digital interface allows direct connection to 16-bit
digital signal processors and microprocessors. The ADMC201
has 12 bit memory mapped registers with twos complement
data format and can be mapped directly into the data memory
map of a DSP. This allows for a single instruction read and write
interface.
Integration
The ADMC201 integrates a four channel simultaneous sampling
analog-to-digital converter, four channel analog multiplexer,
analog reference, vector transformation, six digital inputs/outputs,
and three-phase PWM timers into a 68-pin PLCC. Integration
reduces cost, board space, power consumption, and design and
test time.
REV. B
ANALOG INPUTS
LOGIC
VECTOR TRANSFORMATION
INTERNAL SYSTEM CLOCK
ADMC201–SPECIFICATIONS
(VDD = +5 V � 5%; AGND = DGND = 0 V; REFIN = 2.5 V; External Clock = 12.5 MHz;
TA = –40�C to +85�C unless otherwise noted)
Table I.Timing Specifications (VDD = 5 V, � 5%; TA = –40�C to +85�C)
NOTEAll WRITES to the ADMC201 must occur within 1 System Clock Cycle (0 wait states).
Figure 1.Clock Input Timing
Figure 2.Reset Input Timing
ADMC201
ORDERING GUIDE
Figure 4.Read Cycle Timing Diagram
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . –0.3 V to +7.0 V
Digital Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD
Analog Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD
Analog Reference Input Voltage . . . . . . . . . . . . –0.3 V to VDD
Digital Output Voltage Swing . . . . . . . . . . . . . . –0.3 V to VDD
Analog Reference Output Swing . . . . . . . . . . . . –0.3 V to VDD
Operating Temperature . . . . . . . . . . . . . . . . . –40°C to +85°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +280°C
*Stresses greater than those listed above may cause permanent damage to the
device. These are stress ratings only, and functional operation of the device at
these or any other conditions greater than those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADMC201 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
PIN DESIGNATIONS
PIN CONFIGURATION
VDD
DGND
DGND
DGND
PWMSYNC
STOP
DGND
VDD
VDD
RESET
CONVST
IRQ
VDD
DGND
CLK
VDD
D11D4D6D5D1D2
D10PIO3PIO5PIO2
PIO1
PIO0
PIO4
ADMC201
Interrupt Driven Method
Interrupts can be used to indicate the end of conversion for a
group of channels. Before beginning any A/D conversions, Bit 7
of the SYSCTRL register must be set to 1 to enable A/D con-
version interrupts. Then, when an A/D conversion is complete,
an interrupt will be generated. After an interrupt is detected,
Bit 0 of the SYSSTAT register must be checked to determine if
the A/D converter was the source. Reading the SYSSTAT reg-
ister automatically clears the interrupt flag bits.
Software Timing Method
An alternative method is to use the DSP or microcontroller to
keep track of the amount of time elapsed between CONVST
and the expected completion time (n × tCONV).
Reading Results
The 11-bit A/D conversion results for channels U, V, W and
AUX are stored in the ADCU, ADCV, ADCW and ADCAUX
registers respectively. The twos complement data is left justified
and the LSB is set to zero. The relationship between input volt-
age and output coding is shown in Figure 5.
OUTPUT
CODEFULL-SCALE
TRANSITION2.55V–1LSB
INPUT VOLTAGE
FS = 5V
LSB =5V
2048
Figure 5.Transfer Function
Sample and Hold
After powering up the ADMC201, bring the RESET pin low for
a minimum of two clock cycles in order to enable A/D conversions.
Before initiating the first conversion (CONVST) after a reset,
the SHA time of 20 system clock cycles must occur. A conversion
is initiated by bringing CONVST high for a minimum of one
system clock cycle. The SHA goes into hold mode at the falling
edge of clock.
Following completion of the A/D conversion process, a minimum
of 20 system clock cycles are required before initiating another
conversion in order to allow the sample and hold circuitry to
reacquire the input signals.
If a CONVST is initiated before the 20 clock cycles have elapsed,
the embedded control sequencer will delay conversion until this
requirement is met.
ANALOG INPUT BLOCK
The ADMC201 contains an 11-bit resolution, successive approxi-
mation analog-to-digital (A/D) converter with twos complement
output data format. The analog input range is ±2.5 V (0 V–5 V)
with a 2.5 V offset as defined by REFIN. The on-chip 2.5 V ±
5% reference is utilized by connecting the REFOUT pin to the
REFIN pin.
The input stage to the A/D converter is a four channel SHA
which allows the four channels (U, V, W and AUX) to be held
simultaneously and then sequentially digitized. The auxiliary
input (AUX) is fed by a four channel multiplexer that allows the
channels AUX0, AUX1, AUX2 and AUX3 to be individually
converted along with the primary channels U, V and W. The
auxiliary inputs are ideal for reading slower changing variables
such as bus voltage and temperature. The A/D conversion time
is determined by the system clock frequency, which can range
from 6.25 MHz to 12.5 MHz. The Sample and Hold (SHA)
acquisition time is 20 system clock cycles and is independent of
the number of channels sampled and/or digitized. Forty system
clock cycles are required to complete each A/D conversion. The
analog channel sampling is flexible and is programmable
through the SYSCTRL register. The minimum number of
channels per conversion is two. The throughput time of the
analog acquisition block can be calculated as follows:
where
tAA = analog acquisition time,
n = # channels,
tSHA = SHA acquisition time (20 × system clock period),
tCONV = conversion time (40 × system clock period) per channel.
A/D Conversions are initiated via the CONVST pin. A syn-
chronizing pulse (PWMSYNC) is provided at the beginning of
each PWM cycle. This pulse can be used to synchronize the
A/D conversion process to the PWM switching frequency.
Operating the A/D Converter
The A/D converter can be set up to convert a sequence of channels
as defined in the SYSCTRL register (see Table VI). The default
channel select mode after RESET is to convert channels V and
W only. This is two-/three-phase mode. Three-/three-phase
mode converts channels U, V, W, and/or AUX. Three-/three-
phase mode is selected by writing a 1 to Bit 3 of the SYSCTRL
register. After the conversion process is complete, the channels
can be read in any order.
There are two methods that can be used to indicate when the
A/D conversions are completed and the data is ready: interrupt
driven and software timing.
PWM TIMER BLOCK OVERVIEW
The PWM timers have 12-bit resolution and support program-
mable pulse deletion and deadtime. The ADMC201 generates
three center-based signals A, B and C based upon user-supplied
duty cycles values. The three signals are then complemented
and adjusted for programmable deadtime to produce the six
outputs. The ADMC201 PWM master switching frequency can
range from 2.5 kHz to 20 kHz, when using a 10 MHz system
clock. The master frequency selection is set as a fraction of the
PWMTM register. If the system clock is 10 MHz, then the
minimum edge resolution available is 100 ns.
The output format of the PWM block is active LO. There is an
external input to the PWM timers (STOP) that will disable all
six outputs within one system clock when the input is HIGH.
The ADMC201 has a PWM Synchronization output
(PWMSYNC) which brings out the master switching frequency
from the PWM timers. The width of the PWMSYNC pulse is
equal to one system clock cycle. For example, if the system clock
is 10 MHz, the PWMSYNC width would be equal to 100 ns.
PWM Master Switching Period Selection
The switching time is set by the PWMTM register which should
be loaded with a value equal to the system clock frequency
divided by the desired master switching frequency. For ex-
ample, if the desired switching frequency is 8 kHz and the
system clock frequency is 10 MHz, then the PWMTM register
should be loaded with 1250 (10 MHz/8 kHz). The PWMCHA,
PWMCHB and PWMCHC registers are loaded with the
desired on-time and their values would be calculated as a ratio
of the PWMTM register value. Note: Desired Pulse Density =
(PWMCHx register)/( PWMTM register).
The beginning of each PWM cycle is marked by the PWMSYNC
signal. New values of PWMCHA, PWMCHB and PWMCHC
must all be loaded into their respective registers at least four sys-
tem clock cycles before the beginning of a new PWM cycle. All
three registers must be updated for any of them to take effect.
New PWM on/off times are calculated during these four clock
cycles and therefore the PWMCHA, PWMCHB and PWMCHC
registers must be loaded before this time. If this timing require-
ment is not met, then the PWM outputs may be invalid during
the next PWM cycle.
PWM Example
The following example uses a system clock speed of 10 MHz.
The desired PWM master switching frequency is 8 kHz and the
desired on-time for the timers A, B and C are 25%, 50% and
10% respectively. The values for the PWMCHA, PWMCHB
and PWMCHC registers must be calculated as ratios of the
PWMTM register (1250 in this example). To achieve these
duty cycles, load the PWMCHA register with 313 (1250 ×
0.25), PWMCHB with 625 (1250 × 0.5) and PWMCHC with
125 (1250 × 0.1).
Programmable Deadtime
With perfectly complemented PWM drive signals and nonideal
switching characteristics of the power devices, both transistors
in a particular leg might be switched on at the same time, result-
ing in either a power supply trip, inverter trip or device
destruction. In order to prevent this, a delay must be intro-
duced between the complemented signal edges. For example,
the rising edge of AP occurs before the falling edge of A, and the
falling edge of the complemented A occurs after the rising edge
of A. This capability is known as programmable deadtime.
The ADMC201 programmable deadtime value is loaded into
the 7-bit PWMDT register, in which the LSB is set to zero in-
ternally, which means the deadtime value is always divisible by
two. With a 10 MHz system clock, the 0–126 range of values in
PWMDT yield a range of deadtime values from 0 µs to 12.6 µs
in 200 ns steps. Figure 6 shows PWM timer A with a program-
mable deadtime of PWMDT.
PWMCHA - PWMDT
PWMTM
PWMCHA + PWMDT
Figure 6.Programmable Deadtime Example
Pulse Deletion
The pulse deletion feature prevents a pulse from being gener-
ated when the user-specified duty cycle results in a pulse
duration shorter than the user-specified deletion value. The
pulse deletion value is loaded into the 7-bit register PWMPD.
When the user-specified on-time for a channel would result in a
calculated pulse width less than the value specified in the
PWMPD register, then the PWM outputs for that channel
would be set to full off (0%) and its prime to full on (100%).
This is valid for A, AP, B, BP, C and CP. This feature would
be used in an environment where the inverter’s power transis-
tors have a minimum switching time. If the user-specified duty
cycle would result in a pulse duration shorter than the minimum
switching time of the transistors, then pulse deletion should be
used to prevent this occurrence. With a 10 MHz system clock,
the 0–127 range of values in PWMPD yield a range of deadtime
values from 0 µs to 12.7 µs in 100 ns steps.
External PWM Shutdown
There is an external input pin (STOP) to the PWM timers that
will disable all six outputs when it goes HIGH. When the STOP
pin goes HIGH, the PWM timer outputs will all go HIGH
within one system clock cycle. When the STOP pin goes LOW,
the PWM timer outputs are re-enabled within one system clock
cycle. If external PWM shutdown isn't required, tie the STOP
pin LOW.
ADMC201
VECTOR TRANSFORMATION BLOCK OVERVIEW
The Vector Transformation Block performs both Park and
Clarke coordinate transformations to control a three-phase
motor (Permanent Magnet Synchronous Motor or Induction
Motor) via independent control of the decoupled rotor torque
and flux currents. The Park & Clarke transformations combine
to convert three-phase stator current signals into two orthogonal
rotor referenced current signals Id and Iq. Id represents the flux
or magnetic field current and Iq represents the torque generat-
ing current. The Id and Iq current signals are used by the
processor’s motor torque control algorithm to calculate the re-
quired direct Vd and quadrature Vq voltage components for the
motor. The forward Park and Clarke transformations are used
to convert the Vd and Vq voltage signals in the rotor reference
frame to three-phase voltage signals (U, V, W) in the stator ref-
erence frame. These are then scaled by the processor and
written to the ADMC201’s PWM registers in order to drive the
inverter. The figures below illustrate the Clarke and Park
Transformations respectively.
120°
120°
120°
Three-Phase Equivalent
Stator Currents Two-Phase Currents
Figure 7.Reverse Clarke Transformation
Rotating Stationary
Reference Frame Reference Frame
Figure 8.Reverse Park TransformationVy
Stationary Rotating
Reference Frame Reference Frame
Figure 9.Forward Park Transformation
120°
Equivalent Three-Phase Stator
Two-Phase Voltage Voltage
Figure 10.Forward Clarke Transformation
Operating/Using the Vector Transformation Block
After powering up the ADMC201, RESET must be driven
low for a minimum of two clock cycles to enable vector
transformations.
The vector transformation block can perform either a forward or
reverse transformation.
Reverse Transformation is defined by the following operations:
(a) Clarke: 3-phase current signals to 2-phase current signals
followed by (b) Park: 2-phase current signals cross multiplied by
sin ρ, cos ρ which effectively measures the current components
with respect to the rotor (stationary) where ρ is the electrical
angle of the rotor field with respect to the stator windings.
Forward transformation is defined by the following operations:
(a) Park: 2-phase voltage signals cross multiplied by sin ρ, cos ρ fol-
lowed by (b) Clarke: 2-phase to 3-phase voltage signal conversion.
In order to provide maximum flexibility in the target system, the
ADMC201 operates in an asynchronous manner. This means
that the functional blocks (analog input, reverse transformation,
forward transformation and PWM timers) operate indepen-
dently of each other. The reverse and forward vector
transformation operations cannot occur simultaneously. All
vector transformation registers, except for RHO/RHOP, are
twos complement. RHO/RHOP are unsigned ratios of 360°.
For example, 45° would be 45/360 × 212.
Performing a Reverse Transformation
A reverse transformation is initiated by writing to the reverse
rotation angle register RHO and operates on the values in the
PHIP1, PHIP2 and PHIP3 registers. When the reverse trans-
formation is in 2/3 mode, PHIP1 is calculated from PHIP2 and
PHIP3. This is used in systems where only two-phase currents
are measured. The reverse transformation 2/3 mode is set by
clearing Bit 10 in the SYSCTRL register and is the default
mode after RESET.
In order to perform a reverse transformation, first write to the
PHIP2 and PHIP3 registers, and to the PHIP1 register if not in
2/3 mode. Then initiate the transformation by writing the re-
verse rotation angle to the RHO register.
The reverse rotation will be completed in 37 system clock cycles
after the rotation is initiated. If Bit 6 of the system control reg-
ister is set, then an interrupt will be generated on completion.
When an interrupt occurs, the user must check Bit 1 of the
SYSSTAT register to determine if the vector transformation
block was the source of the interrupt.

Partno	Mfg	Dc	Qty	Available	Descript
ADMC201AP	AD	N/a	2	avai	Motion Coprocessor