ADMC200AP Fast Delivery |IC PHOENIX CO.,LIMITED

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ADMC200AP
Motion Coprocessor
FUNCTIONAL BLOCK DIAGRAM
Motion Coprocessor
FEATURES
Analog Input Block
11-Bit Resolution Analog-to-Digital (A/D) Converter
4 Single-Ended Simultaneously Sampled Analog Inputs
3.2 �s Conversion Time/Channel
0 V–5 V Analog Input Range
Internal 2.5 V Reference
PWM Synchronized Sampling Capability
12-Bit PWM Timer Block
Three-Phase Center-Based PWM
1.5 kHz–25 kHz PWM Switching Frequency Range
Programmable Deadtime
Programmable Pulse Deletion
PWM Synchronized Output
External PWM Shutdown
Vector Transformation Block
12-Bit Vector Transformations
Forward and Reverse Clarke Transformations
Forward and Reverse Park Rotations
2.9 �s Transformation Time
DSP & Microcontroller Interface
12-Bit Memory Mapped Registers
Twos Complement Data Format
6.25 MHz to 25 MHz Operating Clock Range
68-Lead PLCC Package
Single 5 V DC Power Supply
Industrial Temperature Range
GENERAL DESCRIPTION
The ADMC200 is a motion coprocessor that can be used with
either microcontrollers or digital signal processors (DSP). It
provides the functionality that is required to implement a digital
control system. In a typical application, the DSP or micro-
controller performs the control algorithms (position, speed,
torque and flux loops) and the ADMC200 provides the neces-
sary motor control functions: analog current data acquisition,
vector transformation, and PWM drive signals.
PRODUCT HIGHLIGHTS
Simultaneous Sampling of Four Inputs
A four channel sample and hold amplifier allows three-phase
motor currents to be sampled simultaneously, reducing errors
from phase coherency. Sample and hold acquisition time is
1.6 µs and conversion time per channel is 3.2 µs (using a 12.5MHz
system clock).
Flexible Analog Channel Sequencing
The ADMC200 support acquisition of 2, 3, or 4 channels per
group. Converted channel results are stored in registers and the
data can be read in any order. The sampling and conversion
time for two channels is 8 µs, three channels is 11.2 µs, and four
channels is 14.4 µs (using a 12.5 MHz system clock).
Embedded Control Sequencer
The embedded control sequencer off-loads the DSP or micro-
processor, reducing the instructions required to read analog in-
put channels, control PWM timers and perform vector trans-
formations. This frees the host processor for performing control
algorithms.
Fast DSP/Microprocessor Interface
The high speed digital interface allows direct connection to
16-bit digital signal processors and microprocessors. The
ADMC200 has 12 bit memory mapped registers with twos
complement data format and can be mapped directly into the
data memory map of a DSP. This allows for a single instruction
read and write interface.
Integration
The ADMC200 integrates a four channel simultaneous sam-
pling analog-to-digital converter, analog reference, vector trans-
formation, and three-phase PWM timers into a 68-lead PLCC.
Integration reduces cost, board space, power consumption, and
design and test time.
REV. B
ADMC200–SPECIFICATIONS
(VDD = +5 V � 5%; AGND = DGND = 0 V; REFIN = 2.5 V; External Clock =
12.5 MHz; TA = –40�C to +85�C unless otherwise noted)
ANALOG INPUTS
LOGIC
Table I.Timing Specifications (VDD = 5V � 5%; TA = –40�C to +85�C)
NOTEAll WRITES to the ADMC200 must occur within 1 system clock cycle (0 wait states).
Figure 1.Clock Input Timing
Figure 2.Reset Input Timing
ADMC200
ORDERING GUIDE
Figure 4.Read Cycle Timing Diagram
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . –0.3 V to +7.0 V
Digital Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD
Analog Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD
Analog Reference Input Voltage . . . . . . . . . . . . –0.3 V to VDD
Digital Output Voltage Swing . . . . . . . . . . . . . . –0.3 V to VDD
Analog Reference Output Swing . . . . . . . . . . . . –0.3 V to VDD
Operating Temperature . . . . . . . . . . . . . . . . . –40°C to +85°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +280°C
*Stresses greater than those listed above may cause permanent damage to the
device. These are stress ratings only; functional operation of the device at these or
any other conditions greater than those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADMC200 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
PIN DESIGNATIONS
PIN CONFIGURATION
VDD
DGND
DGND
DGND
PWMSYNC
STOP
DGND
VDD
SGNDAGNDAGNDV
REFIN
AUX
DGNDDGND
DGND
DGND
VDD
RESET
CONVST
IRQ
VDD
DGND
CLK
VDDNCNCNCD11D7D4D6D5D1NCNCD2D3D10
ADMC200
registers respectively. The twos complement data is left justified
and the LSB is set to zero. The relationship between input volt-
age and output coding is shown in Figure 5.
OUTPUT
CODEFULL-SCALE
TRANSITION2.55V–1LSB
INPUT VOLTAGE
FS = 5V
LSB =5V
2048
Figure 5.Transfer Function
Sample and Hold
After powering up the ADMC200, bring the RESET pin low for
a minimum of two clock cycles in order to enable A/D conver-
sions. Before initiating the first conversion (CONVST) after a
reset, the SHA time of 20 system clock cycles must occur. A
conversion is initiated by bringing CONVST high for a mini-
mum of one system clock cycle. The SHA goes into hold mode
at the falling edge of clock.
Following completion of the A/D conversion process, a mini-
mum of 20 system clock cycles are required before initiating an-
other conversion in order to allow the sample and hold circuitry
to reacquire the input signals.
If a CONVST is initiated before the 20 clock cycles have
elapsed, the embedded control sequencer will delay conversion
until this requirement is met.
PWM TIMER BLOCK OVERVIEW
The PWM timers have 12-bit resolution and support program-
mable pulse deletion and deadtime. The ADMC200 generates
three center-based signals A, B, and C based upon user-supplied
duty cycles values. The three signals are then complemented
and adjusted for programmable deadtime to produce the six
outputs. The ADMC200 PWM master switching frequency can
range from 2.5 kHz to 20 kHz, when using a 10 MHz system
clock. The master frequency selection is set as a fraction of the
PWMTM register. If the system clock is 10 MHz, then the
minimum edge resolution available is 100 ns.
The output format of the PWM block is active LO. There is an
external input to the PWM timers (STOP) that will disable all
six outputs within one system clock when the input is HIGH.
The ADMC200 has a PWM Synchronization output
(PWMSYNC) which brings out the master switching frequency
from the PWM timers. The width of the PWMSYNC pulse is
equal to one system clock cycle. For example, if the system clock
is 10 MHz, the PWMSYNC width would be equal to 100 ns.
PWM Master Switching Period Selection
The switching time is set by the PWMTM register which should
be loaded with a value equal to the system clock frequency
divided by the desired master switching frequency. For ex-
ANALOG INPUT BLOCK
The ADMC200 contains an 11-bit resolution, successive approxi-
mation analog-to-digital (A/D) converter with twos complement
output data format. The analog input range is ±2.5 V (0 V–5 V)
with a 2.5 V offset as defined by REFIN. The on-chip 2.5 V ±
5% reference is utilized by connecting the REFOUT pin to the
REFIN pin.
The A/D conversion time is determined by the system clock fre-
quency, which can range from 6.25 MHz to 12.5 MHz. The
Sample and Hold (SHA) acquisition time is 20 system clock
cycles and is independent of the number of channels sampled
and/or digitized. The input stage to the A/D converter is a four
channel SHA which allows the four channels to be held simulta-
neously and then sequentially digitized. Forty system clock
cycles are required to complete each A/D conversion. The ana-
log channel sampling is flexible and is programmable through
the SYSCTRL register. The minimum number of channels per
conversion is two. The throughput time of the analog acquisi-
tion block can be calculated as follows:
where
tAA = analog acquisition time,
n = # channels,
tSHA = SHA acquisition time (20 × system clock period),
tCONV = conversion time (40 × system clock period) per channel.
A/D Conversions are initiated via the CONVST pin. A syn-
chronizing pulse (PWMSYNC) is provided at the beginning of
each PWM cycle. This pulse can be used to synchronize the
A/D conversion process to the PWM switching frequency.
Operating the A/D Converter
The A/D converter can be set up to convert a sequence of chan-
nels as defined in the SYSCTRL register (see Table V). Always
write 0 to both Bits 0 and 1 of the SYSCTRL register. The de-
fault channel select mode after RESET is to convert channels V
and W only. This is two-/three-phase mode. Three-/three-phase
mode converts channels U, V, W and/or AUX. Three-/three-
phase mode is achieved by writing a 1 to Bit 3 of the SYSCTRL
register. After the conversion process is complete, the channels
can be read in any order.
There are two methods that can be used to indicate when the
A/D conversions are completed and the data is ready: interrupt
driven and software timing.
Interrupt Driven Method
Interrupts can be used to indicate the end of conversion for a
group of channels. Before beginning any A/D conversions, Bit 7
of the SYSCTRL register must be set to 1 to enable A/D con-
version interrupts. Then, when an A/D conversion is complete,
an interrupt will be generated. After an interrupt is detected
Bit 0 of the SYSSTAT register must be checked to determine if
the A/D converter was the source. Reading the SYSSTAT reg-
ister automatically clears the interrupt flag bits.
Software Timing Method
An alternative method is to use the DSP or microcontroller to
keep track of the amount of time elapsed between CONVST
and the expected completion time (n × tCONV).

Partno	Mfg	Dc	Qty	Available	Descript
ADMC200AP	AD	N/a	80	avai	Motion Coprocessor