ADM8690AN ,Microprocessor Supervisory CircuitsSpecifications subject to change without notice.ABSOLUTE MAXIMUM RATINGS*ORDERING GUIDE(T = +25°C u ..
ADM8690ARN ,Microprocessor Supervisory CircuitsSpecifications subject to change without notice.ABSOLUTE MAXIMUM RATINGS*ORDERING GUIDE(T = +25°C u ..
ADM8691AN ,Microprocessor Supervisory CircuitsSPECIFICATIONSMAXParameter Min Typ Max Units Test Conditions/CommentsBATTERY BACKUP SWITCHINGV Oper ..
ADM8691ARW ,Microprocessor Supervisory CircuitsSPECIFICATIONSMAXParameter Min Typ Max Units Test Conditions/CommentsBATTERY BACKUP SWITCHINGV Oper ..
ADM8692AN ,Microprocessor Supervisory CircuitsFEATURES FUNCTIONAL BLOCK DIAGRAMSUpgrade for ADM690/ADM695, MAX690–MAX695Specified Over Temperatur ..
ADM8692ARN ,Microprocessor Supervisory CircuitsMicroprocessoraSupervisory CircuitsADM8690–ADM8695
AIC3842CN , Current-Mode PWM Controller
AIC3843CNTB , Current-Mode PWM Controller
AIC3843CNTB , Current-Mode PWM Controller
AIC809-46CUTR , 3-PIN MICROPROCESSOR RESET CIRCUITS
AIC809-46CUTR , 3-PIN MICROPROCESSOR RESET CIRCUITS
AIC810-44CUTR , 3-PIN MICROPROCESSOR RESET CIRCUITS
ADM8690AN-ADM8690ARN-ADM8691AN-ADM8691ARW-ADM8692AN-ADM8692ARN-ADM8694AN-ADM8694ARN
Microprocessor Supervisory Circuits
REV.0
Microprocessor
Supervisory Circuits
FEATURES
Upgrade for ADM690/ADM695, MAX690–MAX695
Specified Over Temperature
Low Power Consumption (0.7 mW)
Precision Voltage Monitor
Reset Assertion Down to 1 V VCC
Low Switch On-Resistance 0.7 V Normal,
7 V in Backup
High Current Drive (100 mA)
Watchdog Timer—100 ms, 1.6 s, or Adjustable
400 nA Standby Current
Automatic Battery Backup Power Switching
Extremely Fast Gating of Chip Enable Signals (3 ns)
Voltage Monitor for Power Fail
Available in TSSOP Package
APPLICATIONS
Microprocessor Systems
Computers
Controllers
Intelligent Instruments
Automotive Systems
FUNCTIONAL BLOCK DIAGRAMS
VOUT
CEOUT
LOW LINE
RESET
RESET
WATCHDOG
OUTPUT (WDO)
POWER FAIL
OUTPUT (PFO)
VBATT
VCC
CEIN
OSC IN
OSC SEL
WATCHDOG
INPUT (WDI)
POWER FAIL
INPUT (PFI)
BATT ON
1VOLTAGE DETECTOR = 4.65V (ADM8691, ADM8695)
4.40V (ADM8693)
VOUT
RESET
POWER FAIL
OUTPUT (PFO)
VBATT
VCC
WATCHDOG
INPUT (WDI)
POWER FAIL
INPUT (PFI)
1VOLTAGE DETECTOR = 4.65V (ADM8690, ADM8694)
4.40V (ADM8692)
2RESET PULSE WIDTH = 50ms (AD8690, ADM8692)
200ms (ADM8694)
GENERAL DESCRIPTIONThe ADM8690–ADM8695 family of supervisory circuits offers
complete single chip solutions for power supply monitoring and
battery control functions in microprocessor systems. These
functions include μP reset, backup battery switchover, watchdog
timer, CMOS RAM write protection and power failure warning.
The complete family provides a variety of configurations to sat-
isfy most microprocessor system requirements.
The ADM8690, ADM8692 and ADM8694 are available in
8-pin DIP packages and provide:Power-on reset output during power-up, power-down and
brownout conditions. The RESET output remains opera-
tional with VCC as low as 1 V.Battery backup switching for CMOS RAM, CMOS
microprocessor or other low power logic.A reset pulse if the optional watchdog timer has not been
toggled within a specified time.A 1.3 V threshold detector for power fail warning, low battery
detection or to monitor a power supply other than +5 V.
The ADM8691, ADM8693 and ADM8695 are available in
16-pin DIP and small outline packages (including TSSOP) and
provide three additional functions:Write protection of CMOS RAM or EEPROM.Adjustable reset and watchdog timeout periods.Separate watchdog timeout, backup battery switchover, and
low VCC status outputs.
The ADM8690–ADM8695 family is fabricated using an ad-
vanced epitaxial CMOS process combining low power con-
sumption (0.7 mW), extremely fast Chip Enable gating (3 ns)
and high reliability. RESET assertion is guaranteed with VCC as
low as 1 V. In addition, the power switching circuitry is de-
signed for minimal voltage drop thereby permitting increased
output current drive of up to 100 mA without the need of an
external pass transistor.
ADM8690–ADM8695–SPECIFICATIONS
(VCC = Full Operating Range, VBATT = +2.8 V, TA = TMIN to
TMAX unless otherwise noted)
NOTEWDI is a three level input which is internally biased to 38% of VCC and has an input impedance of approximately 5 MΩ.
Specifications subject to change without notice.
ADM8690–ADM8695
ABSOLUTE MAXIMUM RATINGS*(TA = +25°C unless otherwise noted)
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +6 V
VBATT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +6 V
All Other Inputs . . . . . . . . . . . . . . . . . .–0.3 V to VOUT + 0.5 V
Input Current
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 mA
VBATT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 mA
GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 mA
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . .20 mA
Power Dissipation, N-8 DIP . . . . . . . . . . . . . . . . . . . .400 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . .120°C/W
Power Dissipation, N-16 DIP . . . . . . . . . . . . . . . . . . .600 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . .135°C/W
Power Dissipation, RU-16 DIP . . . . . . . . . . . . . . . . . .600 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . .158°C/W
Power Dissipation, R-16 SOIC . . . . . . . . . . . . . . . . . .600 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . .110°C/W
Operating Temperature Range
Industrial (A Version) . . . . . . . . . . . . . . . . .–40°C to +85°C
Extended (S Version) . . . . . . . . . . . . . . . . .–55°C to +125°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . .+300°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum ratings for
extended periods of time may affect device reliability.
ORDERING GUIDE
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADM8690–ADM8695 features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. Therefore,
proper ESD precautions are recommended to avoid performance degradation or loss of
functionality.
*N = Plastic DIP; R = Small Outline (Wide); R = Small Outline (Narrow);
RU = Thin Shrink Small Outline; SO = Small Outline.
ADM8690–ADM8695
PIN FUNCTION DESCRIPTION
PIN CONFIGURATIONS
VOUT
PFO
WDI
RESET
VBATT
VCC
GND
PFI
VBATT
CEIN
WDO
RESET
RESET
VOUT
VCC
GND
PFO
WDI
CEOUTBATT ON
LOW LINE
OSC IN
OSC SELPFI
CIRCUIT INFORMATION
Battery Switchover SectionThe battery switchover circuit compares VCC to the VBATT
input, and connects VOUT to whichever is higher. Switchover
occurs when VCC is 50 mV higher than VBATT as VCC falls, and
when VCC is 70 mV greater than VBATT as VCC rises. This
20 mV of hysteresis prevents repeated rapid switching if VCC
falls very slowly or remains nearly equal to the battery voltage.
VCC
VBATT
VOUT
BATT ON
(ADM8690,
ADM8695)Figure 1.Battery Switchover Schematic
During normal operation, with VCC higher than VBATT, VCC is
internally switched to VOUT via an internal PMOS transistor
switch. This switch has a typical on-resistance of 0.7 Ω and can
supply up to 100 mA at the VOUT terminal. VOUT is normally
used to drive a RAM memory bank which may require instanta-
neous currents of greater than 100 mA. If this is the case then a
bypass capacitor should be connected to VOUT. The capacitor
If the continuous output current requirement at VOUT exceeds
100 mA, or if a lower VCC–VOUT voltage differential is desired,
an external PNP pass transistor may be connected in parallel with
the internal transistor. The BATT ON output (ADM8691/
ADM8693/ADM8695) can directly drive the base of the exter-
nal transistor.
A 7 Ω MOSFET switch connects the VBATT input to VOUT dur-
ing battery backup. This MOSFET has very low input-to-out-
put differential (dropout voltage) at the low current levels
required for battery back up of CMOS RAM or other low power
CMOS circuitry. The supply current in battery back up is typi-
cally 0.4 μA.
The ADM8690/ADM8691/ADM8694/ADM8695 operates with
battery voltages from 2.0 V to 4.25 V, and the ADM8692/
ADM8693 operates with battery voltages from 2.0 V to 4.0 V.
High value capacitors, either standard electrolytic or the farad
size double layer capacitors, can also be used for short-term
memory backup. A small charging current of typically 10 nA
(0.1 μA max) flows out of the VBATT terminal. This current is
useful for maintaining rechargeable batteries in a fully charged
condition. This extends the life of the backup battery by com-
pensating for its self discharge current. Also note that this cur-
rent poses no problem when lithium batteries are used for
backup since the maximum charging current (0.1 μA) is safe for
even the smallest lithium cells.
If the battery switchover section is not used, VBATT should be
connected to GND and VOUT should be connected to VCC.
PRODUCT SELECTION GUIDE
ADM8690–ADM8695
Watchdog Timer RESETThe watchdog timer circuit monitors the activity of the micro-
processor in order to check that it is not stalled in an indefinite
loop. An output line on the processor is used to toggle the
Watchdog Input (WDI) line. If this line is not toggled within the
selected timeout period, a RESET pulse is generated. The
nominal watchdog timeout period is preset at 1.6 seconds on the
ADM8690/ADM8692/ADM8694. The ADM8691/ADM8693/
ADM8695 may be configured for either a fixed “short” 100 ms
or a “long” 1.6 second timeout period or for an adjustable
timeout period. If the “short” period is selected, some systems
may be unable to service the watchdog timer immediately after a
reset, so the ADM8691/ADM8693/ADM8695 automatically se-
lects the “long” timeout period directly after a reset is issued.
The watchdog timer is restarted at the end of reset, whether the
reset was caused by lack of activity on WDI or by VCC falling be-
low the reset threshold.
The normal (short) timeout period becomes effective following
the first transition of WDI after RESET has gone inactive. The
watchdog timeout period restarts with each transition on the
WDI pin. To ensure that the watchdog timer does not time out,
either a high-to-low or low-to-high transition on the WDI pin
must occur at or less than the minimum timeout period. If WDI
remains permanently either high or low, reset pulses will be
issued after each “long” (1.6 s) timeout period. The watchdog
monitor can be deactivated by floating the Watchdog Input
(WDI) or by connecting it to midsupply.
WDI
WDO
RESET
t1 = RESET TIME
t2 = NORMAL (SHORT) WATCHDOG TIMEOUT PERIOD
t3 = WATCHDOG TIMEOUT PERIOD IMMEDIATELY FOLLOWING A RESETFigure 3.Watchdog Timeout Period and Reset Active
Time
Power Fail RESET OutputRESET is an active low output that provides a RESET signal
to the Microprocessor whenever VCC is at an invalid level.
When VCC falls below the reset threshold, the RESET output
is forced low. The nominal reset voltage threshold is 4.65 V
(ADM8690/ADM8691/ADM8694/ADM8695) or 4.4 V
(ADM8692/ADM8693).
VCC
RESET
LOW LINE
t1 = RESET TIME
V1 = RESET VOLTAGE THRESHOLD LOW
V2 = RESET VOLTAGE THRESHOLD HIGH
HYSTERESIS = V2–V1Figure 2.Power Fail Reset Timing
On power-up, RESET will remain low for 50 ms (200 ms for
ADM8694 and ADM8695) after VCC rises above the appropri-
ate reset threshold. This allows time for the power supply and
microprocessor to stabilize. On power-down, the RESET out-
put remains low with VCC as low as 1 V. This ensures that the
microprocessor is held in a stable shutdown condition.
This RESET active time is adjustable on the ADM8691/
ADM8693/ADM8695 by using an external oscillator or by
connecting an external capacitor to the OSC IN pin. Refer to
Table I and Figure 4.
The guaranteed minimum and maximum thresholds of the
ADM8690/ADM8691/ADM8694/ADM8695 are 4.5 V and
4.73 V, while the guaranteed thresholds of the ADM8692/
ADM8693 are 4.25 V and 4.48 V. The ADM8690/ADM8691/
ADM8694/ADM8695 is, therefore, compatible with 5 V sup-
plies with a +10%, –5% tolerance while the ADM8692/
ADM8693 is compatible with 5 V ± 10% supplies. The reset
threshold comparator has approximately 50 mV of hysteresis.
The response time of the reset voltage comparator is less than 1
μs. If glitches are present on the VCC line which could cause
spurious reset pulses, then VCC should be decoupled close to
the device.
In addition to RESET the ADM8691/ADM8693/ADM8695
contain an active high RESET output. This is the complement
of RESET and is intended for processors requiring an active
high RESET signal.
Table I.ADM8691, ADM8693, ADM8695 Reset Pulse Width and Watchdog Timeout SelectionsNOTE
With the OSC SEL pin low, OSC IN can be driven by an external clock signal, or an external capacitor can be connected between OSC IN and GND. The nominal
internal oscillator frequency is 10.24 kHz. The nominal oscillator frequency with external capacitor is: FOSC (Hz) = 184,000/C (pF)
On the ADM8690/ADM8692 the watchdog timeout period is
fixed at 1.6 seconds and the reset pulse width is fixed at 50 ms.
On the ADM8694 the watchdog timeout period is also 1.6 sec-
onds but the reset pulse width is fixed at 200 ms. The ADM8691/
ADM8693/ADM8695 allow these times to be adjusted as
shown in Table I. Figure 4 shows the various oscillator configu-
rations that can be used to adjust the reset pulse width and
watchdog timeout period.
The internal oscillator is enabled when OSC SEL is high or
floating. In this mode, OSC IN selects between the 1.6 second
and 100 ms watchdog timeout periods. With OSC IN connected
high or floating, the 1.6 second timeout period is selected; while
with it connected low, the 100 ms timeout period is selected. In
either case, immediately after a reset the timeout period is 1.6
seconds. This gives the microprocessor time to reinitialize the
system. If OSC IN is low, then the 100 ms watchdog period be-
comes effective after the first transition of WDI. The software
should be written such that the I/O port driving WDI is left in
its power-up reset state until the initialization routines are com-
pleted and the microprocessor is able to toggle WDI at the mini-
mum watchdog timeout period of 70 ms.
Watchdog Output (WDO)The Watchdog Output WDO (ADM8691/ADM8693/
ADM8695) provides a status output which goes low if the
watchdog timer “times out” and remains low until set high by
the next transition on the Watchdog Input. WDO is also set
high when VCC goes below the reset threshold.
CLOCK
0 TO 500kHzFigure 4a.External Clock Source
COSCFigure 4b.External Capacitor
Figure 4c.Internal Oscillator (1.6 Second Watchdog)
Figure 4d.Internal Oscillator (100 ms Watchdog)
ADM8690–ADM8695(PFI) is compared to an internal +1.3 V reference. The Power
Fail Output (PFO) goes low when the voltage at PFI is less than
1.3 V. Typically PFI is driven by an external voltage divider that
senses either the unregulated dc input to the system’s 5 V regu-
lator or the regulated 5 V output. The voltage divider ratio can
be chosen such that the voltage at PFI falls below 1.3 V several
milliseconds before the +5 V power supply falls below the reset
threshold. PFO is normally used to interrupt the microprocessor
so that data can be stored in RAM and the shut down procedure
executed before power is lost
POWER
FAIL
OUTPUT
INPUTR1
INPUT
POWERFigure 7.Power Fail Comparator
Table II.Input and Output Status In Battery Backup Mode
CE Gating and RAM Write Protection (ADM8691/ADM8693/
ADM8695)The ADM8691/ADM8693/ADM8695 products include
memory protection circuitry which ensures the integrity of data
in memory by preventing write operations when VCC is at an in-
valid level. There are two additional pins, CEIN and CEOUT,
which may be used to control the Chip Enable or Write inputs
of CMOS RAM. When VCC is present, CEOUT is a buffered rep-
lica of CEIN, with a 3 ns propagation delay. When VCC falls be-
low the reset voltage threshold or VBATT, an internal gate forces
CEOUT high, independent of CEIN.
CEOUT typically drives the CE, CS or write input of battery
backed up CMOS RAM. This ensures the integrity of the data
in memory by preventing write operations when VCC is at an in-
valid level. Similar protection of EEPROMs can be achieved by
using the CEOUT to drive the store or write inputs.
CEINCEOUTFigure 5.Chip Enable Gating
VCC
RESET
LOW LINE
t1 = RESET TIME
V1 = RESET VOLTAGE THRESHOLD LOW
V2 = RESET VOLTAGE THRESHOLD HIGH
HYSTERESIS = V2–V1
CEIN
CEOUTFigure 6.Chip Enable Timing
Power Fail Warning ComparatorAn additional comparator is provided for early warning of fail-
ure in the microprocessor’s power supply. The Power Fail Input
