ADM706PAR ,+3 V, Voltage Monitoring uP Supervisory Circuits+3 V, Voltage MonitoringamP Supervisory CircuitsADM706P/R/S/T, ADM708R/S/TFUNCTIONAL BLOCK DIAGRAMS
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ADM706PAN-ADM706PAR-ADM706RAN-ADM706RAR-ADM706SAN-ADM706SAR-ADM706T-ADM706TAN-ADM706TAR-ADM708RAN-ADM708RAR-ADM708SAN-ADM708SAR-ADM708TAN-ADM708TAR
+3 V, Voltage Monitoring uP Supervisory Circuits
FUNCTIONAL BLOCK DIAGRAMSREV.A
+3 V, Voltage MonitoringmP Supervisory Circuits
FEATURES
Precision Supply-Voltage Monitor
+2.63 V (ADM706P/R, ADM708R)
+2.93 V (ADM706S, ADM708S)
+3.08 V (ADM706T, ADM708T)
100 mA Quiescent Current
200 ms Reset Pulsewidth
Debounced Manual Reset Input (MR)
Independent Watchdog Timer—1.6 sec Timeout
(ADM706x)
Reset Output
Active High (ADM706P)
Active Low (ADM706R/S/T)
Both Active High and Active Low (ADM708R/S/T)
Voltage Monitor for Power-Fail or Low Battery Warning
Guaranteed RESET Valid with VCC = 1 V
Superior Upgrade for MAX706P/R/S/T, MAX708R/S/T
APPLICATIONS
Microprocessor Systems
Computers
Controllers
Intelligent Instruments
Critical mP Monitoring
Automotive Systems
Battery Operated Systems
Portable Instruments
GENERAL DESCRIPTIONThe ADM706P/R/S/T and the ADM708R/S/T microprocessor
supervisory circuits are suitable for monitoring either 3 V or 3.3 V
power supplies.
The ADM706P/R/S/T provide the following functions:Power-supply monitoring circuitry which generates a Reset
output during power-up, power-down and brownout condi-
tions. The reset output remains operational with VCC as low
as 1 V.Independent watchdog monitoring circuitry which is acti-
vated if the watchdog input has not been toggled within
1.6 seconds.A 1.25 V threshold detector for power fail warning, low bat-
tery detection, or to monitor an additional power supply.An active low debounced manual reset input (MR).
The ADM706R, ADM706S, ADM706T are identical except for
the reset threshold monitor levels which are 2.63 V, 2.93 V, and
3.08 V respectively. The ADM706P is identical to the ADM706R
in that the reset threshold is 2.63 V. It differs only in that it has
an active high reset output.
The ADM708R/S/T provide the same functionality as the
ADM706R/S/T and only differ in that:A watchdog timer function is not available.An active high reset output (RESET) in addition to the
active low (RESET) output is available.
All parts are available in 8-lead DIP and narrow SOIC packages.
Reset Threshold (VRST)
RESET Output Voltage
RESET Output Voltage
Watchdog Timeout Period
WDI Pulsewidth
WDI Input Threshold
MR Pull Up CurrentMR Pulsewidth
MR Input Threshold
ADM706P/R/S/T, ADM708R/S/T–SPECIFICATIONS
(VCC = 2.70 V to 5.5 V (ADM70_P/R),
VCC = 3.00 V to 5.5 V (ADM70_S), VCC = 3.15 V to 5.5 V (ADM70_T), TA = TMIN to TMAX unless otherwise noted.)
ORDERING GUIDEPFI Input Threshold
ADM706P/R/S/T, ADM708R/S/T
ABSOLUTE MAXIMUM RATINGS*(TA = +25°C unless otherwise noted)
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +6 V
All Other Inputs . . . . . . . . . . . . . . . . . .–0.3 V to VCC + 0.3 V
Input Current
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 mA
GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 mA
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . .20 mA
Power Dissipation, N-8 DIP . . . . . . . . . . . . . . . . . . . .727 mWJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . .135°C/W
Power Dissipation, SO-8 SOIC . . . . . . . . . . . . . . . . . .470 mWJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . .110°C/W
Operating Temperature Range
Industrial (A Version) . . . . . . . . . . . . . . . . .–40°C to +85°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . .+300°C
Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..>5 kV
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum
ratings for extended periods of time may affect device reliability.
ADM706P/R/S/T, ADM708R/S/T
PIN FUNCTION DESCRIPTIONSVCC
GND
PFI
PFO
RESET
WDO
PIN CONFIGURATIONS
VCC
GND
PFI
WDO
RESET
WDI
PFO
VCC
GND
PFI
NC = NO CONNECT
RESET
RESET
PFO
VCC
GND
PFI
WDO
RESET
WDI
PFO
Figure 1.ADM706 Functional Block Diagram
POWER FAIL
INPUT (PFI)POWER FAIL
OUTPUT (PFO)
RESET
*VOLTAGE REFERENCE = 2.63V (R), 2.93V (S), 3.08V (T)
VCC
RESETFigure 2.ADM708 Functional Block Diagram
CIRCUIT INFORMATION
Power Fail ResetThe reset output provides a reset (RESET or RESET) output
signal to the Microprocessor whenever the VCC input is below
the reset threshold. The actual reset threshold voltage is depen-
dent on whether a P/R, S, or T suffix device is used. An internal
timer holds the reset output active for 200 ms after the voltage
on VCC rises above the threshold. This is intended as a power-on
reset signal for the microprocessor. It allows time for both the
power supply and the microprocessor to stabilize after power-
up. If a power supply brownout or interruption occurs, the reset
line is similarly activated and remains active for 200 ms after the
supply recovers. If another interruption occurs during an active
reset period, then the reset timeout period continues for an ad-
ditional 200 ms.
The reset output is guaranteed to remain valid with VCC as low
as 1 V. This ensures that the microprocessor is held in a stable
shutdown condition as the power supply starts up.
The ADM706P provides an active high reset (RESET) signal;
the ADM706R/S/T provides an active low (RESET) signal;
while the ADM708R/S/T provides both RESET and RESET.
Manual ResetThe manual reset input (MR) allows other reset sources such as
a manual reset switch to generate a processor reset. The input is
effectively debounced by the timeout period (200 ms typical).
The MR input is TTL/CMOS compatible so it may also be
driven by any logic reset output. If unused, the MR input may
be tied high or left floating.
Figure 3.RESET, MR and WDO Timing
Watchdog Timer (ADM706)The watchdog timer circuit may be used to monitor the activity
of the microprocessor in order to check that it is not stalled in
an indefinite loop. An output line on the processor is used to
toggle the Watchdog Input (WDI) line. If this line is not toggled
within the timeout period (1.6 sec), the watchdog output
(WDO) is driven low. The WDO output may be connected to a
nonmaskable interrupt (NMI) on the processor. Therefore, if
the watchdog timer times out, an interrupt is generated. The in-
terrupt service routine should then be used to rectify the
problem.
The watchdog timer is cleared by either a high-to-low or by a
low-to-high transition on WDI. Pulses as narrow as 50 ns are
detected. The timer is also cleared by RESET/RESET going
active. Therefore the watchdog timeout period begins after reset
goes inactive.
When VCC falls below the reset threshold, WDO is forced low
whether or not the watchdog timer has timed out. Normally
this would generate an interrupt but it is overridden by RESET/RESET going active.
The watchdog monitor can be deactivated by floating the
Watchdog Input (WDI). The WDO output can now be used as
a low line output since it will only go low when VCC falls below
the reset threshold.
ADM706P/R/S/T, ADM708R/S/T
Valid RESET Below 1 V VCCThe ADM70x family of products are guaranteed to provide a
valid reset level with VCC as low as 1 V. Please refer to the Typi-
cal Performance Characteristics. As VCC drops below 1 V, the
internal transistor will not have sufficient drive to hold it ON so
the voltage on RESET will no longer be held at 0 V. A pull-
down resistor as shown in Figure 7 may be connected externally
to hold the line low if it is required.
Figure 7.RESET Valid Below 1 V
Power-Fail ComparatorThe power-fail comparator is an independent comparator which
may be used to monitor the input power supply. The compara-
tor’s inverting input is internally connected to a 1.25 V reference
voltage. The noninverting input is available at the PFI input.
This input may be used to monitor the input power supply via a
resistive divider network. When the voltage on the PFI input drops
below 1.25 V, the comparator output (PFO) goes low indicating
a power failure. For early warning of power failure the compara-
tor may be used to monitor the preregulator input simply by
choosing an appropriate resistive divider network. The PFO output
can be used to interrupt the processor so that a shutdown proce-
dure is implemented before the power is lost.
INPUT
POWERFigure 5. Power-Fail Comparator
Adding Hysteresis to the Power-Fail ComparatorFor increased noise immunity, hysteresis may be added to the
power-fail comparator. Since the comparator circuit is nonin-
verting, hysteresis can be added simply by connecting a resistor
between the PFO output and the PFI input as shown in Figure
6. When PFO is low, resistor R3 sinks current from the sum-
ming junction at the PFI pin. When PFO is high, resistor R3
sources current into the PFI summing junction. This results in
differing trip levels for the comparator. Further noise immunity
may be achieved by connecting a capacitor between PFI and GND.
INPUT
POWER
3.3V
PFOVL
VIN Figure 6. Adding Hysteresis to the Power-Fail
Comparator
Figure 8.ADM706/ADM708 RESET Output Voltage vs.
Supply Voltage
Typical Performance Characteristics
