ADM708AN ,Low Cost uP Supervisory CircuitsSPECIFICATIONSCC A MIN MAXParameter Min Typ Max Unit Test Conditions/CommentsV Operating Voltage Ra ..
ADM708AR ,Low Cost uP Supervisory CircuitsSPECIFICATIONSCC A MIN MAXParameter Min Typ Max Unit Test Conditions/CommentsV Operating Voltage Ra ..
ADM708ARZ , Low Cost Microprocessor Supervisory Circuits
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ADM708RAR ,+3 V, Voltage Monitoring uP Supervisory CircuitsFEATURESPrecision Supply-Voltage Monitor+2.63 V (ADM706P/R, ADM708R)WATCHDOGWATCHDOGWATCHDOGWATCHDO ..
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ADM705AN-ADM705AR-ADM706AN-ADM706AR-ADM707AN-ADM707AR-ADM708AN-ADM708AR
Low Cost uP Supervisory Circuits
FUNCTIONAL BLOCK DIAGRAMS
WATCHDOG
INPUT (WDI)
POWER-FAIL
INPUT (PFI)POWER-FAIL
OUTPUT (PFO)
WATCHDOG
OUTPUT (WDO)
RESET
*VOLTAGE REFERENCE = 4.65V (ADM705), 4.40V (ADM706)
VCCREV.B
Low Cost �P
Supervisory Circuits
FEATURES
Guaranteed RESET Valid with VCC = 1V
190 �A Quiescent Current
Precision Supply-Voltage Monitor
4.65 V (ADM705/ADM707)
4.40 V (ADM706/ADM708)
200 ms Reset Pulsewidth
Debounced TTL/CMOS Manual Reset Input (MR)
Independent Watchdog Timer—1.6 sec Timeout
(ADM705/ADM706)
Active High Reset Output (ADM707/ADM708)
Voltage Monitor for Power-Fail or Low Battery
Warning
Superior Upgrade for MAX705–MAX708
Also Available in MicroSOIC Packages
APPLICATIONS
Microprocessor Systems
Computers
Controllers
Intelligent Instruments
Critical �P Monitoring
Automotive Systems
Critical �P Power Monitoring
GENERAL DESCRIPTIONThe ADM705–ADM708 are low cost µP supervisory circuits.
They are suitable for monitoring the 5 V power supply/battery
and can also monitor microprocessor activity.
The ADM705/ADM706 provide the following functions:Power-On Reset output during power-up, power-down and
brownout conditions. The RESET output remains opera-
tional with VCC as low as 1V.Independent watchdog timeout, WDO, that goes low if the
watchdog input has not been toggled within 1.6 seconds.A 1.25 V threshold detector for power-fail warning, low
battery detection or to monitor a power supply other than
5V.An active low debounced manual reset input (MR).
The ADM707/ADM708 differ in that:A watchdog timer function is not available.An active high reset output in addition to the active low
output is available.
Two supply-voltage monitor levels are available. The ADM705/
ADM707 generate a reset when the supply voltage falls below
4.65 V, while the ADM706/ADM708 require that the supply
fall below 4.40 V before a reset is issued.
All parts are available in 8-lead DIP and SOIC packages. The
ADM707 and ADM708 are also available in space-saving
microSOIC packages.
ADM705–ADM708–SPECIFICATIONSReset Threshold
Reset Threshold Hysteresis
Reset Pulsewidth
RESET Output Voltage
WDO Output Voltage
MR Pull-Up Current
MR Pulsewidth
MR Input Threshold
Specifications subject to change without notice.
(VCC = 4.75 V to 5.5 V, TA = TMIN to TMAX unless otherwise noted.)
ORDERING GUIDE
ABSOLUTE MAXIMUM RATINGS*(TA = 25°C unless otherwise noted)
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +6 V
All Other Inputs . . . . . . . . . . . . . . . . . .–0.3 V to VCC + 0.3 V
Input Current
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 mA
GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 mA
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . .20 mA
Power Dissipation, N-8 DIP . . . . . . . . . . . . . . . . . . . .727 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . .135°C/W
Power Dissipation, SO-8 SOIC . . . . . . . . . . . . . . . . . .470 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . .110°C/W
Operating Temperature Range
Industrial (A Version) . . . . . . . . . . . . . . . . .–40°C to +85°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . .300°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . .215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220°C
Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>5 kV
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
PIN FUNCTION DESCRIPTIONVCC
GND
PFI
PIN CONFIGURATION
DIP, SOIC DIP, SOIC MicroSOIC
ADM705–ADM708
Manual Reset (ADM707/ADM708)The manual reset input (MR) allows other reset sources, such as
a manual reset switch, to generate a processor reset. The input
is effectively debounced by the timeout period (200 ms typical).
The MR input is TTL/CMOS compatible, so it may also be
driven by any logic reset output.
Figure 3.RESET, MR, and WDO Timing
Watchdog Timer (ADM705/ADM706)The watchdog timer circuit may be used to monitor the activity
of the microprocessor in order to check that it is not stalled in an
indefinite loop. An output line on the processor is used to toggle
the Watchdog Input (WDI) line. If this line is not toggled
within the timeout period (1.6 sec), the watchdog output
(WDO) goes low. The WDO output may be connected to a
nonmaskable interrupt (NMI) on the processor; therefore, if the
watchdog timer times out, an interrupt is generated. The inter-
rupt service routine should then be used to rectify the problem.
If a RESET signal is required when a timeout occurs, the WDO
output should be connected to the manual reset input (MR).
The watchdog timer is cleared by either a high-to-low or by a
low-to-high transition on WDI. It is also cleared by RESET
going low; therefore, the watchdog timeout period begins after
RESET goes high.
When VCC falls below the reset threshold, WDO is forced low
whether or not the watchdog timer has timed out. Normally,
this would generate an interrupt, but it is overridden by RESET
going low.
The watchdog monitor can be deactivated by floating the
Watchdog Input (WDI). The WDO output can now be used as
a low-line output since it will only go low when VCC falls below
the reset threshold.
Figure 4.Watchdog Timing
Figure 1.ADM705/ADM706 Functional Block Diagram
Figure 2.ADM707/ADM708 Functional Block Diagram
CIRCUIT INFORMATION
Power-Fail RESET OutputRESET is an active low output that provides a RESET signal to
the Microprocessor whenever the VCC input is below the reset
threshold. An internal timer holds RESET low for 200 ms after
the voltage on VCC rises above the threshold. This is intended as
a power-on RESET signal for the microprocessor. It allows time
for both the power supply and the microprocessor to stabilize
after power-up. The RESET output is guaranteed to remain
valid (low) with VCC as low as 1 V. This ensures that the micro-
processor is held in a stable shutdown condition as the power
supply voltage ramps up.
In addition to RESET, an active high RESET output is also
available on the ADM707/ADM708. This is the complement of
RESET and is useful for processors requiring an active high
RESET signal.
Power-Fail ComparatorThe power-fail comparator is an independent comparator that
may be used to monitor the input power supply. The comparator’s
inverting input is internally connected to a 1.25 V reference
voltage. The noninverting input is available at the PFI input.
This input may be used to monitor the input power supply via
a resistive divider network. When the voltage on the PFI input
drops below 1.25 V, the comparator output (PFO) goes low,
indicating a power failure. For early warning of power failure,
the comparator may be used to monitor the preregulator input
simply by choosing an appropriate resistive divider network.
The PFO output can be used to interrupt the processor so that
a shutdown procedure is implemented before the power is lost.
Figure 5.Power-Fail Comparator
Adding Hysteresis to the Power-Fail ComparatorFor increased noise immunity, hysteresis may be added to the
power-fail comparator. Since the comparator circuit is non-
inverting, hysteresis can be added simply by connecting a
resistor between the PFO output and the PFI input as shown in
Figure 6. When PFO is low, resistor R3 sinks current from the
summing junction at the PFI pin. When PFO is high, resistor
R3 sources current into the PFI summing junction. This results
in differing trip levels for the comparator. Further noise immu-
nity may be achieved by connecting a capacitor between PFI
and GND.
Figure 6.Adding Hysteresis to the Power-Fail Comparator
Valid RESET Below 1 V VCCThe ADM70x family of products is guaranteed to provide a
valid reset level with VCC as low as 1 V; please refer to the Typi-
cal Performance Characteristics. As VCC drops below 1 V, the
internal transistor will not have sufficient drive to hold it ON so
the voltage on RESET will no longer be held at 0 V. A pull-down
resistor as shown in Figure 7 may be connected externally to
hold the line low if it is required.
Figure 7.RESET Valid Below 1 V
ADM705–ADM708–Typical Performance CharacteristicsFigure 11.PFI Comparator Deassertion Response Time
Figure 12.RESET, RESET Assertion
Figure 13.RESET, RESET Deassertion
Figure 8.RESET Output Voltage vs. Supply Voltage
Figure 9.ADM707/ADM708 RESET Output Voltage vs.
Supply Voltage
Figure 10.PFI Comparator Assertion Response Time
