ADM696AR ,Microprocessor Supervisory CircuitsSPECIFICATIONSParameter Min Typ Max Units Test Conditions/CommentsV Operating Voltage Range 3.0 5.5 ..
ADM697AR ,Microprocessor Supervisory CircuitsSpecifications subject to change without notice.–2– REV. 0ADM696/ADM697Power Dissipation, R-16 SOIC ..
ADM698AN ,Microprocessor Supervisory Circuitsfeatures an identical monitoring circuit as in theADM698 plus an additional watchdog timer input to ..
ADM698AN ,Microprocessor Supervisory CircuitsSPECIFICATIONSParameter Min Typ Max Units Test Conditions/CommentsV Operating Voltage Range 3.0 5.5 ..
ADM698AR ,Microprocessor Supervisory CircuitsSPECIFICATIONSParameter Min Typ Max Units Test Conditions/CommentsV Operating Voltage Range 3.0 5.5 ..
ADM6996F ,6 port 10/100 Mb/s Single Chip Ethernet Switch ControllerTable of Contents Chapter 1 Product Overview ....... 1-1 1.1 Overview....... 1-1 1.2
AIC1714 , Negative Voltage Regulator
AIC1720-33CX , 100mA Low Dropout Linear Regulator
AIC1720-33CZL , 100mA Low Dropout Linear Regulator
AIC1720-33CZT , 100mA Low Dropout Linear Regulator
AIC1720-33CZT , 100mA Low Dropout Linear Regulator
AIC1720-50CS , 100mA Low Dropout Linear Regulator
ADM696AQ-ADM696AR-ADM697AR
Microprocessor Supervisory Circuits
FUNCTIONAL BLOCK DIAGRAMSREV.0
Microprocessor
Supervisory Circuits
FEATURES
Superior Upgrade for MAX696/MAX697
Specified Over Temperature
Adjustable Low Line Voltage Monitor
Power OK/Reset Time Delay
Reset Assertion Down to 1 V VCC
Watchdog Timer—100 ms, 1.6 s, or Adjustable
Low Switch On Resistance
1.5 V Normal, 20 V in Backup
600 nA Standby Current
Automatic Battery Backup Switching (ADM696)
Fast On-Board Gating of Chip Enable Signals (ADM697)
Voltage Monitor for Power Fail or Low Battery Warning
APPLICATIONS
Microprocessor Systems
Computers
Controllers
Intelligent Instruments
Automotive Systems
Critical mP Power Monitoring
GENERAL DESCRIPTIONThe ADM696/ADM697 supervisory circuits offer complete
single chip solutions for power supply monitoring and battery
control functions in microprocessor systems. These functions
include μP reset, backup-battery switchover, watchdog timer,
CMOS RAM write protection, and power failure warning.
The ADM696/ADM697 are available in 16-pin DIP and small
outline packages and provide the following functions:Power-On Reset output during power-up, power-down and
brownout conditions. The RESET voltage threshold is
adjustable using an external voltage divider. The RESET
output remains operational with VCC as low as 1 V.A Reset pulse if the optional watchdog timer has not been
toggled within specified time.Separate watchdog time-out and low line status outputs.Adjustable reset and watchdog timeout periods.A 1.3 V threshold detector for power fail warning, low bat-
tery detection, or to monitor a power supply other than VCC.Battery backup switching for CMOS RAM, CMOS micro-
processor or other low power logic (ADM696).Write protection of CMOS RAM or EEPROM (ADM697).
The ADM696/ADM697 is fabricated using an advanced epitaxial
CMOS process combining low power consumption (5 mW),
extremely fast Chip Enable gating (5 ns) and high reliability.
RESET assertion is guaranteed with VCC as low as 1 V. In
addition, the power switching circuitry is designed for minimal
voltage drop thereby permitting increased output current drive
of up to 100 mA without the need for an external pass transistor.
ADM696/ADM697–SPECIFICATIONSBATTERY BACKUP SWITCHING (ADM696)
RESET AND WATCHDOG TIMER
CHIP ENABLE GATING (ADM697)
NOTE
1WDI is a three-level input which is internally biased to 38% of VCC and has an input impedance of approximately 125 kΩ.
Specifications subject to change without notice.
(VCC = Full Operating Range, VBATT = +2.8 V, TA = TMIN to TMAX
unless otherwise noted.)
ORDERING GUIDE
ABSOLUTE MAXIMUM RATINGS*(TA = +25°C unless otherwise noted)
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +6 V
VBATT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +6 V
All Other Inputs . . . . . . . . . . . . . . . . . .–0.3 V to VOUT + 0.5 V
Input Current
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 mA
VBATT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 mA
GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 mA
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . .20 mA
Power Dissipation, N-16 DIP . . . . . . . . . . . . . . . . . . .600 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . .135°C/W
Power Dissipation, Q-16 DIP . . . . . . . . . . . . . . . . . . .600 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . .100°C/W
Power Dissipation, R-16 SOIC . . . . . . . . . . . . . . . . . .600 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . .110°C/W
Operating Temperature Range
Industrial (A Version) . . . . . . . . . . . . . . . . .–40°C to +85°C
Extended (S Version) . . . . . . . . . . . . . . . . .–55°C to +125°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . .+300°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum ratings for extended periods of time may affect device reliability.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADM696/ADM697 features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
PIN CONFIGURATIONS
GNDBATTOUT
PFI
PFO
WDOVCC
RESET
BATT ON
LOW LINE
OSC IN
OSC SEL
RESETIN
WDIIN
TEST
PFI
PFO
WDOVCC
RESET
GND
LOW LINE
OSC IN
OSC SEL
RESETINOUT
WDI
ADM696/ADM697
PIN FUNCTION DESCRIPTIONVBATT
VOUT
PFI
CEOUT
Low Line RESET OUTPUTRESET is an active low output which provides a RESET signal
to the microprocessor whenever the Low Line Input (LLIN) is
below 1.3 V. The LLIN input is normally used to monitor the
power supply voltage. An internal timer holds RESET low for
50 ms after the voltage on LLIN rises above 1.3 V. This is in-
tended as a power-on RESET signal for the processor. It allows
time for the power supply and microprocessor to stabilize. On
power-down, the RESET output remains low with VCC as low
as 1 V. This ensures that the microprocessor is held in a stable
shutdown condition.
The LLIN comparator has approximately 12 mV of hysteresis
for enhanced noise immunity.
In addition to RESET, an active high RESET output is also
available. This is the complement of RESET and is useful for
processors requiring an active high RESET.
Figure 2.Power-Fail Reset Timing
Watchdog Timer RESETThe watchdog timer circuit monitors the activity of the micro-
processor in order to check that it is not stalled in an indefinite
loop. An output line on the processor is used to toggle the
Watchdog Input (WDI) line. If this line is not toggled within
the selected timeout period, a RESET pulse is generated. The
ADM696/ADM697 may be configured for either a fixed
“short” 100 ms or a “long” 1.6 second timeout period or for an
adjustable timeout period. If the “short” period is selected some
systems may be unable to service the watchdog timer immedi-
ately after a reset, so a “long” timeout is automatically initiated
directly after a reset is issued. The watchdog timer is restarted
at the end of Reset, whether the Reset was caused by lack of ac-
tivity on WDI or by LLIN falling below the reset threshold.
The normal (short) timeout period becomes effective following
the first transition of WDI after RESET has gone inactive. The
watchdog timeout period restarts with each transition on the
WDI pin. To ensure that the watchdog timer does not time out,
either a high-to-low or low-to high transition on the WDI pin
must occur at or less than the minimum timeout period. If WDI
remains permanently either high or low, reset pulses will be is-
sued after each timeout period (1.6 s). The watchdog monitor
can be deactivated by floating the Watchdog Input (WDI) or by
CIRCUIT INFORMATION
Battery-Switchover Section (ADM696)The battery switchover circuit compares VCC to the VBATT
input, and connects VOUT to whichever is higher. Switchover
occurs when VCC is 50 mV higher than VBATT as VCC falls, and
when VCC is 70 mV greater than VBATT as VCC rises. This
20 mV of hysteresis prevents repeated rapid switching if VCC
falls very slowly or remains nearly equal to the battery voltage.
During normal operation with VCC higher than VBATT, VCC is
internally switched to VOUT via an internal PMOS transistor
switch. This switch has a typical on resistance of 1.5 Ω and can
supply up to 100 mA at the VOUT terminal. VOUT is normally
used to drive a RAM memory bank which may require instanta-
neous currents of greater than 100 mA. If this is the case, then
a bypass capacitor should be connected to VOUT. The capacitor
will provide the peak current transients to the RAM. A capaci-
tance value of 0.1 μF or greater may be used.
If the continuous output current requirement at VOUT exceeds
100 mA or if a lower VCC–VOUT voltage differential is desired,
an external PNP pass transistor may be connected in parallel
with the internal transistor. The BATT ON output can directly
drive the base of the external transistor.
A 20 Ω MOSFET switch connects the VBATT input to VOUT
during battery backup. This MOSFET has very low input-to-
output differential (dropout voltage) at the low current levels
required for battery backup of CMOS RAM or other low power
CMOS circuitry. The supply current in battery backup is typi-
cally 0.6 μA.
The ADM696 operates with battery voltages from 2.0 V to VCC
–0.3 V). High value capacitors, either standard electrolytic or
the farad-size double layer capacitors, can also be used for short-
term memory backup. A small charging current of typically
10 nA (0.1 μA max) flows out of the VBATT terminal. This cur-
rent is useful for maintaining rechargeable batteries in a fully
charged condition. This extends the life of the backup battery
by compensating for its self discharge current. Also note that
this current poses no problem when lithium batteries are used
for backup since the maximum charging current (0.1 μA) is safe
for even the smallest lithium cells.
If the battery-switchover section is not used, VBATT should be
connected to GND and VOUT should be connected to VCC.
VBATT
VCC
BATT ON
(ADM691, ADM693,
ADM695, ADM696)
VOUT
ADM696/ADM697
Table I.ADM696, ADM697 Reset Pulse Width and Watchdog Timeout SelectionsNOTE
With the OSC SEL pin low, OSC IN can be driven by an external clock signal, or an external capacitor can be connected between OSC IN and GND. The nominal
internal oscillator frequency is 10.24 kHz. The nominal oscillator frequency with external capacitor is: FOSC (Hz) = 184,000/C (pF).
RESET
WDO
WDI1 = RESET TIME2 = NORMAL (SHORT) WATCHDOG TIMEOUT PERIOD3 = WATCHDOG TIMEOUT PERIOD IMMEDIATELY FOLLOWING A RESETFigure 3.Watchdog Timeout Period and Reset Active Time
The watchdog timeout period defaults to 1.6 s and the reset
pulse width defaults to 50 ms but these times to be adjusted as
shown in Table I. Figure 4 shows the various oscillator configu-
rations which can be used to adjust the reset pulse width and
watchdog timeout period.
The internal oscillator is enabled when OSC SEL is high or
floating. In this mode, OSC IN selects between the 1.6 second
and 100 ms watchdog timeout periods. In either case, immedi-
ately after a reset the timeout period is 1.6 s. This gives the mi-
croprocessor time to reinitialize the system. If OSC IN is low,
then the 100 ms watchdog period becomes effective after the
first transition of WDI. The software should be written such
that the I/O port driving WDI is left in its power-up reset state
until the initialization routines are completed and the micropro-
cessor is able to toggle WDI at the minimum watchdog timeout
period of 70 ms.
CLOCK
0 TO 250kHzFigure 4a.External Clock Source
Figure 4b.External Capacitor
Figure 4c.Internal Oscillator (1.6 s Watchdog)
Figure 4d.Internal Oscillator (100 ms Watchdog)
Watchdog Output (WDO)The Watchdog Output WDO provides a status output which
goes low if the watchdog timer “times out” and remains low
until set high by the next transition on the watchdog input.
WDO is also set high when LLIN goes below the reset threshold.
