ADM691AR ,Microprocessor Supervisory CircuitsSPECIFICATIONS T unless otherwise noted)MAXParameter Min Typ Max Units Test Conditions/CommentsBATT ..
ADM691SQ ,Microprocessor Supervisory CircuitsGENERAL DESCRIPTIONThe ADM690–ADM695 family of supervisory circuits offersVOUTcomplete single chip ..
ADM692AAN ,Microprocessor Supervisory CircuitsGENERAL DESCRIPTIONThe ADM690A/ADM692A/ADM802L/M/ADM805L/MThe ADM805L/M provides an active high res ..
ADM692AN ,Microprocessor Supervisory CircuitsGENERAL DESCRIPTIONThe ADM690–ADM695 family of supervisory circuits offersVOUTcomplete single chip ..
ADM692AQ ,Microprocessor Supervisory CircuitsSpecifications subject to change without notice.ABSOLUTE MAXIMUM RATINGS*ORDERING GUIDE(T = +25°C u ..
ADM692SQ ,Microprocessor Supervisory CircuitsSPECIFICATIONS T unless otherwise noted)MAXParameter Min Typ Max Units Test Conditions/CommentsBATT ..
AIC1714 , Negative Voltage Regulator
AIC1720-33CX , 100mA Low Dropout Linear Regulator
AIC1720-33CZL , 100mA Low Dropout Linear Regulator
AIC1720-33CZT , 100mA Low Dropout Linear Regulator
AIC1720-33CZT , 100mA Low Dropout Linear Regulator
AIC1720-50CS , 100mA Low Dropout Linear Regulator
ADM690AN-ADM691AN-ADM691AR-ADM691SQ-ADM692AN-ADM692AQ-ADM692SQ-ADM693AN-ADM693AR-ADM694AN-ADM694SQ-ADM695AN-ADM695AQ-ADM695AR-ADM695SQ
Microprocessor Supervisory Circuits
REV.A
Microprocessor
Supervisory Circuits
FEATURES
Superior Upgrade for MAX690–MAX695
Specified Over Temperature
Low Power Consumption (5 mW)
Precision Voltage Monitor
Reset Assertion Down to 1 V VCC
Low Switch On-Resistance 1.5 V Normal,
20 V in Backup
High Current Drive (100 mA)
Watchdog Timer—100 ms, 1.6 s, or Adjustable
600 nA Standby Current
Automatic Battery Backup Power Switching
Extremely Fast Gating of Chip Enable Signals (5 ns)
Voltage Monitor for Power Fail
APPLICATIONS
Microprocessor Systems
Computers
Controllers
Intelligent Instruments
Automotive Systems
GENERAL DESCRIPTIONThe ADM690–ADM695 family of supervisory circuits offers
complete single chip solutions for power supply monitoring and
battery control functions in microprocessor systems. These
functions include μP reset, backup battery switchover, watchdog
timer, CMOS RAM write protection, and power failure warn-
ing. The complete family provides a variety of configurations to
satisfy most microprocessor system requirements.
The ADM690, ADM692 and ADM694 are available in 8-pin
DIP packages and provide:Power-on reset output during power-up, power-down and
brownout conditions. The RESET output remains opera-
tional with VCC as low as 1 V.Battery backup switching for CMOS RAM, CMOS
microprocessor or other low power logic.A reset pulse if the optional watchdog timer has not been
toggled within a specified time.A 1.3 V threshold detector for power fail warning, low battery
detection, or to monitor a power supply other than +5 V.
The ADM691, ADM693 and ADM695 are available in 16-pin
DIP and small outline packages and provide three additional
functions.Write protection of CMOS RAM or EEPROM.Adjustable reset and watchdog timeout periods.Separate watchdog timeout, backup battery switchover, and
low VCC status outputs.
FUNCTIONAL BLOCK DIAGRAMS
ADM690–ADM695–SPECIFICATIONSPOWER FAIL DETECTOR
(VCC = Full Operating Range, VBATT = +2.8 V, TA = TMIN to
TMAX unless otherwise noted)
NOTEWDI is a three level input which is internally biased to 38% of VCC and has an input impedance of approximately 125 kΩ.
Specifications subject to change without notice.
ADM690–ADM695
ABSOLUTE MAXIMUM RATINGS*(TA = +25°C unless otherwise noted)
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +6 V
VBATT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +6 V
All Other Inputs . . . . . . . . . . . . . . . . . .–0.3 V to VOUT + 0.5 V
Input Current
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 mA
VBATT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 mA
GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 mA
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . .20 mA
Power Dissipation, N-8 DIP . . . . . . . . . . . . . . . . . . . .400 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . .120°C/W
Power Dissipation, Q-8 DIP . . . . . . . . . . . . . . . . . . . .500 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . .125°C/W
Power Dissipation, N-16 DIP . . . . . . . . . . . . . . . . . . .600 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . .135°C/W
Power Dissipation, Q-16 DIP . . . . . . . . . . . . . . . . . . .600 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . .100°C/W
Power Dissipation, R-16 SOIC . . . . . . . . . . . . . . . . . .600 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . .110°C/W
Operating Temperature Range
Industrial (A Version) . . . . . . . . . . . . . . . . .–40°C to +85°C
Extended (S Version) . . . . . . . . . . . . . . . . .–55°C to +125°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . .+300°C
Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum ratings for extended periods of time may affect device reliability.
ORDERING GUIDE
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADM690–ADM695 features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. Therefore,
proper ESD precautions are recommended to avoid performance degradation or loss of
functionality.
ADM690–ADM695
PIN FUNCTION DESCRIPTION
PIN CONFIGURATIONS
PRODUCT SELECTION GUIDE
CIRCUIT INFORMATION
Battery Switchover SectionThe battery switchover circuit compares VCC to the VBATT
input, and connects VOUT to whichever is higher. Switchover
occurs when VCC is 50 mV higher than VBATT as VCC falls, and
when VCC is 70 mV greater than VBATT as VCC rises. This
20 mV of hysteresis prevents repeated rapid switching if VCC
falls very slowly or remains nearly equal to the battery voltage.
Figure 1.Battery Switchover Schematic
During normal operation with VCC higher than VBATT, VCC is in-
ternally switched to VOUT via an internal PMOS transistor
switch. This switch has a typical on-resistance of 1.5 Ω and can
supply up to 100 mA at the VOUT terminal. VOUT is normally
used to drive a RAM memory bank which may require instanta-
If the continuous output current requirement at VOUT exceeds
100 mA or if a lower VCC–VOUT voltage differential is desired,
an external PNP pass transistor may be connected in parallel
with the internal transistor. The BATT ON output (ADM691/
ADM693/ADM695) can directly drive the base of the external
transistor.
A 20 Ω MOSFET switch connects the VBATT input to VOUT
during battery backup. This MOSFET has very low input-to-
output differential (dropout voltage) at the low current levels
required for battery back up of CMOS RAM or other low
power CMOS circuitry. The supply current in battery back up
is typically 0.6 μA.
The ADM690/ADM691/ADM694/ADM695 operates with
battery voltages from 2.0 V to 4.25 V and the ADM692/ADM693
operates with battery voltages from 2.0 V to 4.0 V. High value
capacitors, either standard electrolytic or the farad size double
layer capacitors, can also be used for short-term memory back
up. A small charging current of typically 10 nA (0.1 μA max)
flows out of the VBATT terminal. This current is useful for
maintaining rechargeable batteries in a fully charged condition.
This extends the life of the back up battery by compensating
for its self discharge current. Also note that this current poses
no problem when lithium batteries are used for back up since
the maximum charging current (0.1 μA) is safe for even the
smallest lithium cells.
If the battery-switchover section is not used, VBATT should be
connected to GND and VOUT should be connected to VCC.
GNDBATTOUT
PFI
PFO
WDOVCC
RESET
BATT ON
LOW LINE
OSC IN
OSC SEL
RESETINOUT
WDI
GNDBATTVOUT
PFIPFO
WDI
RESETVCC
ADM690–ADM695
POWER FAIL RESET OUTPUTRESET is an active low output which provides a RESET signal
to the Microprocessor whenever VCC is at an invalid level. When
VCC falls below the reset threshold, the RESET output is forced
low. The nominal reset voltage threshold is 4.65 V (ADM690/
ADM691/ADM694/ADM695) or 4.4 V (ADM692/ADM693).
Figure 2.Power Fail Reset Timing
On power-up RESET will remain low for 50 ms (200 ms for
ADM694 and ADM695) after VCC rises above the appropriate
reset threshold. This allows time for the power supply and mi-
croprocessor to stabilize. On power-down, the RESET output
remains low with VCC as low as 1 V. This ensures that the
microprocessor is held in a stable shutdown condition.
This RESET active time is adjustable on the ADM691/ADM693/
ADM695 by using an external oscillator or by connecting an
external capacitor to the OSC IN pin. Refer to Table I and
Figure 4.
The guaranteed minimum and maximum thresholds of the
ADM690/ADM691/ADM694/ADM695 are 4.5 V and 4.73 V,
while the guaranteed thresholds of the ADM692/ADM693 are
4.25 V and 4.48 V. The ADM690/ADM691/ADM694/ADM695
is, therefore, compatible with 5 V supplies with a +10%, –5%
tolerance while the ADM692/ADM693 is compatible with 5 V 10% supplies. The reset threshold comparator has approxi-
mately 50 mV of hysteresis. The response time of the reset volt-
age comparator is less than 1 μs. If glitches are present on the
VCC line which could cause spurious reset pulses, then VCC
should be decoupled close to the device.
In addition to RESET the ADM691/ADM693/ADM695 con-
tain an active high RESET output. This is the complement of
RESET and is intended for processors requiring an active high
RESET signal.
Watchdog Timer RESETThe watchdog timer circuit monitors the activity of the micro-
processor in order to check that it is not stalled in an indefinite
loop. An output line on the processor is used to toggle the
Watchdog Input (WDI) line. If this line is not toggled within the
selected timeout period, a RESET pulse is generated. The
nominal watchdog timeout period is preset at 1.6 seconds on the
ADM690/ADM692/ADM694. The ADM691/ADM693/ADM695
may be configured for either a fixed “short” 100 ms or a “long”
1.6 second timeout period or for an adjustable timeout period.
If the “short” period is selected, some systems may be unable to
service the watchdog timer immediately after a reset, so the
ADM691/ADM693/ADM695 automatically selects the “long”
timeout period directly after a reset is issued. The watchdog
timer is restarted at the end of reset, whether the reset was
caused by lack of activity on WDI or by VCC falling below the
reset threshold.
The normal (short) timeout period becomes effective following
the first transition of WDI after RESET has gone inactive. The
watchdog timeout period restarts with each transition on the
WDI pin. To ensure that the watchdog timer does not time out,
either a high-to-low or low-to-high transition on the WDI pin
must occur at or less than the minimum timeout period. If WDI
remains permanently either high or low, reset pulses will be
issued after each “long” timeout period (1.6 s). The watchdog
monitor can be deactivated by floating the Watchdog Input
(WDI) or by connecting it to midsupply.
Figure 3.Watchdog Timeout Period and Reset Active
Time
Table I.ADM691, ADM693, ADM695 Reset Pulse Width and Watchdog Timeout SelectionsNOTE
With the OSC SEL pin low, OSC IN can be driven by an external clock signal, or an external capacitor can be connected between OSC IN and GND. The nominal
internal oscillator frequency is 10.24 kHz. The nominal oscillator frequency with external capacitor is: FOSC (Hz) = 184,000/C (pF).
The watchdog timeout period is fixed at 1.6 seconds, and the
reset pulse width is fixed at 50 ms on the ADM690/ADM692.
On the ADM694 the watchdog timeout period is also 1.6 sec-
onds but the reset pulse width is fixed at 200 ms. The ADM691/
ADM693/ADM695 allow these times to be adjusted as shown
in Table I. Figure 4 shows the various oscillator configurations
which can be used to adjust the reset pulse width and watchdog
timeout period.
The internal oscillator is enabled when OSC SEL is high or
floating. In this mode, OSC IN selects between the 1.6 second
and 100 ms watchdog timeout periods. With OSC IN connected
high or floating, the 1.6 second timeout period is selected; while
with it connected low, the 100 ms timeout period is selected. In
either case, immediately after a reset, the timeout period is 1.6
seconds. This gives the microprocessor time to reinitialize the
system. If OSC IN is low, then the 100 ms watchdog period be-
comes effective after the first transition of WDI. The software
should be written such that the I/O port driving WDI is left in
its power-up reset state until the initialization routines are com-
pleted and the microprocessor is able to toggle WDI at the mini-
mum watchdog timeout period of 70 ms.
Watchdog Output (WDO)The Watchdog Output WDO (ADM691/ADM693/ADM695)
provides a status output which goes low if the watchdog timer
“times out” and remains low until set high by the next transition
on the Watchdog Input. WDO is also set high when VCC goes
below the reset threshold.
Figure 4a.External Clock Source
Figure 4c.
Figure 4d.
ADM690–ADM695
CE Gating and RAM Write Protection (ADM691/ADM693/
ADM695)The ADM691/ADM693/ADM695 products include memory
protection circuitry which ensures the integrity of data in mem-
ory by preventing write operations when VCC is at an invalid
level. There are two additional pins, CEIN and CEOUT, which
may be used to control the Chip Enable or Write inputs of
CMOS RAM. When VCC is present, CEOUT is a buffered replica
of CEIN, with a 5 ns propagation delay. When VCC falls below
the reset voltage threshold or VBATT, an internal gate forces
CEOUT high, independent of CEIN.
CEOUT typically drives the CE, CS, or write input of battery
backed up CMOS RAM. This ensures the integrity of the data
in memory by preventing write operations when VCC is at an in-
valid level. Similar protection of EEPROMs can be achieved by
using the CEOUT to drive the store or write inputs.
If the 5 ns typical propagation delay of CEOUT is excessive, con-
nect CEIN to GND and use the resulting CEOUT to control a
high speed external logic gate.
Power Fail Warning ComparatorAn additional comparator is provided for early warning of failure
in the microprocessor’s power supply. The Power Fail Input
(PFI) is compared to an internal +1.3 V reference. The Power
Fail Output (PFO) goes low when the voltage at PFI is less than
1.3 V. Typically PFI is driven by an external voltage divider
which senses either the unregulated dc input to the system’s 5 V
regulator or the regulated 5 V output. The voltage divider ratio
can be chosen such that the voltage at PFI falls below 1.3 V sev-
eral milliseconds before the +5 V power supply falls below the
reset threshold. PFO is normally used to interrupt the micropro-
cessor so that data can be stored in RAM and the shut down
procedure executed before power is lost
Table II.Figure 6.Chip Enable Timing
