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ADM690AARN-ADM692AAN-ADM802LAN-ADM802LARN-ADM802MAN-ADM802MARN-ADM805LAN-ADM805LARN-ADM805MAN-ADM805MARN
Microprocessor Supervisory Circuits
REV.0
Microprocessor
1.25V
*4.4V FOR ADM692A/ADM802M/ADM805M
ADM805L
ADM805M
POWER FAIL
OUTPUT (PFO)
POWER FAIL
INPUT (PFI)
( ) = ADM805L/M ONLY
Microprocessor Systems
Computers
Controllers
Intelligent Instruments
GENERAL DESCRIPTIONThe ADM690A/ADM692A/ADM802L/M/ADM805L/M
family of supervisory circuits offers complete single chip
solutions for power supply monitoring and battery control
functions in microprocessor systems. These functions include
μP reset, backup battery switchover, watchdog timer, and power
failure warning.
The ADM690A/ADM692A/ADM802L/M/ADM805L/M are
available in 8-pin packages and provide:Power-on reset output during power-up, power-down and
brownout conditions. The RESET output remains opera-
tional with VCC as low as 1 V.Battery backup switching for CMOS RAM, CMOS
microprocessor or other low power devices.A reset pulse if the optional watchdog timer has not been
toggled within 1.6 seconds.A 1.25 V threshold detector for power fail warning, low battery
detection, or to monitor a power supply other than +5 V.
On the ADM690A/ADM802L/ADM805L the reset voltage
threshold is 4.65 V. On the ADM692A/ADM802M/
ADM805M, the reset voltage threshold is 4.40 V.
The ADM802L/ADM802M guarantee power fail accuracies to
±2%.
The ADM805L/M provides an active high reset output, RESET
instead of RESET.
The family of products is fabricated using an advanced epitaxial
CMOS process combining low power consumption and high
reliability. RESET assertion is guaranteed with VCC as low as 1 V.
They provide a pin-compatible upgrade for the MAX690A/
MAX692A/MAX802L/MAX802M/MAX805L
All parts are available in 8-pin DIP and SOIC packages. The
ADM690A is also available in a new space-saving microSOIC
package.
ADM690A/ADM692A/ADM802L/M/ADM805L/M–SPECIFICATIONS
(VCC = 4.75 V to 5.5 V (ADM690A/ADM802L/ADM805L), VCC = 4.5 V to 5.5 V, (ADM692A/ADM802M/ADM805M), VBATT = +2.8 V, TA = TMIN to TMAX
unless otherwise noted)RESET THRESHOLD
NOTESEither VCC or VBATT can be 0 V if the other > +2.0 V.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*(TA = +25°C unless otherwise noted)
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +6 V
VBATT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +6 V
All Other Inputs . . . . . . . . . . . . . . . . . .–0.3 V to VCC + 0.3 V
Input Current
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 mA
VBATT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 mA
GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 mA
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . .20 mA
Power Dissipation, N-8 DIP . . . . . . . . . . . . . . . . . . .400 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . .120°C/W
Power Dissipation, SO-8 SOIC . . . . . . . . . . . . . . . . .500 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . .110°C/W
Operating Temperature Range
Industrial (A Version) . . . . . . . . . . . . . . . .–40°C to +85°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . .+300°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>4 kV
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum ratings for extended periods of time may affect device reliability.
ORDERING GUIDE
PIN CONFIGURATIONS
PIN FUNCTION DESCRIPTION
ADM690A/ADM692A/ADM802L/M/ADM805L/M
Typical Performance Curves
OUT
– V
2.25Figure 1.Output Voltage vs. Load Current in Battery
Backup
PFO
1.3V
PFI
1.2VFigure 2.Power Fail Comparator Response Time L � H
VCC
RESETFigure 3.ADM690A RESET Response Time
Figure 6.RESET Output Voltage vs. VCC
1.25V
*4.4V FOR ADM692A/ADM802M/ADM805M
ADM802L
ADM802M
ADM805L
ADM805M
POWER FAIL
OUTPUT (PFO)
POWER FAIL
INPUT (PFI)
( ) = ADM805L/M ONLYFigure 7.Functional Block Diagram
POWER FAIL RESET, RESETRESET is an active low output which provides a RESET signal
to the microprocessor whenever VCC is at an invalid level. When
VCC falls below the reset threshold, the RESET output is forced
low. The nominal reset voltage threshold is 4.65 V (ADM690A/
ADM802L/ADM805L or 4.4 V ADM692A/ADM802M/
ADM805M.
On power-up RESET will remain low for 200 ms after VCC rises
above the reset threshold. This allows time for the power supply
and microprocessor to stabilize. On power-down, the RESET
output remains low with VCC as low as 1 V. This ensures that
the microprocessor is held in a stable shutdown condition.
The guaranteed minimum and maximum thresholds are as follows:
ADM690A/ADM802L/ADM805L: 4.5 V and 4.75 V
ADM692A: 4.25 V and 4.5 V.
ADM802L: 4.55 V and 4.7 V
ADM802M: 4.3 V and 4.45 V
The ADM805L and ADM805M contain an active high reset
output. This is the complement of RESET and is intended for
processors requiring an active high RESET signal.
The guaranteed minimum and maximum thresholds for the
ADM805 are:
ADM805L: 4.5 V and 4.75 V
ADM805M: 4.25 V and 4.5 V.
Watchdog Timer RESET, RESETThe watchdog timer circuit monitors the activity of the micro-
processor in order to check that it is not stalled in an indefinite
loop. An output line on the processor is used to toggle the
Watchdog Input (WDI) line. If this line is not toggled within
1.6 seconds, a RESET pulse is generated. The watchdog
timeout period restarts with each transition on the WDI pin. To
ensure that the watchdog timer does not time out, either a
high-to-low or low-to-high transition on the WDI pin must
occur at or less than the minimum timeout period. If WDI
remains permanently either high or low, reset pulses will be
Figure 8.Timing Diagram
BATTERY SWITCHOVER SECTIONDuring normal operation with VCC higher than the reset
threshold, VCC is internally switched to VOUT via an internal
PMOS transistor switch. This switch has a typical on-resistance
of less than 1 Ω and can supply up to 100 mA at the VOUT
terminal. Once VCC falls below the reset threshold, the higher of
VCC or VBATT is switched to VOUT. This means that VBATT
connects to VOUT only when VCC is below the reset threshold
and VBATT is greater than VCC.
VOUT is normally used to drive a RAM memory bank which
may require instantaneous currents of greater than 100 mA. If
this is the case, then a bypass capacitor should be connected to
VOUT. The capacitor will provide the peak current transients to the
RAM. A capacitance value of 0.1μF or greater may be used.
A 9 Ω MOSFET switch connects the VBATT input to VOUT
during battery backup. This MOSFET has very low input-to-
output differential (dropout voltage) at the low current levels
required for battery backup of CMOS RAM or other low power
CMOS circuitry. The supply current in battery backup is
typically 0.05 μA.
Typically 3 V batteries are used as the backup supply. High
value capacitors, either standard electrolytic or the farad size
double layer capacitors, can also be used for short-term memory
back up. A small charging current of typically 10 nA (0.1 μA
max) flows out of the VBATT terminal. This current is useful for
maintaining rechargeable batteries in a fully charged condition.
This extends the life of the back up battery by compensating for
its self discharge current. Also note that this current poses no
problem when lithium batteries are used for back up since the
maximum charging current (0.1 μA) is safe for even the smallest
lithium cells.
If the battery-switchover section is not used, VBATT should be
connected to GND and VOUT should be connected to VCC.
ADM690A/ADM692A/ADM802L/M/ADM805L/M
Table I.Input and Output Status in Battery Backup Mode
Power Fail ComparatorThe power fail comparator is an independent comparator
that may be used to monitor the input power supply. The
comparator’s inverting input is internally connected to a 1.25
V reference voltage. The noninverting input is available at the
PFI input. This input may be used to monitor the input power
supply via a resistive divider network. When the voltage on the
PFI input drops below 1.25 V, the comparator output (PFO)
goes low indicating a power failure. For early warning of power
failure the comparator may be used to monitor the preregulator
input simply by choosing an appropriate resistive divider
network. The PFO output can be used to interrupt the
processor so that a shutdown procedure is implemented before
the power is lost.
POWER FAIL
OUTPUT
INPUT
POWERFigure 9.Power Fail Comparator
Adding Hysteresis to the Power Fail ComparatorFor increased noise immunity, hysteresis may be added to the
power fail comparator. Since the comparator circuit is non-
inverting, hysteresis can be added simply by connecting a
resistor between the PFO output and the PFI input as shown in
Figure 10. When PFO is low, resistor R3 sinks current from the
summing junction at the PFI pin. When PFO is high, resistor
R3 sources current into the PFI summing junction. This results
in differing trip levels for the comparator. Further noise
immunity may be achieved by connecting a capacitor between
PFI and GND.
Figure 10. Adding Hysteresis to the Power Fail
Comparator
TYPICAL APPLICATIONSFigure 11 shows a typical power monitoring, battery backup
application. VOUT powers the CMOS RAM. Under normal
operating conditions with VCC present, VOUT is internally
connected to VCC. If a power failure occurs, VCC will decay and
VOUT will be switched to VBATT thereby maintaining power for
the CMOS RAM. A RESET pulse is also generated when VCC
falls below the reset threshold.
CMOS RAM
POWER
µP RESET
µP NMI
I/O LINE
µP SYSTEMGND
VBATT
PFI
UNREGULATED
+5V
BATTERYFigure 11.Typical Application Circuit
The watchdog timer input (WDI) monitors an I/O line from the
μP system. This line must be toggled once every 1.6 seconds to
verify correct software execution. Failure to toggle the line
indicates that the μP system is not correctly executing its
program and may be tied up in an endless loop. If this happens,
a reset pulse is generated to initialize the processor.
