ADM5180JN-ADM5180JP Fast Delivery |IC PHOENIX CO.,LIMITED

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ADM5180JN-ADM5180JP
Octal, RS-232/RS-423 Line Receiver
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Eight Differential Line Receivers in One Package
Meets EIA Standard EIA-232E, 423A, 422A and
CCITT V.10, V.11, V.28
Single +5 V Supply
Differential Inputs Withstand ±25 V
Internal Hysteresis
Low Power CMOS –3.5 mA Supply Current
TTL/CMOS Compatible Outputs
Available in 28-Pin DIP and PLCC Packages
Low Power Replacement for UC5180C/NE5180
APPLICATIONS
High Speed Communication
Computer I-O Ports
Peripherals
High Speed Modems
Printers
Logic Level Translation
Octal, RS-232/RS-423 Line Receiver
GENERAL DESCRIPTION
The ADM5180 is an octal differential line receiver suitable for a
wide range of digital communication systems with data rates up to
200 kB/s. Input signals conforming to EIA Standards 232-E, 422A
and CCITT V.10, V.11, V.28, X.26, and X.27 are accepted and
translated into TTL /CMOS output signal levels.
The ADM5180 is a superior upgrade for the UC5180C and the
NE5180. It is fabricated on an advanced BiCMOS process,
allowing high speed bipolar circuitry to be combined with low
power CMOS. This minimizes the power consumption to less than
25 mW.
A failsafe function ensures a known output state under a variety of
input fault conditions as defined in RS-422A and RS-423A. The
failsafe function is controlled by FS1 and FS2. Each controls four
receivers. With FS = Low and a fault condition the output is forced
low while if FS = High, the output is forced high.
The device is available in both 28-pin DIP and 28-lead PLCC
packages.
Truth Table
FS1
FS2
OUTPUTS
FAILSAFE FUNCTION
ADM5180–SPECIFICATIONS
(VDD = +5 V ± 5%, Input Common-Mode Range = ±7 V. All Specifications TMIN to
TMAX unless otherwise noted.)
TIMING CHARACTERISTICS
(VDD = +5 V ± 5%. All Specifications TMIN to TMAX unless otherwise noted)
NOTE
1Only one output may be shorted at any time.
Specifications subject to change without notice.
Specifications subject to change without notice.
ORDERING GUIDE
ABSOLUTE MAXIMUM RATINGS1
(TA = 25°C unless otherwise noted)
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7 V
Common-Mode Input Voltage . . . . . . . . . . . . . . . . . . . . . .+15 V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . .+25 V
Failsafe Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to VCC
Output Short Circuit Duration . . . . . . . . . . . . . . . . .Continuous2
Power Dissipation Plastic DIP . . . . . . . . . . . . . . . . . . . .1250 mW
(Derate at 12.5 mW/°C Above +50°C)
θJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . .75°C/W
Power Dissipation PLCC . . . . . . . . . . . . . . . . . . . . . . .1000 mW
(Derate at 12.5 mW/°C Above +50°C)
θJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . .+80°C/W
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADM5180 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
8mA
440µA
OUTPUT
PIN
50pF
+2.1V
Figure 2.Timing Test Load
VINVTH2VTL2VTH1VTL1
Figure 1.VTL, VTH, VH Definition
(VIN+) – (VIN–)
OUTPUT
Figure 3.Timing Waveform
Operating Temperature Range
Commercial ( J Version) . . . . . . . . . . . . . . . . . . .0°C to +70°C
Industrial (A Version) . . . . . . . . . . . . . . . . . . .–40°C to +80°C
Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . . . . .+300°C
Vapour Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
NOTESThis is a stress rating only and functional operation of the device at these or any
other conditions above those indicated in the operation sections of this speci-
fication is not implied. Exposure to absolute maximum rating conditions for
extended periods of time may affect reliability.Only one output should be shorted at any time.
PIN DESCRIPTION
FS1, FS2
ADM5180
PIN CONFIGURATIONS
DIP
VDD
FS1FS2FOF+F–EOE+
GNDE–
PLCC
FS2
FS1DE
GND
APPLICATIONS INFORMATION
FAILSAFE OPERATION
The ADM5180 provides a failsafe operating mode to guard against
input fault conditions as defined in RS-422A and RS-423A
standards. The fault conditions are (1) Driver in power-off
condition, (2) Receiver not interconnected with Driver, (3) Open-
circuited interconnecting cable, and (4) Short-circuited intercon-
necting cable. If any of these four fault conditions occurs at the
inputs of a receiver, then the output of that receiver is driven to a
known logic level. The failsafe level is programmed using the
failsafe (FS) input. There are two failsafe inputs, FS1 and FS2
which each control four receivers. FSI controls receivers A...D
and FS2 controls receivers E...H. A connection to VDD on the
failsafe input sets the output high under fault conditions while a
connection to GND sets the output low.
Input Filtering
The ADM5180 contains internal low pass filtering for additional
noise rejection. Frequencies above the passband will be rejected.
For the specified input (5.5 MHz at ±500 mV) the input stage
attenuates the signal such that the threshold levels are not reached
and therefore no change of state occurs on the output. The filtering
is a function of both amplitude and and frequency. As the signal
amplitude decreases then the rejected frequency will decrease.
TIE TO GND FOR
RS232
INPUT
VDD
VFAILSAFE
VOUT
Figure 4.EIA-232/V.28 Data Transmission
INPUT
VDD
VFAILSAFERS422A/V.11
LINE DRIVER
Figure 5.RS-422A/V.11 Data Transmission
Typical Performance Characteristics
IDD – mA
– V
TEMPERATURE – °C
IDD
– mA
PRINTED IN U.S.A.
C1854–7.5–10/93
ADM5180
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead Plastic Leaded Chip Carrier (PLCC)
(P Suffix)
28-Lead Plastic DIP
(N Suffix)
Vpp – V (VID = ±Vpp/2)
PROPAGATION DELAY – ns
Figure 8.Propagation Delay vs. AmplitudeFigure 10.Rejectable Input Frequency vs. Amplitude
IOH – mA
– V2
REJECTABLE INPUT FREQUENCY – MHz
Vpp – V (VID = ±Vpp/2)
IOL – mA
– mVAAAAAAA
PIN 1
0.600 (15.24)
0.195 (4.95)
(6.35)
MAX
0.022 (0.558)
0.014 (0.356)
(2.54)
BSC
0.200 (5.05)
0.125 (3.18)
0.070 (1.77)
MAX
0.060 (1.52)
0.015 (0.38)
1.565 (39.70)
1.380 (35.10)
Figure 9.High Level Output Voltage vs. Output
Source Current
Figure 11.Low Level Output Voltage vs. Output
Sink Current

Partno	Mfg	Dc	Qty	Available	Descript
ADM5180JN	AD	N/a	86	avai	Octal, RS-232/RS-423 Line Receiver
ADM5180JP		N/a	300	avai	Octal, RS-232/RS-423 Line Receiver