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ADM4851AR-ADM4854AR-ADM4855AR-ADM4856AR
Half Duplex RS-485/RS-22 Transceiver w/115kbps Data Rate
5 V Slew-Rate Limited Half- and Full-Duplex
RS-485/RS-422 Transceivers
Rev. 0
FEATURES
EIA RS-485-/RS-422-compliant
Data rate options
ADM4850/ADM4854—115 kbps
ADM4851/ADM4855—500 kbps
ADM4852/ADM4856—2.5 Mbps
ADM4853/ADM4857—10 Mbps
Half- and full-duplex options
Reduced slew rates for low EMI
True fail-safe receiver inputs
5 µA (maximum) supply current in shutdown mode
Up to 256 transceivers on one bus
Outputs high-z when disabled or powered off
−7 V to +12 V bus common-mode range
Thermal shutdown and short-circuit protection
Pin-compatible with MAX308x
Specified over the −40°C to +85°C temperature range
Available in 8-lead SOIC and LFCSP packages
APPLICATIONS
Low power RS-485 applications
EMI-sensitive systems
DTE-DCE interfaces
Industrial control
Packet switching
Local area networks
Level translators
FUNCTIONAL BLOCK DIAGRAM GND
VCC
GND
VCC
Figure 1.
GENERAL DESCRIPTION The ADM4850−ADM4857 are differential line transceivers
suitable for high speed half- and full-duplex data communication
on multipoint bus transmission lines. They are designed for
balanced data transmission and comply with EIA Standards
RS-485 and RS-422. The ADM4850−ADM4853 are half-duplex
transceivers, which share differential lines and have separate
enable inputs for the driver and receiver. The full-duplex
ADM4854−ADM4857 transceivers have dedicated differential
line driver outputs and receiver inputs.
The parts have a 1/8-unit-load receiver input impedance, which
allows up to 256 transceivers on one bus. Since only one driver
should be enabled at any time, the output of a disabled or pow-
ered-down driver is three-stated to avoid overloading the bus.
The receiver inputs have a true fail-safe feature, which ensures a
logic high output level when the inputs are open or shorted.
This guarantees that the receiver outputs are in a known state
before communication begins and when communication ends.
The driver outputs are slew-rate limited to reduce EMI and data
errors caused by reflections from improperly terminated buses.
Excessive power dissipation caused by bus contention or by
output shorting is prevented with a thermal shutdown circuit.
The parts are fully specified over the commercial and industrial
temperature ranges, and are available in 8-lead SOIC and LFCSP
packages.
Table 1. Selection Table TABLE OF CONTENTS Specifications.....................................................................................3
ADM4850/ADM4854 Timing Specifications...........................4
ADM4851/ADM4855 Timing Specifications...........................4
ADM4852/ADM4856 Timing Specifications...........................5
ADM4853/ADM4857 Timing Specifications...........................5
Absolute Maximum Ratings............................................................6
ESD Caution..................................................................................6
Pin Configurations and Function Descriptions...........................7
Test Circuits.......................................................................................8
Switching Characteristics................................................................9
Typical Performance Characteristics...........................................10
Circuit Description.........................................................................12
Slew-Rate Control......................................................................12
Receiver Input Filtering.............................................................12
Half-/Full-Duplex Operation...................................................12
High Receiver Input Impedance..............................................13
Three-State Bus Connection.....................................................13
Shutdown Mode.........................................................................13
Fail-Safe Operation....................................................................13
Current Limit and Thermal Shutdown...................................13
Outline Dimensions.......................................................................14
Ordering Guide..........................................................................15
REVISION HISTORY
10/04—Revision 0: Initial Version SPECIFICATIONS V = 5 V ± 5%, TA = TMIN to TMAX, unless otherwise noted.
Table 2. Guaranteed by design.
ADM4850/ADM4854 TIMING SPECIFICATIONS V = 5 V ± 5%, TA = TMIN to TMAX, unless otherwise noted.
Table 3. The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to
enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode.
ADM4851/ADM4855 TIMING SPECIFICATIONS V = 5 V ± 5%, TA = TMIN to TMAX, unless otherwise noted.
Table 4. The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to
enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode.
ADM4852/ADM4856 TIMING SPECIFICATIONS V = 5 V ± 5%, TA = TMIN to TMAX, unless otherwise noted.
Table 5. The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to
enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode.
ADM4853/ADM4857 TIMING SPECIFICATIONS V = 5 V ± 5%, TA = TMIN to TMAX, unless otherwise noted.
Table 6. 1 The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to
enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode.
ABSOLUTE MAXIMUM RATINGS
Table 7. Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VCCGNDB04931-002
AFigure 2. ADM4850–ADM4853 Pin Configuration
Table 8. ADM4850–ADM4853 Pin Descriptions
VCCA
GNDYB04931-003
ZFigure 3. ADM4854–ADM4857 Pin Configuration
Table 9. ADM4854–ADM4857 Pin Descriptions TEST CIRCUITS 04931-004
Figure 4. Driver Voltage Measurement
375Ω
375Ω
Figure 5. Driver Voltage Measurement over Common-Mode Voltage Range
04931-006
Figure 6. Driver Propagation Delay
VCC
VOUT
DE IN
0V OR 3VS1
Figure 7. Driver Enable/Disable
VOUT
Figure 8. Receiver Propagation Delay
VCC
+1.5V
–1.5V
RE IN
Figure 9. Receiver Enable/Disable
