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ADM2483BRW
Slew-Rate Limited Isolated RS-485 Transceiver
Half-Duplex iCoupler®
Isolated RS-485 Transceiver
Rev. 0
FEATURES
RS-485 transceiver with electrical data isolation
Complies with ANSI TIA/EIA RS-485-A-1998 and
ISO 8482:1987(E)
500 kbps data rate
Slew rate–limited driver outputs
Low power operation: 2.5 mA max
Suitable for 5 V or 3 V operation (VDD1)
High common-mode transient immunity: >25 kV/μs
True fail-safe receiver inputs
Glitch-free power-up/-down protection
256 nodes on bus
Thermal shutdown protection
Safety and regulatory approvals:
UL recognition: 2500 VRMS for 1 minute per UL 1577
CSA Component Acceptance Notice #5A
VDE Certificate of Conformity
DIN EN 60747-5-2 (VDE 0884 Rev. 2): 2003-01
DIN EN 60950 (VDE 0805): 2001-12; EN 60950: 2000
VIORM = 560 V peak
Operating temperature range: −40°C to +85°C
APPLICATIONS
Low power RS-485/RS-422 networks
Isolated interfaces
Building control networks
Multipoint data transmission systems
FUNCTIONAL BLOCK DIAGRAM
GND1GND2
TxD
POWER_VALID
RxDFigure 1.
GENERAL DESCRIPTION The ADM2483 differential bus transceiver is an integrated,
galvanically isolated component designed for bidirectional data
communication on balanced, multipoint bus transmission lines.
It complies with ANSI TIA/EIA RS-485-A and ISO
8482:1987(E). Using Analog Devices’ iCoupler
® technology, the
ADM2483 combines a 3-channel isolator, a 3-state differential
line driver, and a differential input receiver into a single
package. The logic side of the device is powered with either a
5 V or 3 V supply, while the bus side uses a 5 V supply only.
The ADM2483 is slew-limited to reduce reflections with
improperly terminated transmission lines. The controlled slew
rate limits the data rate to 500 kbps. The device’s input
impedance is 96 kΩ, allowing up to 256 transceivers on the bus.
Its driver has an active-high enable. The driver differential
outputs and receiver differential inputs are connected internally
to form a differential I/O port. When the driver is disabled or
when VDD1 or VDD2 = 0, this imposes minimal loading on the
bus. An active-high receiver disable, which causes the receive
output to enter a high impedance state, is provided as well.
The receiver inputs have a true fail-safe feature that ensures a
logic-high receiver output level when the inputs are open or
shorted. This guarantees that the receiver outputs are in a
known state before communication begins and at the point
when communication ends.
Current limiting and thermal shutdown features protect against
output short circuits and bus contention situations that might
cause excessive power dissipation. The part is fully specified
over the industrial temperature range and is available in a
16-lead wide body SOIC package.
TABLE OF CONTENTS Specifications.....................................................................................3
Timing Specifications.......................................................................4
Absolute Maximum Ratings............................................................5
ESD Caution..................................................................................5
Package Characteristics...............................................................6
Regulatory Information...............................................................6
Insulation and Safety-Related Specifications............................6
VDE 0884 Insulation Characteristics, .......................................7
Pin Configurations and Function Descriptions...........................8
Test Circuits.......................................................................................9
Switching Characteristics..............................................................10
Typical Performance Characteristics...........................................11
Circuit Description.........................................................................14
Electrical Isolation......................................................................14
Truth Tables.................................................................................15
Power-Up/Power-Down Characteristics.................................15
Thermal Shutdown....................................................................15
True Fail-Safe Receiver Inputs..................................................15
Magnetic Field Immunity..........................................................15
Applications Information..............................................................17
Power_Valid Input.....................................................................17
Isolated Power Supply Circuit..................................................17
Outline Dimensions.......................................................................18
Ordering Guide..........................................................................18
REVISION HISTORY
10-04—Revision 0: Initial Version
SPECIFICATIONS 2.7 ≤ VDD1 ≤ 5.5 V, 4.75 V ≤ VDD2 ≤ 5.25 V, TA = TMIN to TMAX, unless otherwise noted.
Table 1. 1 Common-mode transient immunity is the maximum common-mode voltage slew rate that can be sustained while maintaining specification-compliant operation. VCM
is the common-mode potential difference between the logic and bus sides. The transient magnitude is the range over which the common mode is slewed. The
common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.
TIMING SPECIFICATIONS 2.7 ≤ VDD1 ≤ 5.5 V, 4.75 V ≤ VDD2 ≤ 5.25 V, TA = TMIN to TMAX, unless otherwise noted.
Table 2. ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. All voltages are relative to their respective ground.
Table 3. Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
PACKAGE CHARACTERISTICS
Table 4. Device considered a two-terminal device: Pins 1, 2, 3, 4, 5, 6, 7, and 8 shorted together, and Pins 9, 10, 11, 12, 13, 14, 15, and 16 shorted together.
2 Input capacitance is from any input data pin to ground.
REGULATORY INFORMATION The ADM2483 has been approved by the following organizations:
Table 5. In accordance with UL1577, each ADM2483 is proof-tested by applying an insulation test voltage ≥ 3000 Vrms for 1 s (current leakage detection limit = 5 µA).
2 In accordance with VDE 0884, each ADM2483 is proof-tested by applying an insulation test voltage ≥ 1050 VPEAK for 1 s (partial discharge detection limit = 5 pC).
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 6.
VDE 0884 INSULATION CHARACTERISTICS1, 2
Table 7. Suitable for basic electrical isolation only within this safety limit data. Maintenance of this safety data shall be ensured by means of protective circuits. An asterisk (*) on the physical package denotes VDE 0884 approval for 560 V peak working voltage.
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS NC = NO CONNECT
VDD1VDD2
GND1*GND2*
RxDNCBA
TxDNCNC
GND1*GND2*PINS 2 AND 8 ARE INTERNALLY CONNECTED.
EITHER OR BOTH MAY BE USED FOR GND1.
PINS 9 AND 15 ARE INTERNALLY CONNECTED.
EITHER OR BOTH MAY BE USED FOR GND2.
Figure 2. Pin Configuration
Table 8. Pin Function Descriptions TEST CIRCUITS Figure 3. Driver Voltage Measurement
375Ω
Figure 4. Driver Voltage Measurement
Figure 5. Driver Propagation Delay
0V OR 3V04736-006
DE INS2
VCCFigure 6. Driver Enable/Disable
04736-007
VOUTFigure 7. Receiver Propagation Delay
VOUT
VCC+1.5V–1.5V
Figure 8. Receiver Enable/Disable
SWITCHING CHARACTERISTICS tPLH
–VO
tSKEW= |tPLH–tPHL|
Figure 9. Driver Propagation Delay, Rise/Fall Timing
VOH
VOL
A–B
RxD
Figure 10. Receiver Propagation Delay
2.3V
VOH
VOL
0.7VDD1
0.3VDD1
2.3V
A, B
A, B
tZL
tZH
Figure 11. Driver Enable/Disable Timing
VOH
VOL–0.5V
0.7VDD1
0.3VDD1
RxD
RxD
O/P LOW
O/P HIGH
1.5V
1.5V
tZL
tZH
Figure 12. Receiver Enable/Disable Timing
