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ADM1073ARUADIN/a4avai-48 V Full Feature Hot Swap Controller
ADM1073ARUZADN/a500avai-48 V Full Feature Hot Swap Controller
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ADM1073ARU-ADM1073ARUZ-ADM1073ARUZ-REEL7
-48 V Full Feature Hot Swap Controller
Full-Feature −48 V Hot Swap ControllerRev. 0
FEATURES
Precision inrush linear current limit
Soft start inrush current limit profiling
Precision maximum on-time in current limit
Maximum on-time modulated by FET drain voltage for
additional SOA protection
Adjustable PWM retry scheme and multiple device cascading
capability for charging large capacitive loads
Limited number of PWM cycles for FET SOA protection under
short circuit condition
Ability to configure device as continuous autoretry with a
5-second cooling period
Shunt regulator topology to allow very large transient input
supplies
Separate UV and OV pins for programming allowable input
supply window
Programmable OV hysteresis using current source into pin
when supply is high
Programmable UV hysteresis using current sink from pin
when supply is low
PWRGD output indicates when capacitor charging complete
SPLYGD output indicates when supply is within
valid window
LATCHED output indicates the end of the retry cycle before
load capacitance is charged
SHDN input for user-commanded shutdown
RESTART input for user-triggered 5-second shutdown and
autorestart— virtual card reseat
FUNCTIONAL BLOCK DIAGRAM

04488-P
rG-001
LATCHEDRESTART
SPLYGDVIN
TIMER
SHDN
VEE
SENSE
GATE
DRAIN
PWRGD

Figure 1.
APPLICATIONS
Central office switching
Telecommunication and data communication equipment
−48 V distributed power systems
Negative power supply control
High availability servers
−48 V power supply modules
Disk arrays
GENERAL DESCRIPTION

The ADM1073 is a full-feature, negative voltage, hot swap
controller that allows boards to be safely inserted and removed
from a live −48 V backplane. The part provides precise and
robust current limiting, and protection against both transient
and nontransient short circuits in overvoltage and undervoltage
conditions. The ADM1073 can operate from a negative voltage
of −18 V to −80 V and can tolerate transient voltages of up to
−200 V.
Inrush current is limited to a programmable value by control-
ling the gate drive of an external N-channel FET. The maximum
current limit is set by the choice of the sense resistor, RSENSE.
A built-in soft start function allows control of the inrush
current profile by an external capacitor on the soft start (SS)
pin.
An external capacitor on the TIMER pin determines the time
for which the FET gate is controlled to be high when maximum
inrush current flows. The ADM1073 employs a limited consec-
utive retry scheme, whereby, if the load capacitance is not fully
charged within one attempt, the FET gate is pulled low and
retries after a cooling period. (continued on Page 3)
TABLE OF CONTENTS
General Description.........................................................................3
Specifications.....................................................................................4
Absolute Maximum Ratings............................................................6
Thermal Characteristics..............................................................6
ESD Caution..................................................................................6
Pin Configuration and Function Descriptions.............................7
Typical Performance Characteristics.............................................8
Functional Description..................................................................13
Hot Circuit Insertion.................................................................13
Initial Startup..............................................................................13
Board Removal...........................................................................14
Controlling the Current.............................................................14
Sense.............................................................................................15
Sense Resistor..............................................................................15
Soft Start (SS Pin).......................................................................15
GATE............................................................................................15
VIN.................................................................................................15
VEE.................................................................................................15
Timing Control—TIMER.........................................................15
Drain............................................................................................16
PWRGD.......................................................................................16
LATCHED...................................................................................16
SPLYGD.......................................................................................16
RESTART.....................................................................................16
SHDN...........................................................................................16
Undervoltage/Overvoltage Detection.....................................16
Functionality and Timing..............................................................18
Live Insertion..............................................................................18
Overvoltage and Undervoltage Faults.....................................18
Soft Start......................................................................................19
Current Faults.............................................................................20
Logic Inputs.................................................................................21
Kelvin Sense Resistor Connection...........................................21
Outline Dimensions.......................................................................22
Ordering Guide..........................................................................22
REVISION HISTORY

Revision 0: Initial Version
GENERAL DESCRIPTION
(continued from Page 1)
Further control of the inrush current is provided by modulating
the width of the pulses, depending on the drain-source voltage
across the FET. This allows maximum charge transfer to the
load capacitance while maintaining the FET in its safe operating
area (SOA).
The default duty cycle of the pulse train is 6%, decreasing to
2.5% with maximum FET drain-source voltage, with a
maximum of seven successive autorestarts. After seven
successive autorestarts, the fault is latched and the part goes into
shutdown, with the result that the external FET is disabled until
the power is reset. The LATCHED output signal indicates when
the seven retries are complete.
Further programmability is offered by allowing alteration of the
default 6% ratio. An extra resistor between the TIMER pin and
VEE allows the ratio of on-time to off-time to be decreased,
while a resistor between TIMER and VIN allows the ratio to be
increased.
The ADM1073 has separate UV and OV pins for undervoltage
and overvoltage detection. The FET is turned off, if a
nontransient voltage less than the undervoltage threshold
(typically −36 V) is detected on the UV pin, or if greater than
the overvoltage threshold (typically −80 V) is detected on the
OV pin. The operating voltage window of the ADM1073 is
programmable via resistor networks on the UV and OV pins.
The hysteresis levels on the undervoltage and overvoltage
detectors can also be altered (see the Undervoltage/Overvoltage
Detection section). The SPLYGD output signal indicates when
the backplane supply is within the externally programmable
operating voltage range.
Other functions include PWRGD output, which can be used to enable a power
module (the DRAIN pin is monitored to determine when
the load capacitance is fully charged) SHDN input to manually disable the GATE drive RESTART input to remotely initiate a 5 second shutdown
The ADM1073 is fabricated using BiCMOS technology for
minimal power consumption and is available in a 14-lead
TSSOP package.
SPECIFICATIONS
VDD = 0 V, VEE = −48 V; TA = −40°C to +85°C, unless otherwise noted.
Table 1.


ABSOLUTE MAXIMUM RATINGS
All voltages referred to VEE, TA = 25°C, unless otherwise noted.
Table 2.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL CHARACTERISTICS

14-lead TSSOP Package:
θJA = 240°C/W
θJC = 43°C/W
ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
RESTART
VIN
PWRGD
SENSE
SHDN
TIMER
DRAIN
VEE
LATCHED
GATE
SPLYGD

04488-P
rG-002
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions

TYPICAL PERFORMANCE CHARACTERISTICS
04488-P
rG-003
TEMPERATURE (°C)–50–35–20–51025405570

100

Figure 3. IIN vs. Temperature
04488-P
rG-004
VIN (V)
(mA)
1.0

Figure 4. IIN vs. VIN
04488-P
rG-005
TEMPERATURE (°C)–50–35–20–51025405570

Figure 5. RZ (VIN Forward Voltage) vs. Temperature
04488-P
rG-006
TEMPERATURE (°C)–50–35–20–51025405570
(V
11.5

Figure 6. VIN vs. Temperature
04488-P
rG-007
TEMPERATURE (°C)–50–35–20–5–1025405570
LKO
(V

Figure 7. Undervoltage Lockout, VLKO, vs. Temperature
04488-P
rG-008
TEMPERATURE (°C)–50–35–20–501025405570
LAY
(ms
100

Figure 8. POR Delay vs. Temperature
04488-P
rG-009
TEMPERATURE (°C)–50–35–20–51025405570
GATEL
(mV
100

Figure 9. VGATEL vs. Temperature
04488-P
rG-010
TEMPERATURE (°C)–50–35–20–51025405570
GATEH
(V)
12.0

Figure 10. VGATEH vs. Temperature
04488-P
rG-011
TEMPERATURE (°C)–50–35–20–51025405570
GATE

100

Figure 11. IGATE (Source) vs. Temperature
04488-P
rG-012
VGATE (V)
GATE
(mA)

Figure 12. IGATE (Source) vs. VGATE
04488-P
rG-013
TEMPERATURE (°C)–50–35–20–51025405570
GATE
(mA)

Figure 13. IGATE (FCL, Sink) vs. Temperature (VGATE = 2 V)
04488-P
rG-014
VGATE (V)1234567891011
GATE
(mA)
100

Figure 14. IGATE (FCL, Sink) vs. VGATE
04488-P
rG-015
TEMPERATURE (°C)–50–35–20–51025405570
(V
820

Figure 15. UV Threshold vs. Temperature
04488-P
rG-016
TEMPERATURE (°C)–50–35–20–501025405570
(V
1.90

Figure 16. OV Threshold vs. Temperature
04488-P
rG-017
TEMPERATURE (°C)–50–35–20–51025405570
LAY
(ms
0.4

Figure 17. UV Voltage Fault Filter Time vs. Temperature
04488-P
rG-018
TEMPERATURE (°C)–50–35–20–51025405570
LAY

Figure 18. OV Voltage Fault Filter Time vs. Temperature
04488-P
rG-019
TEMPERATURE (°C)–50–35–20–51025405570
SEN

3.0

Figure 19. ISENSE vs. Temperature (VSENSE = 50 mV)
04488-P
rG-020
VSENSE (V)
SEN

–20

Figure 20. ISENSE vs. (VSENSE − VEE)
04488-P
rG-021
TEMPERATURE (°C)–50–35–20–51025405570
V (
100

Figure 21. Voltage Limits for Load Current Control vs. Temperature
04488-P
rG-022
TEMPERATURE (°C)–50–35–20–51025405570
TIME
R THRE
OLD (V
1.5

Figure 22. High and Low TIMER Thresholds vs. Temperature
04488-P
rG-023
TEMPERATURE(°C)–50–35–20–51025405570
TIMER
(ms

Figure 23. Maximum Current Limit On-Time vs. Temperature
(IDRAIN = 4 µA, CTIMER = 47 nF)
04488-P
rG-024
CTIMER (nF)
TIMER (ms)

Figure 24. Current Limit On-Time vs. CTIMER (1 nF − 100 nF)
04488-P
rG-025
TEMPERATURE (°C)–50–35–20–51025405570

Figure 25. Current Limit PWM vs. Temperature
04488-P
rG-026
RTIMER (MΩ)0123456789

Figure 26. Current Limit PWM vs. RTIMER
04488-P
rG-027
TEMPERATURE (°C)–50–35–20–51025405570
tSH
(s
0.5

Figure 27. Continuous Short Circuit Time before Shutdown vs. Temperature
04488-P
rG-028
TEMPERATURE (°C)–50–35–20–51025405570
tRE
ART
(s

Figure 28. RESTART Time vs. Temperature
04488-P
rG-029
CSS (nF)0123456789
RAMP
(ms
3.0

Figure 29. Soft Start Ramp Time vs. CSS
04488-P
rG-030
TEMPERATURE (°C)–50–35–20–51025405570
/OV

Figure 30. IUV/OV vs. Temperature
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