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AH183-WLA , LOW POWER HALL EFFECT SWITCH
AH183-WLA , LOW POWER HALL EFFECT SWITCH
AH1883-ZG-7 , MICROPOWER, ULTRA-SENSITIVE HALL EFFECT SWITCH
AH1884-ZG-7 , MICROPOWER, ULTRA-SENSITIVE HALL EFFECT
AH1885-ZG-7 , MICROPOWER, ULTRA-SENSITIVE HALL EFFECT SWITCH
AH1886-ZG-7 , MICROPOWER, ULTRA-SENSITIVE HALL EFFECT
ADM1060ARU-ADM1060ARUZ
Multi Power Supply Sequencer & Supervisor
Communications System
Supervisory/Sequencing Circuit
FEATURES
Faults detected on 7 independent supplies
1 high voltage supply (2 V to 14.4 V)
4 positive voltage only supplies (2 V to 6 V)
2 positive/negative voltage supplies (+2 V to +6 V and –2 V to –6 V)
Watchdog detector input—timeout delay programmable from 200 ms to 12.8 sec
4 general-purpose logic inputs
Programmable logic block—combinatorial and sequencing logic control of all inputs and outputs
9 programmable output drivers:
Open collector (external resistor required)
Open collector with internal pull-up to VDD
Fast internal pull-up to VDD
Open collector with internal pull-up to VPn
Fast internal pull-up to VPn
Internally charge-pumped high drive (for use with
external N-channel FETs—PDOs 1 to 4 only)
EEPROM—256 bytes of user EEPROM
Industry-standard 2-wire bus interface (SMBus)
Guaranteed PDO low with VPn, VH = 1 V
APPLICATIONS
Central office systems
Servers
Infrastructure network boards
High density, multivoltage system cards
GENERAL DESCRIPTION The ADM1060 is a programmable supervisory/sequencing
device that offers a single chip solution for multiple power
supply fault detection and sequencing in communications
systems.
In central offices, servers, and other infrastructure systems, a
common backplane dc supply is reduced to multiple board sup-
plies using dc-to-dc converters. These multiple supplies are used
to power different sections of the board, such as 3.3 V logic
circuits, 5 V logic circuits, DSP core, and DSP I/O circuits. There
is usually a requirement that certain sections power up before
others; for example, a DSP core may need to power up before
the DSP I/O, or vice versa, to avoid damage, miscommunication,
or latch-up. The ADM1060 facilitates this, providing supply
fault detection and sequencing/combinatorial logic for up to
seven independent supplies. The seven supply fault detectors
consist of one high voltage detector (up to +14.4 V), two bipolar
voltage detectors (up to +6 V or down to −6 V), and four posi-
tive low voltage detectors (up to +6 V). All of the detectors can
be programmed to detect undervoltage, overvoltage, or out-of-
window (undervoltage or overvoltage) conditions. The inputs to
these supply fault detectors are via the VH (high voltage) pin,
VBn (positive or negative) pins, and VPn (positive only) pins.
Either the VH supply or one of the VPn supplies is used to
power the ADM1060 (whichever is highest). This ensures that
in the event of a supply failure, the ADM1060 is kept alive for as
long as possible, thus enabling a reliable fault flag to be asserted
and the system to be powered down in an ordered fashion.
Other inputs to the ADM1060 include a watchdog detector
(WDI) and four general-purpose inputs (GPIn). The watchdog
detector can be used to monitor a processor clock. If the clock
does not toggle (transition from low to high or from high to
low) within a programmable timeout period (up to 18 sec.), a
fail flag will assert. The four general-purpose inputs can be con-
figured as logic buffers or to detect positive/negative edges and
to generate a logic pulse or level from those edges. Thus, the
user can input control signals from other parts of the system
(e.g., RESET or POWER_GOOD) to gate the sequencing of the
supplies supervised by the ADM1060.
The ADM1060 features nine programmable driver outputs
(PDOs). All nine outputs can be configured to be logic outputs,
which can provide multiple functions for the end user such as
RESET generation, POWER_GOOD status, enabling of LDOs,
and watchdog timeout assertion. PDOs 1 to 4 have the added
feature of being able to provide an internally charge-pumped
high voltage for use as the gate drive of an external N-channel
FET that could be placed in the path of one of the supplies
being supervised.
(continued on Page 3)
Rev. B
TABLE OF CONTENTS General Description.........................................................................3
Specifications.....................................................................................5
Absolute Maximum Ratings............................................................7
Typical Performance Characteristics.............................................8
Inputs................................................................................................11
SFD REGISTER NAMES...........................................................14
SFD Register Bit Maps...............................................................15
Programming..................................................................................21
Logic.................................................................................................22
PLBA REGISTER BIT MAPS...................................................28
Outputs............................................................................................33
PROGRAMMABLE DRIVER OUTPUTS.............................33
Status/Faults....................................................................................35
FAULT REGISTERS...................................................................38
MASK REGISTERS....................................................................39
Programming..................................................................................40
WRITE OPERATIONS.............................................................44
READ OPERATIONS................................................................45
Pin Configuration and Functional Descriptions........................49
Outline Dimensions.......................................................................50
Ordering Guide..........................................................................50
REVISION HISTORY
12/03—Data sheet changed from Rev. A to Rev. B Changes to Specifications.............................................................................5
Changes to Outputs section............................................................33
Updated Outline Dimensions.........................................................50
5/03—Data sheet changed from Rev. 0 to Rev. A. Changes to Features..........................................................................1
Changes to Specifications................................................................5
Changes to Figure 1..........................................................................4
Changes to Absolute Maximum Ratings.......................................7
Changes to Figures 2, 8, 15–16..................................................8–10
Changes to Figure 17......................................................................11
Changes to Programmable Supply Fault Detectors section......11
Changes to Figure 18......................................................................12
Changes to Figure 19......................................................................13
Change to Table 9...........................................................................15
Change to Table 14.........................................................................16
Change to Table 19.........................................................................17
Changes to Programmable Driver Outputs section...................33
Change to Table 40.........................................................................34
Changes to Figure 25–26...............................................................43
Changes to Figure 37......................................................................47
Changes to Table 58........................................................................49
Changes to Ordering Guide section.............................................50
GENERAL DESCRIPTION (continued from Page 1)
All of the inputs and outputs described previously are
controlled by the programmable logic block array (PLBA). This
is the logic core of the ADM1060. It is comprised of nine
macrocells, one for each PDO. These macrocells are essentially
just wide AND gates. Any/all of the inputs can be used as an
input to these macrocells. The output of a macrocell can also be
used as an input to any macrocell other than itself (an input to
itself would result in a nonterminating loop). The PLBA outputs
control the PDOs of the ADM1060 via delay blocks, where a
delay of 0 ms to 500 ms can be programmed on the rising
and/or the falling edge of the data. This results in a very flexible
sequencing ability. Thus, for instance, PDO1 can be
programmed so that it will not assert until the VP2, VP3, and
VP4 supplies are in tolerance; VB1 and VH have been in
tolerance for 200 ms; and PDO7 has already been asserted. A
simple sequencing operation would be to daisy-chain each PLB
output into the input of the next PLB such that PDO9 does not
assert until PDO8 asserts, which in turn does not assert until
PDO7 asserts, and so on.
All of the functional capability described here is programmable
through the industry-standard 2-wire bus (SMBus) provided.
Device settings can be written to EEPROM memory for auto-
matic programming of the device on power-up. The EEPROM
is organized in 512 bytes, half of which are used to program all
of the functions on the ADM1060. The other 256 bytes of
EEPROM are for general-purpose system use such as date codes
and system ID. Read/write access to this is also via the 2-wire
interface. In addition, each output state can be directly over-
driven from the serial interface, allowing a further level of
control, as in a system controlled soft power-down.
VP1
VP2
VP3
VP4
VB1
VB2
GPI1
GPI2
GPI3
GPI4
WDI
GND
DDCAP
PDO9
PDO8
PDO7
PDO6
PDO5
PDO4
PDO3
PDO2
PDO1SPECIFICATIONS (VH = 4.75 V to 14.4 V, VPn = 3.0 V to 6.0 V,1 TA = −40°C to +85°C, unless otherwise noted.)
Table 1. NOTES At least one VPn must be ≥3.0 V if used as supply. VH must be ≥4.5 V if used as supply.
2Specification is not production tested, but is supported by characterization data at initial product release.
31% threshold accuracy is only achievable on parts preprogrammed by Analog Devices. Contact
[email protected] for further details. Logic inputs will accept input high voltages up to 5.5 V even when the device is operating at supply voltages below 5 V.
5Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 method A117, and measured at −40°C, +25°C, and +85°C. For programming and erasing of EEPROM, a minimum VDD = 3.0 V is required 0°C to +85°C and a minimum VDD = 4.5 V is required −40°C to 0°C.
7Retention lifetime equivalent at junction temperature (TJ) = 55°C as per JEDEC Std. 22 method A117. Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge and VIH = 2.0 V for a rising edge.
ABSOLUTE MAXIMUM RATINGS
Table 2. Absolute Maximum Ratings Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rat-
ing only; functional operation of the device at these or any
other conditions above those indicated in the operational sec-
tion of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL CHARACTERISTICS 28-Lead TSSOP Package:
θJA = 98°C/W
TYPICAL PERFORMANCE CHARACTERISTICS
VVH,VVP1 (V)
DDCAP
(VFigure 2. VVDDCAP vs. VVH and VVP1
VVP1 (V)
IDD
(mA)
0.5Figure 3. IDD vs. VVP1 (Supply)
VVP1 (V)
VP1
100013245Figure 4. IVP1 vs. VVP1 (Not Supply)
VVH (V)
IDD
(mA)
3.5Figure 5. IDD vs. VVH
VVH (V)
IVH
100Figure 6. IVH vs. VVH (Not Supply)
VVB1 (V)
–400Figure 7. IVB1 vs. VVB1
TEMPERATURE (°C)
RCE
NT DE
IATION
1.5%
1.0%
0.5%
0.0%
–0.5%
–1.0%
–1.5%
–40–25–1052035506580Figure 8. Percent Deviation in VTHRESH vs. Temperature
TEMPERATURE (°C)
(V
10.0–40–25–1052035655080Figure 9. VPDO (FET Drive Mode) vs. Temperature
ILOAD (mA)
(V
0.500.51.01.52Figure 10. VPDO (Strong Pull-Up to VP1) vs. Load Current
ILOAD (µA)
(V
0.5510152025304035Figure 11. VPDO (Weak Pull-Up to VP1) vs. Load Current
ILOAD (mA)
(V
0.25Figure 12. VPDO (Strong Pull-Down) vs. Load Current
ILOAD (µA)
(V1.2
0.2Figure 13. VPDO (Weak Pull-Down) vs. Load Current
TEMPERATURE (°C)
CILLATOR FRE
NCY
(k
Hz)
–40–25–1052035506580Figure 14. Oscillator Frequency vs. Temperature
ILOAD (µA)
CCP
(V
4.50100200300500400Figure 15. VCCP vs. Load Current
TEMPERATURE (°C)
GPI THRESHOLD (
0.5–40–25–1052035506580Figure 16. GPI Threshold vs. Temperature
INPUTS
POWERING THE ADM1060 The ADM1060 is powered from the highest voltage input on
either the Positive Only supply inputs (VPn) or the High Volt-
age supply input (VH). The same pins are used for supply fault
detection (discussed below). A VDD arbitrator on the device
chooses which supply to use. The arbitrator can be considered
as diode OR’ing the positive supplies together (as shown in
Figure 17).The diodes are supplemented with switches in a syn-
chronous rectifier manner to minimize voltage loss. This loss
can be reduced to ~0.2 V, resulting in the ability to power the
ADM1060 from a supply as low as 3.0 V. Note that the supply on
the VBn pins cannot be used to power the device, even if the
input on these pins is positive. Also, the minimum supply of
3.0 V must appear on one of the VPn pins in order to correctly
power up the ADM1060. A supply of no less than 4.5 V can be
used on VH. This is because there is no synchronous rectifier
circuit on the VH pin, resulting in a voltage drop of ~1.5 V
across the diode of the VDD arbitrator.
An external capacitor to GND is required to decouple the
on-chip supply from noise. This capacitor should be connected
to the VDDCAP pin, as shown in Figure 17. The capacitor has
another use during “brown outs” (momentary loss of power).
Under these conditions, where the input supply, VPn, dips
transiently below VDD, the synchronous rectifier switch
immediately turns off so that it does not pull VDD down. The
VDD capacitor can then act as a reservoir to keep the chip active
until the next highest supply takes over the powering of the
device. A 1 µF capacitor is recommended for this function. A
minimum capacitor value of 0.1 µF is required.
Note that in the case where there are two or more supplies
within 100 mV of each other, the supply that takes control of
VDD first will keep control. For example, if VP1 is connected to a
3.3 V supply, VDD will power up to approximately 3.1 V through
VP1. If VP2 is then connected to another 3.3 V supply, VP1 will
still power the device, unless VP2 goes 100 mV higher than
VP1.
A second capacitor is required on the VCCP pin of the
ADM1060. This capacitor is the reservoir capacitor for the
central charge pump. Again, a 1 µF capacitor is recommended
for this function. A minimum capacitor value of 0.1 µF is
required.
VP1
VP2
VP3
VP4
VDDCAP PIN
OFF-CHIP
DECOUPLINGCAPACITOR
ON-CHIP SUPPLY Figure 17. VDD Arbitrator Operation
PROGRAMMABLE SUPPLY FAULT DETECTORS
(SFDs) The ADM1060 has seven programmable supply fault detectors
(SFDs): one high voltage detector (+2 V to +14.4 V), two bipolar
detectors (+1 V to +6 V, −2 V to –6 V) and four positive only
voltage detectors (+0.6 V to +6 V). Inputs are applied to these
detectors via the VH (high voltage supply input), VBn (bipolar
supply input), and VPn (positive only input) pins, respectively.
The SFDs detect a fault condition on any of these input supplies.
A fault is defined as undervoltage (where the supply drops
below a preprogrammed level), overvoltage (where the supply
rises above a preprogrammed level), or out-of-window (where
the supply deviates outside either the programmed overvoltage
or undervoltage threshold). Only one fault type can be selected
at a time.
An undervoltage (UV) fault is detected by comparing the input
supply to a programmed reference (the undervoltage threshold).
If the input voltage drops below the undervoltage threshold, the
output of the comparator goes high, asserting a fault. The
undervoltage threshold is programmed using an 8-bit DAC. On
a given range, the UV threshold can be set with a resolution of
Step Size = Threshold Range/255
An overvoltage (OV) fault is detected in exactly the same way,
using a second comparator and DAC to program the reference.
All thresholds are programmed using 8-bit registers, one regis-
ter each for the seven UV thresholds and one each for the seven
OV thresholds. The UV or OV threshold programmed by the
user is given by VVV+×=255
where
VT is the desired threshold voltage (UV or OV)
VR is the threshold voltage range
N is the decimal value of the 8 bit code
VB is the bottom of threshold range
The code for a given threshold is therefore given by
N = 255 × (VT – VB)/VR
For example, if the user wishes to set a 5 V OV threshold on
VP1, the code to be programmed in the PS1OVTH register
(discussed later) would be
N = 255 × (5 – 2.005)/3.997
Thus, N = 191 (1011 1111 binary, or 0xBF)
The available threshold ranges and their resolutions are shown
in Table 3. Note that the low end of the detection range is fixed
at 33.33% of the top of the range. Note also that for a given SFD,
the ranges overlap; for example, VH goes from 2 V to 6 V and
then from 4.8 V to 14.4 V. This is to provide better threshold
setting resolution as supplies decrease in value.
Table 3. Input Threshold Ranges and Resolution Figure 18 illustrates the function of the programmable SFD (for
the case of a positive supply).
COMPARATOR
COMPARATOR
FAULT TYPE
SELECT
GLITCHSETTING UV
AND OVTHRESHOLDS
FAULTOUTPUT
VPnFigure 18. Positive Programmable Supply Fault Detector
SFD COMPARATOR HYSTERESIS The OV and UV comparators shown in Figure 18 are always
looking at VPn via a potential divider. In order to avoid
chattering (multiple transitions when the input is very close to
the set threshold level), these comparators have digitally
programmable hysteresis. The UV and OV hysteresis can be
programmed in two registers that are similar but separate to the
UV or OV threshold registers. Only the five LSBs of these
registers can be set. The hysteresis is added after the supply
voltage goes out of tolerance. Thus, the user can determine how
much above the UV threshold the input must rise again before a
UV fault is deasserted. Similarly, the user can determine how
much below the OV threshold the input must fall again before
an OV fault is deasserted. The hysteresis figure is given by
VH = VR × NTHRESH/255
where
VH is the desired hysteresis voltage
NTHRESH is the decimal value of the 5-bit hysteresis code
Therefore, if the low range threshold detector was selected, the
max hysteresis is defined as
(3 V – 1 V) × 31/255 = 242 mV, where (25 – 1 = 31)
The hysteresis programming resolution is the same as the
threshold detect ranges—that is, 37.5 mV on the high range,
15.6 mV on the midrange, 7.8 mV on the low range, and 4.7 mV
on the ultralow range.
BIPOLAR SFDs The two bipolar SFDs also allow the detection of faults on nega-
tive supplies. A polarity bit in the setup register for this SFD
(Bit 7 in Register BSnSEL—see register map overleaf) deter-
mines if a positive or negative input should be applied to VBn.
Only one range (−6 V to −2 V) is available when the SFDs are in
negative mode. Note that the bipolar SFDs cannot be used to
SFD FAULT TYPES Three types of faults can be asserted by the SFD: an OV fault, a
UV fault, and an out-of-window fault (where the UV and OV
faults are OR’ed together). The type of fault required is
programmed using the fault type select bits (Bits 0, 1 in Register
_SnSEL). If an application requires separate fault conditions to
be detected on one supply (e.g., assert PDO1 if a UV fault
occurs on a 3.3 V supply, assert PDO9 if an OV fault occurs on
the same 3.3 V supply), that supply will need to be applied to
more than one input pin.
GLITCH FILTERING ON THE SFDs The final stage of the SFD is a glitch filter. This block provides
time domain filtering on the output of the SFD. This allows the
user to remove any spurious transitions (such as supply bounce
at turn-on). This deglitching function is in addition to the
programmable hysteresis of the SFDs. The glitch filter timeout
is programmable up to 100 µs. If a pulse shorter than the
programmed timeout appears on the input, this pulse is masked
and the signal change will appear on the output. If an input
pulse longer than the programmed timeout appears on the
input, this pulse will appear on the output. The output will be
delayed (with respect to the input) by the length of the
programmed timeout.
Figure 19 shows the implementation of glitch filtering.
GLITCH FILTER INPUT
PROGRAMMED TIMEOUTPROGRAMMED TIMEOUT
tGFtGFt0t0Figure 19. Glitch Filtering on the SFDs
PROGRAMMING THE SFDs ON THE SMBus The details of using the SMBus are described later, but the regis-
ter names associated with the supply fault detector blocks, the
bit map of those registers, and the function of each of the bits is
described in the following tables. The tables show how to set up
UV threshold, UV hysteresis, OV threshold, OV hysteresis,
glitch filtering, and fault type for each of the SFDs on the
ADM1060.
SFD REGISTER NAMES
Table 4. List of Registers for the Supply Fault Detectors
SFD Register Bit Maps
BIPOLAR SUPPLY FAIL DETECT (BSn SFD) REGISTERS
Table 5. Register 0xA0, 0xA8 BSnOVTH
(Power-On Default 0xFF)
Table 6. Register 0xA1, 0xA9 BSnOVHYST
(Power-On Default 0x00)
Table 7. Register 0xA2, 0xAA BSnUVTH
(Power-On Default 0x00)
Table 8. Register 0xA3, 0xAB BSnUVHYST
(Power-On Default 0x00)
Table 9. Register 0xA4, 0xAC BSnSEL (Power-On Default 0x00) HIGH VOLTAGE SUPPLY FAULT DETECT (HV SFD) REGISTERS
Table 10. Register 0xB0 HSOVTH
(Power-On Default 0xFF)
Table 11. Register 0xB1 HSOVHYST
(Power-On Default 0x00)
Table 12. Register 0xB2 HSUVTH
(Power-On Default 0x00)
Table 13. Register 0xB3 HSUVHYST
(Power-On Default 0x00)
Table 14. Register 0xB4 HSSEL (Power-On Default 0x00) POSITIVE VOLTAGE SUPPLY FAULT DETECT (PSn SFD) REGISTERS
Table 15. Register 0xB8, 0xC0, 0xC8, 0xD0 PSnOVTH
(Power-On Default 0xFF)
Table 16. Register 0xB9, 0xC1, 0xC9, 0xD1 PSnOVHYST
(Power-On Default 0x00)
Table 17. Register 0xBA, 0xC2, 0xCA, 0xD2 PSnUVTH
(Power-On Default 0x00)
Table 18. Register 0xBB, 0xC3, 0xCB, 0xD3 PSnUVHYST
(Power-On Default 0x00)
Table 19. Register 0xBC, 0xC4, 0xCC, 0xD4 PSnSEL (Power-On Default 0x00) WATCHDOG FAULT DETECTOR The ADM1060 has a watchdog fault detector. This can be used
to monitor a processor clock to ensure normal operation. The
detector monitors the WDI pin, expecting a low-to-high or
high-to-low transition within a preprogrammed period. The
watchdog timeout period can be programmed from 200 ms to a
maximum of 12.8 sec.
If no transition is detected, two signals are asserted. One is a
latched high signal, indicating a fault has occurred. The other
signal is a low-high-low pulse that can be used as a RESET sig-
nal for a processor core. The width of this pulse can be
programmed from 10 µs to a maximum of 10 ms. These two
watchdog signals can be selected as inputs to each of the PLBs
(see the PLBA section). They can also be inverted, if required;
for example, if a high-low-high pulse were required by a proces-
sor to reset. Thus, a fault on the watchdog can be used to
generate a pulsed or latched output on any or all of the nine
PDOs.
The latched signal can be cleared low by reading LATF1, then
LATF2 across the SMBus interface (see the Fault Registers sec-
tion). The RAM register list and the bit map for the watchdog
fault detector are shown below.
Table 20. Watchdog Fault Detector Registers
Table 21. WDCFG Register 0x9C (Power-On Default 0x00) GENERAL-PURPOSE INPUTS (GPIs) The ADM1060 has four general-purpose logic inputs (GPIs).
These are TTL/CMOS logic level compatible. Standard logic
signals can be applied to the pins: RESET from reset generators,
PWRGOOD signals, fault flags, manual resets, and so on. These
signals can be gated with the other inputs supervised by the
ADM1060 and used to control the status of the PDOs. The
inputs can be simply buffered, or a logic transition can be
detected and a pulse output generated. The width of this pulse is
programmable from 10 µs to a maximum of 10 ms. The
configuration of the GPIs is shown in the register and bit maps
below.
The GPIs also feature a glitch filter similar to that provided on
the SFDs. This enables the user to ignore spurious transitions
on the GPIs. For example, the glitch filter can be used to
debounce a manual reset switch. The length of the glitch filter
can also be programmed.
LOGIC STATE OF THE GPIs AND OTHER LOGIC
INPUTS Each of the GPIs can have a weak (10 µA) pull-down current
source. The current sources can be connected to the inputs by
progamming the relevant bit in the PDEN register. This enables
the user to control the condition of these inputs, pulling them to
GND even when they are unused or left floating.
Note that the same pull-down function is provided for the
SMBus address pins, A0 and A1, and for the WDI pin. A register
is used to program which of the inputs is connected to the cur-
rent sources.
Table 22. General-Purpose Inputs (GPIn) Registers
Table 23. GPInCFG Registers Bit Map (Power-On Default 0x00)
Table 24. Registers for the Pull-Down Current Sources on Logic Inputs
Table 25. PDEN Register 0x91 Bit Map (Power-On Default 0x00) PROGRAMMING
PROGRAMMABLE LOGIC BLOCK ARRAY The ADM1060 contains a programmable logic block array
(PLBA). This block is the logical core of the device. The PLBA
(and the PDBs—see the Programmable Delay Block section)
provides the sequencing function of the ADM1060. The asser-
tion of the nine programmable driver outputs (PDO) is
controlled by the PLBA. The PLBA is comprised of nine macro-
cells, one per PDO channel. The main components of the
macrocells are two wide AND-OR gates, as shown in Figure 20.
Each AND gate represents a function (A or B) that can be used
independently to control the assertion of the PDO pin. There
are 21 inputs to each of these AND gates: The logic outputs of all seven supply fault detectors The four GPI logic inputs The watchdog fault detector (latched and pulsed) The delayed output of any of the other macrocells (the
output of a macrocell cannot be an input to itself, since this
would result in a nonterminating loop).
All 21 inputs are hardwired to both function A and function B
AND gates. The user can then select which of these inputs con-
trols the output. This is done using two control signals, IMK (a
masking bit, setting it ignores the relevant input) and POL (a
polarity bit, setting it inverts the input before it is applied to the
AND gate). The effect of setting these bits can be seen in
Figure 20. The inverting gate shown is an XOR gate, resulting in
the following truth table:
Table 26. Truth Table for PLB Input Inversion The last two entries in the truth table show that with the
INVERT (POL) bit set, the XOR output is always the inverse of
the input.
Similarly, the ignore gate shown is an OR gate, resulting in the
following truth table:
Table 27. Truth Table for PLB Input Masking It can be seen here that once the IMK bit is set, the OR output is
always 1, regardless of the input, thus ignoring it. Figure 21 is a
detailed diagram of the 21 inputs and the registers required to
program them. Those shown are just for function A of PLB1,
but function B and all of the functions in the other eight PLBs
are programmed exactly the same way. An enable register allows
the user to use function A, function B, or both. The output of
functions A and/or B is input to a programmable delay block
(PDB) where a delay can be programmed on both the rising and
falling edges of an input (see the Programmable Delay Block
section). The output of this PDB block can be progammed to
invert before any of the PDO pins is asserted.
INVERTOUTPUT
PLBOUT
ENABLEFUNCTION A
ENABLE
FUNCTION B
2 WIDE AND GATES
(21 INPUTS)
SIGNAL INPUTS
POL (INVERT)
IMK (IGNORE)Figure 20. Simplified Programmable Logic Block Macrocell Schematic
LOGIC
IGNORE
INVERT
IGNORE
INVERT
INVERT
INVERT
IGNORE
INVERT
INVERT
IGNORE
INVERT
IGNORE
INVERT
IGNORE
INVERT
IGNORE
ENABLE
FUNCTION A
RISE TIME
FALL TIMEPLBOUT
NOT CONNECTEDFUNCTION B
The control bits for these macrocells are stored locally in latches
that are loaded at power-up. These latches can also be updated
via the serial interface. The registers containing the macrocell
control bits and the function of each bit are defined in the tables
that follow.
Figure 21 highlights all 21 inputs to a given function and the
register/bits that need to be set in order to condition the 21
inputs correctly. The diagram only shows function A of Pro-
grammable Logic Block 1 (PLB1), but all functions are
programmed in the same way.
For example, if the user wishes to assert PLBOUT 200 ms after
all of the supplies are in spec (PLBOUT may be used to drive
the enable pin of an LDO), the supply fault detectors VBn, VH,
and VPn are required to control the function. The function is
programmed as follows:
1. The IGNORE bit of all the other inputs (GPIs, PDBs, WDI)
in the relevant P1xxxIMK registers is set to 1. Thus, regard-
less of its status, the input to the function AND gate for
these inputs will be 1.
2. Since the SFDs assert a 1 under a fault condition and a 0
when the supplies are in tolerance, the SFD outputs need to
be inverted before being applied to the function. Thus the
relevant bit in the P1SFDPOL register is set (see Table 38).
3. The function is enabled (Bit 1 of Register P1EN—see
Table 36).
4. A rise time of 200 ms is programmed (register
P1PDBTIM—see register map for details).
Table 28. Programmable Logic Block Array (PLBA) Registers
