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ADM1041A
Secondary-Side Controller with Current Share and Housekeeping
Secondary-Side Controller with
Current Share and Housekeeping
Rev. 0
FEATURES
Digital calibration via internal EEPROM
Supports SSI specification
Comprehensive fault detection
Reduced component count on secondary side
Standalone or microcontroller control
SECONDARY-SIDE FEATURES
Generates error signal for primary-side PWM
Output voltage adjustment and margining
Current sharing
Current-limit adjustment
OrFET control
Programmable soft-start slew rate
Standalone or microcontroller operation
Differential load voltage sense
AC mains undervoltage detection (ac sense)
Overvoltage protection
INTERFACE AND INTERNAL FEATURES
SMBus interface (I2C-compatible)
Voltage-error amplifier
Differential current sense
Sense resistor or current transformer option
Overvoltage protection
Undervoltage protection
Overcurrent protection
Overtemperature protection
Start-up undervoltage blanking
Programmable digital debounce and delays
352-byte EEPROM available for field data
160-byte EEPROM for calibration
Ground continuity monitoring
APPLICATIONS
Network servers
Web servers
Power supply control
VDD
ISOLATION BARRIERFigure 1. Typical Application Circuit
TABLE OF CONTENTS General Description.........................................................................3
Sample Application Circuit Description...................................3
Specifications.....................................................................................6
Absolute Maximum Ratings..........................................................13
Thermal Characteristics............................................................13
ESD Caution................................................................................13
Pin Configuration and Function Descriptions...........................14
Terminology................................................................................16
Theory of Operation......................................................................18
Power Management....................................................................18
Gain Trimming and Configuration.........................................18
Differential Remote Sense Amplifier.......................................19
Set Load Voltage.........................................................................19
Load Overvoltage (OV).............................................................19
Local Voltage Sense....................................................................19
Local Overvoltage Protection (OVP)......................................19
Local Undervoltage Protection (UVP)....................................19
False UV Clamp..........................................................................19
Voltage Error Amplifier.............................................................20
Main Voltage Reference.............................................................20
Current-Sense Amplifier...........................................................20
Current Sensing..........................................................................21
Current-Transformer Input......................................................21
Current-Sense Calibration........................................................21
Current-Limit Error Amplifier.................................................21
Overcurrent Protection.............................................................22
Current Share..............................................................................22
Current-Share Offset..................................................................22
ISHARE Drive Amplifier................................................................22
Differential Sense Amplifier.....................................................22
ISHARE Error Amplifier.................................................................22
ISHARE Clamp................................................................................22
SHARE_OK Detector................................................................23
Pulse/ACSENSE2.............................................................................24
Pulse.............................................................................................24
ACSENSE..........................................................................................24
OrFET Gate Drive......................................................................25
Oscillator and Timing Generators...............................................27
Logic I/O and Monitor Pins......................................................27
SMBus Serial Port.......................................................................30
Microprocessor Support............................................................30
Broadcasting................................................................................30
SMBus Serial Interface...............................................................30
General SMBus Timing.............................................................31
SMBus Protocols for RAM and EEPROM..............................33
SMBus Read Operations...........................................................35
SMBus Alert Response Address (ARA)..................................36
Support for SMBus 1.1...............................................................36
Layout Considerations...............................................................36
Power-Up Auto-Configuration................................................36
Extended SMBus Addressing....................................................37
Backdoor Access.........................................................................37
Register Listing...............................................................................38
Detailed Register Descriptions.....................................................39
Manufacturing Data...................................................................48
Microprocessor Support................................................................49
Test Name Table..............................................................................51
Outline Dimensions.......................................................................53
Ordering Guide..........................................................................53
GENERAL DESCRIPTIONThe ADM1041A is a secondary-side and management IC spec-
ifically designed to minimize external component counts and to
eliminate the need for manual calibration or adjustment on the
secondary-side controller. The principle application of this IC is
to provide voltage control, current share, and housekeeping
functions for single output in N+1 server power supplies.
The ADM1041A is manufactured with a 5 V CMOS process
and combines digital and analog circuitry. An internal
EEPROM provides added flexibility for trimming timing and
voltage and selecting various functions. Programming is done
via an SMBus serial port that also allows communication
capability with a microprocessor or microcontroller.
The usual configuration using this IC is on a one-per-output
voltage rail. Output from the IC can be wire-OR’ed together or
bused in parallel and read by a microprocessor. A key feature on
this IC is support for an OrFET circuit when higher efficiency
or power density is required.
SAMPLE APPLICATION CIRCUIT DESCRIPTION Figure 1 shows a sample application circuit using the
ADM1041A. The primary side is not detailed and the focus is
on the secondary side of the power supply.
The ADM1041A controls the output voltage from the power
supply to the designed programmed value. This programmed
value is determined during power supply design and is digitally
adjusted via the serial interface. Digital adjustment of the
current sense and current limit is also calibrated via the serial
interface, as are all of the internal timing specifications.
The control loop consists of a number of elements, notably the
inputs to the loop and the output of the loop. The ADM1041A
takes the loop inputs and determines what, if any, adjustments
are needed to maintain a stable output. To maintain a stable
loop, the ADM1041A uses three main inputs: Remote voltage sense Load current sense Current sharing information
In this example, a resistor divider senses the output current as a
voltage drop across a sense resistor (RS) and feeds a portion
into the ADM1041A. Remote local voltage sense is monitored
via VS+ and VS− pins. Finally, current sharing information is fed
back via the share bus. These three elements are summed
together to generate a control signal (VCMP), which closes the
loop via an optocoupler to the primary side PWM controller.
Another key feature of the ADM1041A is its control of an
OrFET. The OrFET causes lower power dissipation across the
OR'ing diode. The main function of the OrFET is to disconnect
the power supply from the load in the event of a fault occurring
during steady state operation, for example, if a filter capacitor or
rectifier fails and causes a short. This eliminates the risk of
bringing down the load voltage that is supplied by the redun-
dant configuration of other power supplies. In the case of a
short, a reverse voltage is generated across the OrFET. This
reverse voltage is detected by the ADM1041A and the OrFET is
shut down via the FG pin. This intervention prevents any
interruption on the power supply bus. The ADM1041A can
then be interrogated via the serial interface to determine why
the power supply has shut down.
This application circuit also demonstrates how temperature can
be monitored within a power supply. A thermistor is connected
between the VDD and MON2 pins. The thermistor’s voltage
varies with temperature. The MON2 input can be programmed
to trip a flag at a voltage corresponding to an overheating power
supply. The resulting action may be to turn on an additional
cooling fan to help regulate the temperature within the power
supply.
Figure 2. Application Block Diagram
Differences Between the ADM1041A and ADM1041
For all new designs, it is recommended to use the ADM1041A.
The parts differ as follows:
• The ADM1041 allows the internal VREF voltage reference to
be accessed at Pin 18. This is not accessible using the
ADM1041A.
• The ADM1041A has longer VDDOK debounce and VDDOV
debounce than the ADM1041. The GND_OK Disable bit (Register 11h) does not disable
when using the ADM1041. It does disable when using the
ADM1041A.
URATON
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