ADM1034 ,Thermal Monitor and Fan Speed ControllerAPPLICATIONS Programmable fault queue SMBusALERT output Desktop and notebook PCs Embedded systems F ..
ADM1034ARQ ,Thermal Monitor and Fan Speed ControllerFEATURES Linear and discrete options for look-up table 1 local and 2 remote temperature channels FA ..
ADM1034ARQ-REEL ,Thermal Monitor and Fan Speed ControllerCharacteristics 8 Conversion Rate Register .... 23 Functional Description ... 10 I/O Timer and Li ..
ADM1034ARQZ ,Thermal Monitor and Fan Speed ControllerSpecifications subject to change without notice. No license is granted by implication www.analog.c ..
ADM1034ARQZ ,Thermal Monitor and Fan Speed ControllerCharacteristics ........ 6 Interrupt Masking Register. 22 ESD Caution. 6 FAN_FAULT Output .. 23 Pin ..
ADM1034ARQZ-REEL ,Thermal Monitor and Fan Speed ControllerSpecifications.... 4 ALERT Interrupt Behavior . 21 Absolute Maximum Ratings...... 6 Handling SMBUSA ..
AH1802-FJG-7-01 , MICROPOWER, ULTRA-SENSITIVE OMNIPOLAR
AH1802-SNG-7 , MICROPOWER, ULTRA-SENSITIVE OMNIPOLAR
AH1803-SNG-7 , MICROPOWER, ULTRA-SENSITIVE HALL EFFECT
AH183-WLA , LOW POWER HALL EFFECT SWITCH
AH183-WLA , LOW POWER HALL EFFECT SWITCH
AH1883-ZG-7 , MICROPOWER, ULTRA-SENSITIVE HALL EFFECT SWITCH
ADM1034-ADM1034ARQ-ADM1034ARQ-REEL-ADM1034ARQZ-ADM1034ARQZ-REEL
Thermal Monitor and Fan Speed Controller
Thermal Monitor and
Fan Speed (RPM) Controller
Rev. 0
FEATURES
1 local and 2 remote temperature channels
±1°C accuracy on local and remote channels
Automatic remote temperature channels, up to 1 kΩ
Fast (up to 64 measurements per second)
SMBus 2.0, 1.1, and 1.0 compliant
SMBus address input/LOCATION input to UDID
Programmable over-/undertemperature limits
Programmable fault queue
SMBusALERT output
Fail-safe overtemperature comparator output
Fan speed (RPM) controller
Look-up table for temperature-to-fan-speed control
Linear and discrete options for look-up table
FAN_FAULToutput
THERM input, used to time PROCHOT assertions
REF input, used as reference for THERM (PROCHOT)
3 V to 5.5 V supply
Small 16-lead QSOP package
APPLICATIONS
Desktop and notebook PCs
Embedded systems
Telecommunications equipment
LCD projectors
FUNCTIONAL BLOCK DIAGRAM
TACH1
ALERT
THERM
SDA
SCL
GND
VCC
DRIVE1
TACH2
DRIVE2
LOCATION
D2–
D2+
D1–
D1+
FAN_FAULT
REFFigure 1.
TABLE OF CONTENTS Specifications.....................................................................................4
Absolute Maximum Ratings............................................................6
Thermal Characteristics..............................................................6
ESD Caution..................................................................................6
Pin Configuration and Function Descriptions.............................7
Typical Performance Characteristics.............................................8
Functional Description..................................................................10
Internal Registers........................................................................10
Serial Bus Interface.....................................................................10
Location Input.............................................................................10
SMBus 2.0 ARP-Capable Mode................................................10
SMBus 2.0 Fixed-and-Discoverable Mode..............................12
SMBus 2.0 Read and Write Operations...................................12
Register Addresses for Single/Block Byte Modes...................14
Write Operations........................................................................14
Read Operations.........................................................................15
SMBus Timeout..........................................................................15
Packet Error Checking (PEC)...................................................15
Alert Response Address (ARA)................................................15
Temperature Measurement System..............................................16
Internal Temperature Measurement........................................16
Remote Temperature Measurement.........................................16
Additional Functions.................................................................18
Layout Considerations...................................................................19
Limits, Status Registers, and Interrupts.......................................20
8-Bit Limits..................................................................................20
Out-of-Limit Comparisons.......................................................20
Analog Monitoring Cycle Time................................................20
Status Registers...........................................................................20
ALERT Interrupt Behavior.......................................................21
Handling SMBUSALERT Interrupts.......................................22
Interrupt Masking Register.......................................................22
FAN_FAULT Output.................................................................23
Fault Queue.................................................................................23
Conversion Rate Register..........................................................23
THERM I/O Timer and Limits................................................23
THERM % Limit Register.........................................................24
Fan Drive Signal.........................................................................25
Synchronous Speed Control.....................................................25
Fan Inputs....................................................................................26
Fan Speed Measurement...........................................................26
Fan Speed Measurement Registers...........................................27
Reading Fan Speed.....................................................................27
Calculating Fan Speed...............................................................27
Alarm Speed................................................................................27
Look-Up Table: Modes of Operation.......................................28
Setting Up the Size of the Look-Up Table...............................29
Setting Up the Look-Up Table in Linear Mode......................29
Setting Which Temperature Channel Controls a Fan...........29
Look-Up Table Hysteresis.........................................................29
Programming the THERM Limit for Each Temperature
Channel........................................................................................30
XOR Tree Test Mode..................................................................30
Lock Bit........................................................................................30
SW Reset......................................................................................30
Outline Dimensions.......................................................................40
Ordering Guide..........................................................................40
REVISION HISTORY
8/04—Revision 0: Initial Version
GENERAL DESCRIPTION The ADM1034 is a dual-channel remote- and local-temperature
sensor and fan controller. The remote channels monitor the
temperature of two remote thermal diodes, which may be
discrete 2N3904/6s or may be located on a microprocessor die.
The device also monitors its own ambient temperature.
The ADM1034 can monitor and control the speed of two
cooling fans. The user can program a target fan speed, or else
use the look-up table to input a temperature-to-fan-speed
profile. The look-up table can be configured to run the fans at
discrete speeds (discrete mode) or to ramp the fan speed with
temperature (linear mode).
The ADM1034 communicates over a 2-wire SMBus 2.0
interface. An 8-level LOCATION input allows the user to
choose between SMBus 1.1 and SMBus 2.0. An ALERT output
indicates error conditions. The THERM I/O signals over-
temperature as an output and times THERM assertions as
an input. Pin 8 can be configured as a reference for the
THERM (PROCHOT) input.
SPECIFICATIONS TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted.1
Table 1. Typicals are at TA = 25°C and represent most likely parametric norm. Standby current typ is measured with VCC = 3.3 V. Timing specifications are tested at logic levels of
VIL = 0.8 V for a falling edge and VIH = 2.1 V for a rising edge. Operation at 5.5 V is guaranteed by design, not production tested.
3 Recommend use of 100 kΩ pull-up resistors for all open-drain outputs from the ADM1034. Guaranteed by design, not production tested.
5 SMBus timeout disabled by default. See thesection for more information. SMBUS
tRtF
SCL04918-0-002
Figure 2. Serial Bus Timing Diagram
ABSOLUTE MAXIMUM RATINGS
Table 2. During power-up the voltage on FAN_FAULT should not be higher than VCC.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to Absolute
Maximum Rating conditions for extended periods may affect
device reliability.
THERMAL CHARACTERISTICS 16-Lead QSOP Package:
θJA = 150°C/W, θJC = 39°C/W
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
TACH1
DRIVE2
TACH2
THERM
VCC
GND
DRIVE1
SDA
ALERT
LOCATION
D1+
FAN_FAULT/REFD1–
D2–
D2+
SCL
TOP VIEW
(Not to Scale)
ADM103404918-0-003
Figure 3. Pin Configuration
Table 3. Pin Function Descriptions TYPICAL PERFORMANCE CHARACTERISTICS
LEAKAGE RESISTANCE (MΩ)
MPERAT
URE ERRO
R (°C)
–80102030405060708090100Figure 4. Temperature Error vs. PCB Track Resistance DXP to GND and VCC
CAPACITANCE (nF)
MPERAT
URE ERRO
R (°C)
–80042681004918-0-005
Figure 5. Remote Temperature Error vs. D+, D− Capacitance
SERIES RESISTANCE IN D+/D– LINES (kΩ)
RATURE
RROR (
–10123465Figure 6. Remote Temperature Error vs. Series Resistance on D+ and D−
MPERAT
URE ERRO
R (°C)
–1001M2M3M4M65M04918-0-007
MFigure 7. Remote Temperature Error vs. Power Supply Noise Frequency
NOISE FREQUENCY (Hz)
RATURE
RROR (01M2M4M3M5M6MFigure 8. Remote Temperature Error vs. Common-Mode Noise Frequency
Coupled on D+ and D−
NOISE FREQUENCY
MPERAT
URE ERRO
R (°C)
0.501M3M2M5M4M6MFigure 9. Remote Temperature Error vs. Differential Mode Noise Frequency
Coupled on D+ and D−
TEMPERATURE (°C)
ERRO
R (–60–40–20080100120406020140Figure 10. Remote Temperature Error vs. Actual Diode Temperature
TEMPERATURE (°C)
ERRO
R (°C)
–50010050150Figure 11. Local Temperature Error vs. Actual Temperature
FSCL (kHz)
ICC
3601101000100Figure 12. Standby Supply Current vs. SCLK Frequency
SUPPLY VOLTAGE (V)
ANDBY
CURRE
0.102453104918-0-013
Figure 13. Standby Supply Current vs. Supply Voltage
CONVERSION RATE (Hz)
ICC
2000.010.1110010Figure 14. Supply Current vs. Conversion Rate
TEMPERATURE (°C)
CURRE
1.25–60–40–20010040608020Figure 15. Supply Current vs. ADM1034 Temperature
FUNCTIONAL DESCRIPTION The ADM1034 is a local- and remote-temperature monitor and
fan controller for use in a variety of applications, including
microprocessor-based systems. The device accurately monitors
remote and ambient temperature and uses that information to
quietly control the speed of a cooling fan. Whenever one of the
fans stalls, the device asserts a FAN_FAULT output.
The ADM1034 features a THERM I/O. As an input, this
measures assertions on the THERM pin. As an output, it asserts
a low signal to indicate when the measured temperature exceeds
the programmed THERM temperature. The ADM1034
communicates over an SMBus 2.0 interface. Its LOCATION
input determines which version of SMBus to use, as well as the
SMBus address (in fixed-and-discoverable mode) and the
LOCATION bits in the UDID (in ARP-capable mode).
INTERNAL REGISTERS Table 4 gives a brief description of the ADM1034’s principal
internal registers. For more detailed information on the
function of each register, refer to Table 34.
SERIAL BUS INTERFACE The ADM1034 communicates with the master via the 2-wire
SMBus 2.0 interface. It supports two versions of SMBus 2.0,
determined by the value of the LOCATION input’s resistors.
The first version is fully ARP-capable. This means that it
supports address resolution protocol (ARP), allowing the
master to dynamically address the device on power-up. It
responds to ARP commands such as “Prepare to ARP.”
The second SMBus version, fixed-and-discoverable, is
backwards-compatible with SMBus 1.0 and 1.1. In this mode,
the ADM1034 powers up with a fixed address, which is
determined by the state of the LOCATION pin on power-up.
Note: When using the ADM1034, Addresses 0xC2 and 0xCA
should not be used by any other device on the bus.
LOCATION INPUT The LOCATION input is a resistor divider input. It has multiple
functions and can specify the SMBus version (in fixed-and-
discoverable or ARP-capable modes); the SMBus address (in
fixed-and-discoverable mode); and the LLL bits (in UDID in
ARP-capable mode).
The voltage of this 8-level input is set by a potential divider. The
voltage on LOCATION is sampled on power-up and digitized
by the on-chip ADC to determine the LOCATION input value.
Because the LOCATION input is sampled only at power-up,
changes made while power is applied have no effect.
VCC
GNDPIN 1304918-0-016
Figure 16. Bootstrapping the LOCATION Input
SMBus 2.0 ARP-CAPABLE MODE In ARP-capable mode, the ADM1034 supports features such as
address resolution protocol (ARP) and unique device identifier
(UDID). The UDID is a 128-bit message that describes the
ADM1034’s capabilities to the master. The UDID also includes a
vendor-specific ID for functionally equivalent devices.
VCC
1.5kΩ
1kΩ
1kΩ
1kΩ
1kΩ
1kΩ
1.5kΩ
GND
ADM1034NO.1
ADM1034NO.2
ADM1034NO.3
ADM1034NO.5
ADM1034NO.7
ARP
LOCATION = 111
ARP
ADM1034NO.4
ARP
LOCATION = 101
ARP
ADM1034NO.6
ADDRESS = 53h
ADDRESS = 52h
ADM1034NO.8
ADDRESS = 51h
ADDRESS = 50h04918-0-017
Figure 17. Setting Up Multiple ADM1034 Addresses in
SMBus 2.0 ARP-Capable Mode
In SMBus 2.0 mode, this vendor-specific ID is generated by an
on-chip random number generator. This should enable two
adjacent ADM1034s in the same system to power up with a
different vendor-specific ID, allowing the master to identify the
two separate ADM1034s and assign a different address to each.
The state of the LOCATION input on power-up is also reflected
in the UDID. This is useful when there is more than one
ADM1034 in the system, so the master knows which one it is
communicating with. The complete UDID is listed in Table 6.
The SMBus 2.0 master issues both general and directed ARP
commands. A general command is directed at all ARP devices.
A directed command is targeted at a single device once an
address has been established. The PEC byte must be used for
ARP commands. (Refer to the Packet Error Checking (PEC)
section.) The ADM1034 responds to the following commands: Prepare to ARP (general) Reset device (general and directed)
Table 4. Internal Register Descriptions
Table 5. Resistor Ratios for Setting LOCATION Bits 1 FD denotes fixed-and-discoverable mode, ARP denotes ARP-capable mode.
Table 6. UDID Values SMBus 2.0 FIXED-AND-DISCOVERABLE MODE The ADM1034 also supports fixed-and-discoverable mode,
which is backwards-compatible with SMBus 1.0 and 1.1. Fixed-
and-discoverable mode supports all the same functionality as
ARP-capable mode, except for assign address—in which case it
powers up with a fixed address and is not changed by the assign
address call. The fixed address is determined by the state of the
LOCATION pin on power-up.
SMBus 2.0 READ AND WRITE OPERATIONS The master initiates data transfer by establishing a start
condition, defined as a high-to-low transition on the serial data
line (SDA) while the serial clock line (SCL) remains high. This
indicates that an address/data stream is to follow. All slave
peripherals connected to the serial bus respond to the start
condition and shift in the next 8 bits, which consist of a 7-bit
address (MSB first) plus an R/W bit. This last bit determines the
direction of the data transfer (whether data is written to or read
from the slave device).
1. The peripheral that corresponds to the transmitted address
responds by pulling the data line low during the low period
before the 9th clock pulse, which is known as the
acknowledge bit. All other devices on the bus remain idle
while the selected device waits for data to be read from or
written to it. If the R/W bit is a 0, the master writes to the
slave device. If the R/W bit is a 1, the master reads from it.
2. Data is sent over the serial bus in sequences of 9 clock
pulses—8 bits of data followed by an acknowledge bit from
the slave device. Transitions on the data line must occur
during the low period of the clock signal and remain stable
during the high period, because a low-to-high transition
when the clock is high may be interpreted as a stop signal.
The number of data bytes that can be transmitted over the
serial bus in a single read or write operation is limited only
by what the master and slave devices can handle.
3. When all data bytes have been read or written, stop
conditions are established. In write mode, the master pulls
the data line high during the 10th clock pulse to assert a
stop condition. In read mode, the master device overrides
the acknowledge bit by pulling the data line high during
the low period before the 9th clock pulse. This is known as
no acknowledge. The master takes the data line low during
the low period before the 10th clock pulse, then high
during the 10th clock pulse to assert a stop condition.
It is not possible to mix read and write in one operation,
because the type of operation is determined at the beginning
and cannot be changed without starting a new operation.
To write data to one of the device data registers or to read data
from it, the address pointer register (APR) must be set so that
the correct data register is addressed; then data can be written
into that register or read from it. The first byte of a write
operation always contains an address that is stored in the APR.
If data is to be written to the device, then the write operation
contains a second data byte, which is written to the register
selected by the APR.
As illustrated in Figure 18, the device address is sent over the
bus, followed by R/W set to 0. This is followed by two data
bytes. The first data byte is the address of the internal data
register to be written to, which is stored in the APR. The second
data byte is the data to be written to the internal data register.
When reading data from a register there are two possibilities.
If the ADM1034’s APR value is unknown or incorrect, it must
be set to the correct value before data can be read from the
desired data register. To do this, perform a write to the ADM1034
as before, but send only the data byte containing the register.
(See Figure 19.) A read operation is then performed, using the
serial bus address and the R/W bit set to 1, followed by the data
byte read from the data register. (See Figure 20.)
However, if the APR is already at the desired address, data can
be read from the corresponding data register without first
writing to the APR. In this case, Figure 19 can be omitted.
In Figure 18 to Figure 20, the serial bus address is determined
by the state of the LOCATION pin on power-up.
START BY
MASTER
STOP BY
MASTER
ACK. BY
ADM1034
ACK. BY
ADM1034
ACK. BY
ADM10349
SCL
SDA
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
ADDRESS POINTER REGISTER BYTE
FRAME 3
DATA BYTE
SDA (CONTINUED)
SCL (CONTINUED)104918-0-021
Figure 18. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register
STOP BY
MASTERACK. BY
ADM1034
ACK. BY
ADM1034START BY
MASTER
SCL9
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
ADDRESS POINTER REGISTER BYTE04918-0-022
SDAFigure 19. Writing to the Address Pointer Register Only (Send Byte)
STOP BY
MASTER
MASTER
ACK. BY
ADM1034
NO ACK. BY
ADM1034
R/W
SCL99
SDAA5A4A3A2A1A0D7D6D5D4D3D2D1D0
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
DATA BYTE FROM ADM103404918-0-023
Figure 20. Reading Data from a Previously Selected Register
REGISTER ADDRESSES FOR
SINGLE/BLOCK BYTE MODES The ADM1034 supports single-byte as well as block read and
write operations. The register address determines whether a
single-byte or multiple-byte (block) operation is run. For a
single-byte operation, the MSB of the register address is set to 0;
for a multiple-byte operation, it is set to 1. The number of bytes
read in a multiple-byte operation is set in the #Bytes/Block Read
Register at Address 0x00. The number of bytes written to the
ADM1034 is specified during the block-write operation. The
addresses quoted in the register map and throughout this data
sheet assume single-byte operation. For multiple-byte
operations, set the MSB of each register address to 1.
WRITE OPERATIONS The SMBus specifications define protocols for read and write
operations. The ADM1034 supports send-byte, write-byte, and
block-byte SMBus write protocols. The following abbreviations
are used in the diagrams:
S—START
P—STOP
R—READ
W—WRITE
A—ACKNOWLEDGE
A—NO ACKNOWLEDGE
Send Byte In this operation, the master device sends a single-command
byte to a slave device as follows:
1. The master device asserts a start condition on SDA.
2. The master sends a 7-bit address followed by the write bit
(low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends the register address.
5. The slave asserts ACK on SDA.
6. The master asserts a stop condition on SDA, and the
transaction ends.
SLAVE
ADDRESSREG
ADDRESSWAAP04918-0-018
Figure 21. Send Byte
The ADM1034 uses the send-byte operation to write a register
address to the APR for a subsequent read from the same
address. (See Figure 24.) The user may be required to read data
from the register immediately after setting up the address. If so,
the master can assert a repeat start condition immediately after
the final ACK and carry out a single-byte read without asserting
Write Byte In this operation, the master device sends a register address and
one data byte to the slave device as follows:
1. The master asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by a
write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends the register address. The MSB of the
register address should equal 0 for a write-byte operation.
If the MSB equals 1, a block-write operation takes place.
5. The slave asserts ACK on SDA.
6. The master sends a data byte.
7. The slave asserts ACK on SDA.
8. The master asserts a stop condition on SDA to end the
transaction.
SLAVE
ADDRESSREG
ADDRESSDATAWAAAP04918-0-019
Figure 22. Write Byte Operation
Block Write In this operation, the master device writes a block of data to a
slave address as follows. A maximum of 32 bytes can be written.
1. The master asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by a
write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends the register address. The register address
sets up the address pointer register and determines
whether a block-write (MSB = 1) or a byte-write (MSB = 0)
takes place.
5. The slave asserts ACK on SDA.
6. The master sends the byte count.
7. The slave asserts ACK on SDA.
8. The master sends N data bytes.
9. The slave asserts ACK on SDA after each byte.
10. The master asserts a stop condition on SDA to end the
transaction.
SLAVE
ADDRESSBYTE
COUNTDATA 2DATA 1REGISTER
ADDRESSWAAPAAAFigure 23. Block Write to RAM
READ OPERATIONS
Receive Byte This is useful when repeatedly reading a single register. The
register address must be set up prior to this, with the MSB at 0
to read a single byte. In this operation, the master device
receives a single byte from a slave device as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by the
read bit (high).
3. The addressed slave device asserts ACK on SDA.
4. The master receives a data byte.
5. The master sends NO ACK on SDA.
6. The master asserts a stop condition on SDA, and the
transaction ends.
In the ADM1034, the receive-byte protocol is used to read a
single byte from a register whose address has previously been
set by a send-byte or write-byte operation.
SLAVE
ADDRESSDATARAAP04918-0-024
Figure 24. Receive Byte
Block Read In this operation, the master reads a block of data from a slave
device. The number of bytes to be read must be set in advance.
To do this, use a write-byte operation to the #Bytes/Block Read
Register at Address 0x00. The register address determines
whether a block-read or a read-byte operation is to be completed
(set MSB to 1 to specify a block-read operation). A maximum of
32 bytes can be read.
1. The master asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by the
write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends the register address (MSB = 1).
5. The slave asserts ACK on SDA.
6. The master asserts a repeated start on SDA.
7. The master sends the 7-bit slave address followed by the
read bit (high).
8. The slave asserts ACK on SDA.
9. The slave sends the byte count.
10. The master asserts ACK on SDA.
11. The slave sends N data bytes.
12. The master asserts ACK on SDA after each data byte.
13. The master does not acknowledge after the Nth data byte.
14. The master asserts a stop condition on SDA to end the
SLAVEADDRESSBYTECOUNTDATA 1REGISTERADDRESSWAPAASLAVEADDRESSSRA025
Figure 25. Block Read from RAM
SMBus TIMEOUT The ADM1034 has a programmable SMBus timeout feature.
When this is enabled, the SMBus typically times out after 25 ms
of no activity. The timeout is disabled by default. It prevents
hangups by releasing the bus after a period of inactivity.
To enable the SDA timeout, set the SDA timeout bit (Bit 5) of
Configuration Register 1 (Address 0x01) to 1.
To enable the SCL timeout, set the SCL timeout bit (Bit 4) of
Configuration Register 1 (Address 0x01) to 1.
PACKET ERROR CHECKING (PEC) The ADM1034 also supports packet error checking (PEC). This
optional feature is triggered by the extra clock for the PEC byte.
The PEC byte is calculated using CRC-8. The frame check
sequence (FCS) conforms to CRC-8 by the following: )128+++=xxxxC
For more information, consult www.SMBus.org.
ALERT RESPONSE ADDRESS (ARA) ADDRESSDEVICEADDRESSRAAP04918-0-043
Figure 26. ALERT Response Address
When multiple devices exist on the same bus, the ARA feature
allows an interrupting device to identify itself to the host.
The ALERT output can be used as an interrupt output or as an
SMBusALERT. One or more ALERT outputs can be connected
to a common SMBusALERT line, connected to the master.
If a device’s ALERT line goes low, the following occurs:
1. SMBusALERT is pulled low.
2. The master initiates a receive-byte operation and sends the
alert response address (ARA 0001 100). This is a general
call address that must not be used as a specific address.
3. The device with the low ALERT output responds to the
ARA, and the master reads its device address. Once the
address is known, it can be interrogated in the usual way.
4. If low ALERT output is detected in more than one device,
the one with the lowest device address has priority, in
accordance with normal SMBus arbitration.
5. Once the ADM1034 has responded to the ARA, it resets its
ALERT output. However, if the error persists, the ALERT is
TEMPERATURE MEASUREMENT SYSTEM
INTERNAL TEMPERATURE MEASUREMENT The ADM1034 contains an on-chip band gap temperature
sensor. The on-chip ADC performs conversions on the sensor’s
output, outputting the data in 13-bit format. The resolution of
the local temperature sensor is 0.03125°C.
Table 7 shows the format of the temperature data MSBs. Table 8
shows the same for the LSBs. To ensure accurate readings, read
the LSBs first. This locks the current LSBs and MSBs until the
MSBs are read. They then start to update again. (Reading only
the MSBs does not lock the registers.) Temperature updates to
the look-up table take place in parallel; so fan speeds may be
updated even if the MSBs are locked.
Table 7. Temperature Data Format
(Local Temperature and Remote Temperature High Bytes)
Table 8. Local and Remote Sensor Extended Resolution Temperature (°C) = (MSB − 64°C) + (LSB × 0.03125)
Example: MSB = 0101 0100 = 84d
LSB = 11100 = 28
Temperature °C = (84 – 64) + (28 × 0.03125) = 20.875
REMOTE TEMPERATURE MEASUREMENT The ADM1034 can measure the temperature of two external
diode sensors or diode-connected transistors, which are
connected to Pins 9 and 10 and Pins 11 and 12. These pins are
dedicated temperature input channels. The series resistance
cancellation (SRC) feature can automatically cancel out the
effect of up to 1 kΩ of resistance in series with the remote
thermal diode.
The forward voltage of a diode or diode-connected transistor,
operated at a constant current, exhibits a negative temperature
coefficient of about −2 mV/°C. Unfortunately, the absolute
value of Vbe varies from device to device, and individual
calibration is required to null this out. Therefore, the technique
is unsuitable for mass production.
2N39042N3906
Figure 27. Measuring Temperature by Using Discreet Transistors
The ADM1034 operates at three different currents to measure
the change in Vbe. Figure 28 shows the input signal conditioning
used to measure the output of an external temperature sensor. It
also shows the external sensor as a substrate transistor, provided
for temperature monitoring on some microprocessors. The
external sensor could work equally well as a discrete transistor.
If a discrete transistor is used, the collector is not grounded, and
should be linked to the base. If a PNP transistor is used, the base
is connected to the D− input and the emitter to the D+ input. If
an NPN transistor is used, the emitter is connected to the D−
input and the base to the D+ input.
If the sensor is used in a very noisy environment, a capacitor
value up to 1000 pF may be placed between the D+ and D−
inputs to filter the noise. However, additional parasitic
capacitance on the lines between D+, D−, and the thermal diode
should also be considered. The total capacitance should never
be greater than 1000 pF.
To measure each ∆Vbe, the sensor is switched between operating
currents of I, (N1 × I), and (N2 × I). The resulting waveform is
passed through a 65 kHz low-pass filter to remove noise, then to
a chopper-stabilized amplifier that amplifies and rectifies the
waveform. This produces a dc voltage proportional to ∆Vbe.
These voltage measurements determine the temperature of the
thermal diode, while automatically compensating for any series
resistance on the D+ and/or D− lines. The temperature is stored
in two registers as a 13-bit word.
To further reduce the effects of noise, digital filtering is
performed by averaging the results of 16 measurement cycles at
conversion rates of less than or equal to 8 Hz. An external
temperature measurement takes nominally 32 ms when
averaging is enabled and 6 ms when averaging is disabled.
One LSB of the ADC corresponds to 0.03125°C. The ADM1034
can theoretically measure temperatures from −64°C to
+191.96875°C, although these are outside its operating range.
The extended temperature resolution data format is shown in
Table 8. The data for the local and remote channels is stored in
the extended temperature resolution registers (Reg. 0x40 =
Local, Reg. 0x42 = Remote 1, and Reg. 0x44 = Remote 2).
Table 9.Temperature Measurement Registers High and low temperature limit registers are associated with
each temperature measurement channel. Exceeding the
programmed high and low limits sets the appropriate status bit.
Exceeding either limit can cause an SMBusALERT interrupt.
Table 10. Temperature Measurement Limit Registers
REMOTE
SENSINGTRANSISTOR
VOUT+
TO ADC
VOUT–04918-0-027
Figure 28. ADM1034 Signal Conditioning
ADDITIONAL FUNCTIONS Several other temperature measurement functions available on
the ADM1034 offer the systems designer added flexibility.
Turn-off Averaging The ADM1034 performs averaging at conversion rates of less
than or equal to 8 conversions per second. This means that the
value in the measurement register is the average of 16 measure-
ments. For faster measurements, set the conversion rate to 16
conversions per second or greater. (Averaging is not carried out
at these conversion rates.) Alternatively, switch off averaging at
the slower conversion rates by setting Bit 1 (AVG) of
Configuration 1 Register (Address 0x01).
Single-Channel ADC Conversions In normal operating mode, the ADM1034 converts on three
temperature channels: the local temperature channel, and the
remote 1 and remote 2 channels. However, the user has the
option to set up the ADM1034 to convert on one channel only.
To enable single-channel mode, the user sets the round-robin
bit (Bit 7) in Configuration Register 2 (Address 0x02) to 0.
When the round-robin bit equals 1, the ADM1034 converts on
all three temperature channels. In single-channel mode, it
converts on one channel only, to be determined by the state of
the channel selector bits (Bits 5 and 4) of the Configuration
Register 2 (Address 0x02).
Table 11. Channel Selector
Removing Temperature Errors As CPUs run faster and faster, it gets more difficult to avoid
high frequency clocks when routing the D+ and D− traces
around a system board. Even when the recommended layout
guidelines are followed, temperature errors attributed to noise
coupled onto the D+ and D− lines remain. High frequency
noise generally gives temperature measurements that are
consistently too high. The ADM1034 has Local, Remote 1, and
Remote 2 temperature offset registers at 0x16, 0x17, and 0x18—
one for each channel. By completing a one-time calibration, the
user can determine the offset caused by the system board noise
and remove it using the offset registers. The registers
automatically add a twos compliment word to the remote
temperature measurements, ensuring correct readings in the
value registers.
Table 12. Offset Registers
Table 13. Offset Register Values LAYOUT CONSIDERATIONS Digital boards can be electrically noisy environments. Try
to protect the analog inputs from noise, particularly when
measuring the very small voltages from a remote diode sensor.
Take the following precautions: Place the ADM1034 as close as possible to the remote
sensing diode. A distance of 4 inches to 8 inches is
adequate, provided that the worst noise sources such
as clock generators, data/address buses, and CRTs are
avoided. Route the D+ and D− tracks close together, in parallel, with
grounded guard tracks on each side. Provide a ground
plane under the tracks if possible. Use wide tracks to minimize inductance and reduce noise
pickup. At least 5 mil track width and spacing are
recommended.
GND
GND04918-0-028
Figure 29. Arrangement of Signal Tracks Try to minimize the number of copper/solder joints,
because they can cause thermocouple effects. Where
copper/solder joints are used, make sure that they are in
both the D+ and D− paths and at the same temperature.
Thermocouple effects are not a major problem because
1°C corresponds to approximately 200 µV, and thermocou-
ple voltages are approximately 3 µV/°C of temperature
difference. Unless there are two thermocouples with a big
temperature differential between them, the voltages should
be much less than 200 µV. Place a 0.1 µF bypass capacitor close to the ADM1034. If the distance to the remote sensor is more than 8 inches,
twisted pair cable is recommended. This works up to about
6 feet to 12 feet. For very long distances (up to 100 feet), use shielded
twisted pair such as Belden #8451 microphone cable.
Connect the twisted pair to D+ and D− and the shield to
GND, close to the ADM1034. Leave the remote end of the
shield unconnected to avoid ground loops.
Because the measurement technique uses switched current
sources, excessive cable and/or filter capacitance can affect the
measurement. When using long cables, the filter capacitor C1
may be reduced or removed. In any case, the total shunt
capacitance should never exceed 1000 pF.
Noise Filtering For temperature sensors operating in noisy environments,
common practice is to place a capacitor across the D+ and D−
pins to help combat the effects of noise. However, large
capacitances affect the accuracy of the temperature measurement,
leading to a recommended maximum capacitor value of 1000 pF.
While this capacitor reduces the noise, it does not eliminate it,
making it difficult to use the sensor in a very noisy environment.
The ADM1034 has a major advantage over other devices when
it comes to eliminating the effects of noise on the external
sensor. The series resistance cancellation feature allows a filter
to be constructed between the external temperature sensor and
the part. The effect of any filter resistance seen in series with the
remote sensor is automatically cancelled from the temperature.
The construction of a filter allows the ADM1034 and the
remote temperature sensor to operate in noisy environments.
Figure 30 shows a low-pass R-C-R filter with the following
values: R = 100 Ω and C = 1 nF. This filtering reduces both
common-mode noise and differential noise.
100ΩSENSOR
Figure 30. Filter between Remote Sensor and ADM1034
LIMITS, STATUS REGISTERS, AND INTERRUPTS High and low limits are associated with each measurement
channel on the ADM1034. These can form the basis of system
status monitoring. A status bit can be set for any out-of-limit
condition and detected by polling the device. Alternatively,
SMBusALERTs can be generated to flag a processor or
microcontroller of an out-of-limit condition.
8-BIT LIMITS The following is a list of all the 8-bit limits on the ADM1034:
Table 14. Temperature Limit Registers
Table 15. THERM Limit Register
OUT-OF-LIMIT COMPARISONS The ADM1034 measures all parameters in a round-robin
format and sets the appropriate status bit for out-of limit
conditions. Comparisons are made differently, depending on
whether the measured value is compared to a high or low limit.
High Limit: ≥ Comparison Performed
Low Limit: < Comparison Performed
ANALOG MONITORING CYCLE TIME The analog monitoring cycle time begins on power-up, or, if
monitoring has been disabled, by writing a 1 to the monitor/
STBY bit of Configuration Register 1, (Address 0x01). The ADC
measures each one of the analog inputs in turn; as each
measurement is completed, the result is automatically stored in
the appropriate value register. The round-robin monitoring
cycle continues unless it is disabled by writing a 0 to the
monitor/STBY bit (Bit 0) of Configuration Register 1
(Address 0x01).
The ADC performs round-robin conversions and takes 11 ms
for the local temperature measurement and 32 ms for each
remote temperature measurement with averaging enabled.
The total monitoring cycle time for the average temperatures is
therefore nominally
(2 × 32) + 11 = 75 ms
Once the conversion time elapses, the round robin starts again.
For more information, refer to the Conversion Rate Register
section.
Fan TACH measurements take place in parallel and are not
synchronized with the temperature measurements in any way.
STATUS REGISTERS The results of limit comparisons are stored in the status
registers. A 1 represents an out-of-limit measurement; a
0 represents an in-limit measurement. The status registers are
located at Addresses 0x4F to 0x51.
If the measurement is outside its limits, the corresponding
status register bit is set to 1. It remains set at 1 until the
measurement falls back within its limits and it is read or until
an ARA is completed.
Poll the state of the various measurements by reading the status
registers over the serial bus. If Bit 0 (ALERT low) of Status
Register 3 (Address 0x51) is set, this means that the ALERT
output has been pulled low by the ADM1034.
Pin 14 can be configured as a SMBusALERT output. This
automatically notifies the system supervisor of an out-of-limit
condition. Reading the status register clears the status bit as long
as the error condition is gone.
Status register bits are sticky. Whenever a status bit is set due to
an out-of-limit condition, it remains set—even after the
triggering event has gone. The only way to clear the status bit is
to read the status register (after the event has gone). Interrupt
mask registers (Reg. 0x08, Reg. 0x09, Reg. 0x0A) allow
individual interrupt sources to be masked from causing an
ALERT. However, if one of these masked interrupt sources goes
out of limit, its associated status bit is set in the status register.
