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ADM1026JST-REEL-ADM1026JST-REEL7-ADM1026JSTZ-ADM1026JSTZ-REEL-ADM1026JSTZ-REEL7
Highly Integrated Thermal and System Monitor for Servers/High Reliability Systems
Complete Thermal System
Management Controller
Rev. A
FEATURES
Up to 19 analog measurement channels (including internal
measurements)
Up to 8 fan speed measurement channels
Up to 17 general-purpose logic I/O pins
Remote temperature measurement with remote diode (two
channels)
On-chip temperature sensor
Analog and PWM fan speed control outputs
2-wire serial system management bus (SMBus)
8 kB on-chip EEPROM
Full SMBus 1.1 support includes packet error checking (PEC)
Chassis intrusion detection
Interrupt output (SMBAlert)
Reset input, reset outputs
Thermal interrupt (THERM) output
Limit comparison of all monitored values
APPLICATIONS
Network servers and personal computers
Telecommunications equipment
Test equipment and measuring instruments
D2–/AIN9(0V– +2.5V)(0V– +2.5V)
AIN7(0V– +2.5V)
AIN6(0V– +2.5V)
VBAT
+5 VIN
–12 VIN
+12 VIN
+VCCP
AIN0(0V– +3V)
AIN1(0V– +3V)
AIN2(0V– +3V)
AIN3(0V– +3V)
AIN4(0V– +3V)
AIN5(0V– +3V)
D1+
D1–/NTESTIN
DGND
DAC
AGNDVREF (1.82V OR 2.5V)
SCLSDA3.3V MAIN
ADD/
NTESTOUT
FAN7/GPIO7
FAN6/GPIO6
FAN5/GPIO5
FAN4/GPIO4
FAN3/GPIO3
FAN2/GPIO2
FAN1/GPIO1
FAN0/GPIO0
GPIO15
GPIO14
GPIO13
GPIO12
GPIO11
GPIO10
GPIO9
GPIO8
PWM
3.3V STBY
GPIO16/THERM
INT
RESETMAIN
RESETSTBY02657-A
Figure 1. Functional Block Diagram
TABLE OF CONTENTS Specifications.....................................................................................3
Absolute Maximum Ratings............................................................5
Thermal Characteristics..............................................................5
ESD Caution..................................................................................5
Pin Configuration and Function Descriptions.............................6
Typical Performance Characteristics.............................................8
Product Description.......................................................................10
Functional Description..............................................................10
Internal Registers........................................................................11
EEPROM.....................................................................................11
SMBus Protocols for RAM and EEPROM..............................13
Measurement Inputs..................................................................16
Temperature Measurement System..........................................20
Analog Output............................................................................22
Fan Speed Measurement...........................................................25
Enabling and Clearing Interrupts............................................29
NAND Tree Tests........................................................................31
Using the ADM1026..................................................................33
Registers...........................................................................................36
Detailed Register Descriptions.................................................38
Outline Dimensions.......................................................................54
Ordering Guide..........................................................................55
REVISION HISTORY
3/04—Data Sheet Changed from Rev. 0 to Rev. A Updated Format..................................................................Universal
Change to Footnote 4, Table 1..........................................................4
Added Figure 15.................................................................................9
Changes to Table 6..........................................................................17
Changes to Figure 27......................................................................18
Change to Figure 31.......................................................................19
Change to Battery Measurement Input Section.........................19
Changes to Table 7..........................................................................21
Changes to Equations in Fan Speed Measurement Section......26
Change to Chassis Intrusion Input Section................................27
Changes to Reset Input and Outputs Section.............................31
Changes to Software Reset Function Section.............................34
Changes to Ordering Guide..........................................................55
5/02—Revision 0: Initial Version
SPECIFICATIONS1, 2, 3
Table 1. TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted.
All voltages are measured with respect to GND, unless otherwise specified. Typicals are at TA = 25°C and represent the most likely parametric norm. Shutdown current typ is measured with VCC = 3.3 V. Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge and VIH = 2.1 V for a rising edge. Total unadjusted error (TUE) includes offset, gain, and linearity errors of the ADC, multiplexer, and on-chip input attenuators. VBAT is accurate only for VBAT voltages
greater than 1.5 V (see Figure 15).
5 Total analog monitoring cycle time is nominally 273 ms, made up of 18 ms × 11.38 ms measurements on analog input and internal temperature channels, and
2 ms × 34.13 ms measurements on external temperature channels.
6 The total fan count is based on two pulses per revolution of the fan tachometer output. The total fan monitoring time depends on the number of fans connected and
the fan speed. See the Fan Speed Measurement section for more details.
7 ADD is a three-state input that may be pulled high, low, or left open-circuit.
8 Logic inputs accept input high voltages up to 5 V even when device is operating at supply voltages below 5 V.
ABSOLUTE MAXIMUM RATINGS
Table 2. Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL CHARACTERISTICS 48-Lead LQFP package θJA = 50°C/W, θJC = 10°C/W
SCL
SDAFigure 2. Serial Bus Timing Diagram
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS GPIO9
GPIO8
FAN0/GPIO0
FAN1/GPIO1
FAN2/GPIO2
FAN3/GPIO3
3.3V MAIN
DGND
FAN4/GPIO4
FAN5/GPIO5
FAN6/GPIO6
FAN7/GPIO7
ADD/NTE
TOUT
INT
ESETSTB
ESETM
AGND
3.3V STB
DAC
AIN5(0V– 3V)
AIN6(0V– 2.5V)
AIN7(0V– 2.5V)
+VCCP
+12 VIN
–12 VIN
+5 VIN
VBAT
D2+/AIN8(0V– 2.5V)
D2–/AIN9(0V– 2.5V)
D1+
D1–/NTESTIN
GPIO10GPIO11GPIO12GPIO13GPIO14GPIO15GPIO16/
IN0
IN1
IN2
IN3
IN402657-A
Figure 3. Pin Configuration
Table 3.
GPIO pins are open drain and require external pull-up resistors. Fan inputs have integrated 10 kΩ pull-ups, but these pins become open drain when reconfigured as
GPIOs.
TYPICAL PERFORMANCE CHARACTERISTICS
LEAKAGE RESISTANCE (MΩ)
RATURE
RROR (
°C)10
–1502657-A
Figure 4. Temperature Error vs. PCB Track Resistance
FREQUENCY (MHz)
RATURE
RROR (°C)02657-A
Figure 5. Temperature Error vs. Power Supply Noise Frequency
FREQUENCY (MHz)
RATURE
RROR (°C)02657-A
Figure 6. Temperature Error vs. Common-Mode Noise Frequency
PIII TEMPERATURE (°C)
ADING (°C)
11002657-A
Figure 7. Pentium® III Temperature vs. ADM1026 Reading
CAPACITANCE (nF)
RATURE
RROR (
°C)
–2502657-A
Figure 8. Temperature Error vs. Capacitance Between D+ and D–
FREQUENCY (MHz)
RATURE
RROR (°C)02657-A
Figure 9. Temperature Error vs. Differential-Mode Noise Frequency
TEMPERATURE (°C)
ESET TIM
T (
45002657-A
Figure 10. Power-up Reset Timeout vs. Temperature
VCC(V)
(mA)
0.502657-A
Figure 11. Supply Current vs. Supply Voltage
TEMPERATURE(°C)
RATURE
RROR (°C)
1.802657-A
Figure 12. Local Sensor Temperature Error
TEMPERATURE (°C)
RATURE
RROR (°C)
–2.002657-A
Figure 13. Remote Sensor Temperature Error
TIME (s)
RATURE
(°C)
12002657-A
Figure 14. Response to Thermal Shock
VBAT VOLTAGE
BAT
ME
URE02657-A
Figure 15. VBAT Measurement vs. Voltage
PRODUCT DESCRIPTION The ADM1026 is a complete system hardware monitor for
microprocessor-based systems, providing measurement and
limit comparison of various system parameters. The ADM1026
has up to 19 analog measurement channels. Fifteen analog
voltage inputs are provided, five of which are dedicated to
monitoring +3.3 V, +5 V, and ±12 V power supplies, and the
processor core voltage. The ADM1026 can monitor two other
power supply voltages by measuring its own VCC and the main
system supply. One input (two pins) is dedicated to a remote
temperature-sensing diode. Two additional pins can be
configured as general-purpose analog inputs to measure
0 V to 2.5 V, or as a second temperature sensing input. The eight
remaining inputs are general-purpose analog inputs with a
range of 0 V to 2.5 V or 0 V to 3 V. The ADM1026 also has an
on-chip temperature sensor.
The ADM1026 has eight pins that can be configured for fan
speed measurement or as general-purpose logic I/O pins.
Another eight pins are dedicated to general-purpose logic I/O.
An additional pin can be configured as a general-purpose I/O
or as the bidirectional THERM pin.
Measured values can be read out via a 2-wire serial system
management bus, and values for limit comparisons can be
programmed over the same serial bus. The high speed,
successive approximation ADC allows frequent sampling of all
analog channels to ensure a fast interrupt response to any out-
of-limit measurement.
FUNCTIONAL DESCRIPTION The ADM1026 is a complete system hardware monitor for
microprocessor-based systems. The device communicates with
the system via a serial system management bus. The serial bus
controller has a hardwired address line for device selection
(ADD, Pin 15), a serial data line for reading and writing
addresses and data (SDA, Pin 14), and an input line for the
serial clock (SCL, Pin 13). All control and programming
functions of the ADM1026 are performed over the serial bus.
Measurement Inputs Programmability of the analog and digital measurement inputs
makes the ADM1026 extremely flexible and versatile. The
device has an 8-bit A/D converter, and 17 analog measurement
input pins that can be configured in different ways.
Pins 25 and 26 are dedicated temperature inputs and may be
connected to the cathode and anode of a remote temperature-
sensing diode.
Pins 27 and 28 may be configured as temperature inputs and
connected to a second temperature-sensing diode, or may be
reconfigured as analog inputs with a range of 0 V to 2.5 V.
Pins 29 to 33 are dedicated analog inputs with on-chip
attenuators configured to monitor VBAT, +5 V, −12 V, +12 V,
and the processor core voltage VCCP, respectively.
Pins 34 to 41 are general-purpose analog inputs with a range
of 0 V to 2.5 V or 0 V to 3 V. These are mainly intended for
monitoring SCSI termination voltages, but may be used for
other purposes.
The ADC also accepts input from an on-chip band gap
temperature sensor that monitors system ambient temperature.
In addition, the ADM1026 monitors the supply from which it is
powered, 3.3 V STBY, so there is no need for a separate pin to
monitor the power supply voltage.
The ADM1026 has eight pins that are general-purpose logic
I/O pins (Pins 1, 2, and 43 to 48), a pin that can be configured
as GPIO or as a bidirectional thermal interrupt (THERM) pin
(Pin 42), and eight pins that can be configured for fan speed
measurement or as general-purpose logic pins (Pins 3 to 6 and
Pins 9 to 12).
Sequential Measurement When the ADM1026 monitoring sequence is started, it cycles
sequentially through the measurement of analog inputs and the
temperature sensor, while at the same time the fan speed inputs
are independently monitored. Measured values from these
inputs are stored in value registers. These can be read over the
serial bus, or can be compared with programmed limits stored
in the limit registers. The results of out-of-limit comparisons are
stored in the interrupt status registers. An out-of-limit event
generates an interrupt on the INT line (Pin 17).
Any or all of the interrupt status bits can be masked by
appropriate programming of the interrupt mask registers.
Chassis Intrusion A chassis intrusion input (Pin 16) is provided to detect
unauthorized tampering with the equipment. This event is
latched in a battery-backed register bit.
Resets The ADM1026 has two power-on reset outputs, RESETMAIN
and RESETSTBY, that are asserted when 3.3 V MAIN or 3.3 V
STBY fall below the reset threshold. These give a 180 ms reset
pulse at power-up. RESETMAIN also functions as an active-low
RESET input.
Fan Speed Control Outputs The ADM1026 has two outputs intended to control fan speed,
though they can also be used for other purposes. Pin 18 is an
open drain, pulse width modulated (PWM) output with a
programmable duty cycle and an output frequency of 75 Hz.
Pin 23 is connected to the output of an on-chip, 8-bit, digital-to-
analog converter with an output range of 0 V to 2.5 V.
Either or both of these outputs may be used to implement a
temperature-controlled fan by controlling the speed of a fan
using the temperature measured by the on-chip temperature
sensor or remote temperature sensors.
INTERNAL REGISTERS Table 4 describes the principal registers of the ADM1026. For
more detailed information, see Table 11 to Table 124.
Table 4. Principal Registers
EEPROM The ADM1026 has 8 kB of nonvolatile, electrically erasable,
programmable read-only memory (EEPROM) from register
Addresses 8000h to 9FFFh. This may be used for permanent
storage of data that is not lost when the ADM1026 is powered
down, unlike the data in the volatile registers. Although referred
to as read-only memory, the EEPROM can be written to (as well
as read from) via the serial bus in exactly the same way as the
other registers. The main differences between the EEPROM and
other registers are An EEPROM location must be blank before it can be
written to. If it contains data, it must first be erased. Writing to the EEPROM should be restricted because its
typical cycle life is 100,000 write operations, due to the
usual EEPROM wear-out mechanisms.
The EEPROM in the ADM1026 has been qualified for two key
EEPROM memory characteristics: memory cycling endurance
and memory data retention.
Endurance qualifies the ability of the EEPROM to be cycled
through many program, read, and erase cycles. In real terms,
a single endurance cycle is composed of four independent,
sequential events, as follows:
1. Initial page erase sequence
2. Read/verify sequence
3. Program sequence
4. Second read/verify sequence
In reliability qualification, every byte is cycled from 00h to FFh
until a first fail is recorded, signifying the endurance limit of the
EEPROM memory.
Retention quantifies the ability of the memory to retain its
programmed data over time. The EEPROM in the ADM1026
has been qualified in accordance with the formal JEDEC
Retention Lifetime Specification (A117) at a specific junction
temperature (TJ = 55°C) to guarantee a minimum of 10 years
retention time. As part of this qualification procedure, the
EEPROM memory is cycled to its specified endurance limit
described above before data retention is characterized. This
means that the EEPROM memory is guaranteed to retain its
data for its full specified retention lifetime every time the
EEPROM is reprogrammed. Note that retention lifetime based
on an activation energy of 0.6 V derates with TJ, as shown in
Figure 16.
JUNCTION TEMPERATURE (°C)
NTION (Y
15002657-A
Figure 16. Typical EEPROM Memory Retention
Serial Bus Interface Control of the ADM1026 is carried out via the serial system
management bus (SMBus). The ADM1026 is connected to this
bus as a slave device, under the control of a master device.
The ADM1026 has a 7-bit serial bus slave address. When the
device is powered on, it does so with a default serial bus address.
The 5 MSBs of the address are set to 01011, and the 2 LSBs are
determined by the logical states of Pin 15 ADD/NTESTOUT.
This pin is a three-state input that can be grounded, connected
to VCC, or left open-circuit to give three different addresses.
Table 5. Address Pin Truth Table If ADD is left open-circuit, the default address is 0101110
(5Ch). ADD is sampled only at power-up on the first valid
SMBus transaction, so any changes made while the power is on
(and the address is locked) have no effect.
The facility to make hardwired changes to device addresses
allows the user to avoid conflicts with other devices sharing the
same serial bus, for example if more than one ADM1026 is used
in a system.
General SMBus Timing Figure 17 and Figure 18 show timing diagrams for general read
and write operations using the SMBus. The SMBus specification
defines specific conditions for different types of read and write
operations, which are discussed later in this section.
The general SMBus protocol1 operates as follows:
1. The master initiates data transfer by establishing a start
condition, defined as a high-to-low transition on the serial
data line (SDA) while the serial clock line SCL remains
high. This indicates that a data stream follows. All slave
peripherals connected to the serial bus respond to the start
condition and shift in the next 8 bits, consisting of a 7-bit
slave address (MSB first) and an R/W bit, which determine
the direction of the data transfer, that is, whether data is
written to or read from the slave device
(0 = write, 1 = read).
The peripheral whose address corresponds to the trans-
mitted address responds by pulling the data line low during
the low period before the ninth clock pulse, known as the
acknowledge bit, and holding it low during the high period
of this clock pulse. All other devices on the bus remain idle
while the selected device waits for data to be read from or
written to it. If the R/W bit is 0, the master writes to the
slave device. If the R/W bit is 1, the master reads from the
slave device.
2. Data is sent over the serial bus in sequences of nine clock
pulses, 8 bits of data followed by an acknowledge bit from
the slave device. Data transitions on the data line must
occur during the low period of the clock signal and re-
main stable during the high period, because a low-to-high
transition when the clock is high may be interpreted as
a stop signal.
If the operation is a write operation, the first data byte after
the slave address is a command byte. This tells the slave
device what to expect next. It may be an instruction telling
the slave device to expect a block write, or it may simply be
a register address that tells the slave where subsequent data
is to be written.
Because data can flow in only one direction as defined by
the R/W bit, it is not possible to send a command to a slave
device during a read operation. Before doing a read oper-
ation, it may first be necessary to do a write operation to
tell the slave what type of read operation to expect and/or
the address from which data is to be read.
3. When all data bytes have been read or written, stop
conditions are established. In write mode, the master pulls
the data line high during the 10th clock pulse to assert a
stop condition. In read mode, the master
device releases the SDA line during the low period before
the ninth clock pulse, but the slave device does not pull
it low (called No Acknowledge). The master takes the data
line low during the low period before the 10th clock pulse,
then high during the 10th clock pulse to assert a stop
condition.
1 If it is required to perform several read or write operations in succession, the
master can send a repeat start condition instead of a stop condition to begin
a new operation.
SCL
SDA
ACK. BY
SLAVE
START BY
MASTER
FRAME 1SLAVE ADDRESSFRAME 2COMMAND CODE1
ACK. BY
SLAVE
ACK. BYSLAVESTOP BYMASTER
FRAME NDATA BYTE9
SCL(CONTINUED)
SDA
(CONTINUED)
ACK. BYSLAVE
FRAME 3DATA BYTE02657-A
Figure 17. General SMBus Write Timing Diagram
SCL
SDA
ACK. BYMASTER
START BY
MASTER
FRAME 1SLAVE ADDRESSFRAME 2DATA BYTE1
ACK. BY
SLAVE
NO ACK.STOP BY
MASTER
FRAME N
DATA BYTE9
SCL(CONTINUED)
SDA
(CONTINUED)
ACK. BYMASTER
FRAME 3DATA BYTE02657-A
Figure 18. General SMBus Read Timing Diagram
SMBus PROTOCOLS FOR RAM AND EEPROM The ADM1026 contains volatile registers (RAM) and non-
volatile EEPROM. RAM occupies Addresses 00h to 6Fh, while
EEPROM occupies Addresses 8000h to 9FFFh.
Data can be written to and read from both RAM and EEPROM
as single data bytes and as block (sequential) read or write
operations of 32 data bytes, the maximum block size allowed by
the SMBus specification.
Data can only be written to unprogrammed EEPROM locations.
To write new data to a programmed location, it is first necessary
to erase it. EEPROM erasure cannot be done at the byte level;
the EEPROM is arranged as 128 pages of 64 bytes, and an entire
page must be erased. Note that of these 128 pages, only 124
pages are available to the user. The last four pages are reserved
for manufacturing purposes and cannot be erased/rewritten.
The EEPROM has three RAM registers associated with it,
EEPROM Registers 1 and 2 are for factory use only. EEPROM
Register 3 sets up the EEPROM operating mode. Setting Bit 0 of
EEPROM Register 3 puts the EEPROM into read mode. Setting
Bit 1 puts it into programming mode. Setting Bit 2 puts it into
erase mode.
Only one of these bits must be set before the EEPROM may be
accessed. Setting no bits or more than one of them causes the
device to respond with No Acknowledge if an EEPROM read,
program, or erase operation is attempted.
It is important to distinguish between SMBus write opera-
tions, such as sending an address or command, and EEPROM
programming operations. It is possible to write an EEPROM
address over the SMBus, whatever the state of EEPROM
Register 3. However, EEPROM Register 3 must be correctly set
before a subsequent EEPROM operation can be performed. For
example, when reading from the EEPROM, Bit 0 of EEPROM
Register 3 can be set, even though SMBus write operations are
Bit 3 of EEPROM Register 3 is used for EEPROM write protec-
tion. Setting this bit prevents accidental programming or era-
sure of the EEPROM. If an EEPROM write or erase operation
is attempted when this bit is set, the ADM1026 responds with
No Acknowledge. This bit is write-once and can only be cleared
by a power-on reset.
EEPROM Register 3 Bit 7 is used for clock extend. Program-
ming an EEPROM byte takes approximately 250 µs, which
would limit the SMBus clock for repeated or block write opera-
tions. Because EEPROM block read/write access is slow, it is
recommended that this clock extend bit typically be set to 1.
This allows the ADM1026 to pull SCL low and extend the
clock pulse when it cannot accept any more data.
ADM1026 SMBus Operations The SMBus specification defines several protocols for different
types of read and write operations. The ones used in the
ADM1026 are discussed below. The following abbreviations are
used in the diagrams:
S Start
W Write
P Stop
A Acknowledge
R Read No Acknowledge
ADM1026 Write Operations
Send Byte In this operation, the master device sends a single command
byte to a slave device, as follows:
1. The master device asserts a start condition on the SDA.
2. The master sends the 7-bit slave address followed by the
write bit (low).
3. The addressed slave device asserts an ACK on the SDA.
4. The master sends a command code.
5. The slave asserts ACK on the SDA.
6. The master asserts a stop condition on the SDA and the
transaction ends.
In the ADM1026, the send byte protocol is used to write a
register address to RAM for a subsequent single-byte read from
the same address or block read or write starting at that address.
This is illustrated in Figure 19.
02657-A
Figure 19. Setting a RAM Address for Subsequent Read
If it is required to read data from the RAM immediately after
setting up the address, the master can assert a repeat start
condition immediately after the final ACK and carry out a
Write Byte/Word In this operation, the master device sends a command byte and
one or two data bytes to the slave device as follows:
1. The master device asserts a start condition on the SDA.
2. The master sends the 7-bit slave address followed by the
write bit (low).
3. The addressed slave device asserts an ACK on the SDA.
4. The master sends a command code.
5. The slave asserts an ACK on the SDA.
6. The master sends a data byte.
7. The slave asserts an ACK on the SDA.
8. The master sends a data byte (or may assert stop here.)
9. The slave asserts an ACK on the SDA.
10. The master asserts a stop condition on the SDA to end the
transaction.
In the ADM1026, the write byte/word protocol is used for four
purposes. The ADM1026 knows how to respond by the value of
the command byte and EEPROM Register 3.
The first purpose is to write a single byte of data to RAM. In
this case, the command byte is the RAM address from 00h to
6Fh and the (only) data byte is the actual data. This is illustrated
in Figure 20.
02657-A
Figure 20. Single Byte Write to RAM
The protocol is also used to set up a 2-byte EEPROM address
for a subsequent read or block read. In this case, the command
byte is the high byte of the EEPROM address from 80h to 9Fh.
The (only) data byte is the low byte of the EEPROM address.
This is illustrated in Figure 21.
02657-A
Figure 21. Setting an EEPROM Address
If it is required to read data from the EEPROM immediately
after setting up the address, the master can assert a repeat start
condition immediately after the final ACK and carry out a
single-byte read or block read operation without asserting an
intermediate stop condition. In this case, Bit 0 of EEPROM
Register 3 should be set.
The third use is to erase a page of EEPROM memory. EEPROM
memory can be written to only if it is previously erased. Before
writing to one or more EEPROM memory locations that are
already programmed, the page or pages containing those
locations must first be erased. EEPROM memory is erased by
writing an EEPROM page address plus an arbitrary byte of data
Because the EEPROM consists of 128 pages of 64 bytes, the
EEPROM page address consists of the EEPROM address high
byte (from 80h to 9Fh) and the two MSBs of the low byte. The
lower six bits of the EEPROM address (low byte only) specify
addresses within a page and are ignored during an erase
operation.
02657-A
Figure 22. EEPROM Page Erasure
Page erasure takes approximately 20 ms. If the EEPROM is
accessed before erasure is complete, the ADM1026 responds
with No Acknowledge.
Last, this protocol is used to write a single byte of data to
EEPROM. In this case, the command byte is the high byte of the
EEPROM address from 80h to 9Fh. The first data byte is the low
byte of the EEPROM address, and the second data byte is the
actual data. Bit 1 of EEPROM Register 3 must be set. This is
illustrated in Figure 23.
02657-A
Figure 23. Single-Byte Write to EEPROM
Block Write In this operation, the master device writes a block of data to a
slave device. The start address for a block write must have been
set previously. In the case of the ADM1026, this is done by a
Send Byte operation to set a RAM address or by a write
byte/word operation to set an EEPROM address.
1. The master device asserts a start condition on the SDA.
2. The master sends the 7-bit slave address followed by the
write bit (low).
3. The addressed slave device asserts an ACK on the SDA.
4. The master sends a command code that tells the slave
device to expect a block write. The ADM1026 command
code for a block write is A0h (10100000).
5. The slave asserts an ACK on the SDA.
6. The master sends a data byte (20h) that tells the slave
device that 32 data bytes are being sent to it. The master
should always send 32 data bytes to the ADM1026.
7. The slave asserts an ACK on the SDA.
8. The master sends 32 data bytes.
9. The slave asserts an ACK on the SDA after each data byte.
10. The master sends a packet error checking (PEC ) byte.
11. The ADM1026 checks the PEC byte and issues an ACK if
correct. If incorrect (NACK), the master resends the data
bytes.
12. The master asserts a stop condition on the SDA to end the
transaction.
Figure 24. Block Write to EEPROM or RAM
When performing a block write to EEPROM, Bit 1 of EEPROM
Register 3 must be set.
Unlike some EEPROM devices that limit block writes to within
a page boundary, there is no limitation on the start address
when performing a block write to EEPROM, except: There must be at least 32 locations from the start address
to the highest EEPROM address (9FFF) to avoid writing to
invalid addresses. If the addresses cross a page boundary, both pages must be
erased before programming.
ADM1026 Read Operations The ADM1026 uses the SMBus read protocols described here.
Receive Byte In this operation, the master device receives a single byte from a
slave device as follows:
1. The master device asserts a start condition on the SDA.
2. The master sends the 7-bit slave address followed by the
read bit (high).
3. The addressed slave device asserts an ACK on the SDA.
4. The master receives a data byte.
5. The master asserts a NO ACK on the SDA.
6. The master asserts a stop condition on the SDA to end the
transaction.
In the ADM1026, the receive byte protocol is used to read a
single byte of data from a RAM or EEPROM location whose
address has previously been set by a send byte or write
byte/word operation. Figure 25 shows this. When reading from
EEPROM, Bit 0 of EEPROM Register 3 must be set.
02657-A
Figure 25. Single-Byte Read from EEPROM or RAM
Block Read In this operation, the master device reads a block of data from a
slave device. The start address for a block read must have been
set previously. In the case of the ADM1026 this is done by a
send byte operation to set a RAM address, or by a write
byte/word operation to set an EEPROM address. The block read
operation consists of a send byte operation that sends a block
read command to the slave, immediately followed by a repeated
start and a read operation that reads out multiple data bytes as
follows:
1. The master device asserts a start condition on the SDA.
2. The master sends the 7-bit slave address followed by the
write bit (low).
3. The addressed slave device asserts an ACK on the SDA.
4. The master sends a command code that tells the slave
device to expect a block read. The ADM1026 command
code for a block read is A1h (10100001).
5. The slave asserts an ACK on the SDA.
6. The master asserts a repeat start condition on the SDA.
7. The master sends the 7-bit slave address followed by the
read bit (high).
8. The slave asserts an ACK on the SDA.
9. The ADM1026 sends a byte count data byte that tells the
master how many data bytes to expect. The ADM1026
always returns 32 data bytes (20h), the maximum allowed
by the SMBus 1.1 specification.
10. The master asserts an ACK on the SDA.
11. The master receives 32 data bytes.
12. The master asserts an ACK on the SDA after each data byte.
13. The ADM1026 issues a PEC byte to the master. The master
should check the PEC byte and issue another block read if
the PEC byte is incorrect.
14. A NACK is generated after the PEC byte to signal the end
of the read.
15. The master asserts a stop condition on the SDA to end the
transaction.
02657-A
Figure 26. Block Read from EEPROM or RAM
When block reading from EEPROM, Bit 0 of EEPROM
Register 3 must be set.
Note that although the ADM1026 supports packet error
checking (PEC), its use is optional. The PEC byte is calculated
using CRC-8. The frame check sequence (FCS) conforms to
CRC-8 by the polynomial:
C(x) = x8 + x2 + x1 + 1
Consult the SMBus 1.1 Specification for more information.
MEASUREMENT INPUTS The ADM1026 has 17 external analog measurement pins that
can be configured to perform various functions. It also meas-
ures two supply voltages, 3.3 V MAIN and 3.3 V STBY, and the
internal chip temperature.
Pins 25 and 26 are dedicated to remote temperature measure-
ment, while Pins 27 and 28 can be configured as analog inputs
with a range of 0 V to 2.5 V, or as inputs for a second remote
temperature sensor.
Pins 29 to 33 are dedicated to measuring VBAT, +5 V, −12 V,
+12 V supplies, and the processor core voltage VCCP. The
remaining analog inputs, Pins 34 to 41, are general-purpose
analog inputs with a range of 0 V to 2.5 V (Pins 34 and 35) or
0 V to 3 V (Pins 36 to 41).
A-to-D Converter (ADC) These inputs are multiplexed into the on-chip, successive
approximation, analog-to-digital converter. The ADC has a
resolution of 8 bits. The basic input range is 0 V to 2.5 V, which
is the input range of AIN6 to AIN9, but five of the inputs have
built-in attenuators to allow measurement of VBAT, +5 V, −12 V,
+12 V, and the processor core voltage VCCP, without any external
components. To allow the tolerance of these supply voltages, the
ADC produces an output of 3/4 full scale (decimal 192) for the
nominal input voltage, and so has adequate headroom to cope
with over voltages. Table 6 shows the input ranges of the analog
inputs and output codes of the ADC.
When the ADC is running, it samples and converts an analog
or local temperature input every 711 µs (typical value). Each
input is measured 16 times and the measurements are averaged
to reduce noise, so the total conversion time for each input is
11.38 ms.
Measurements on the remote temperature (D1 and D2) inputs
take 2.13 ms. These are also measured 16 times and are
averaged, so the total conversion time for a remote temperature
input is 34.13 ms.
Table 6. A-to-D Output Code vs. VIN 1 VBAT is not accurate for voltages under 1.5 V (see Figure 15).
Voltage Measurement Inputs
The internal structure for all the analog inputs is shown in
Figure 27. Each input circuit consists of an input protection
diode, an attenuator, plus a capacitor to form a first-order low-
pass filter that gives each voltage measurement input immunity
to high frequency noise. The −12 V input also has a resistor
connected to the on-chip reference to offset the negative voltage
range so that it is always positive and can be handled by the
ADC. This allows most popular power supply voltages to be
monitored directly by the ADM1026 without requiring any
additional resistor scaling.
21.9k+VCCP
9.3pF
VREF
17.5kΩ
114.3kΩ–12V
49.5kΩ
VBAT
AIN0– AIN5
(0V– 3V)
21.9kΩ
AIN6– AIN9
(0V– 2.5V)4.6pF
52.5kΩ
83.5kΩ+5V
113.5kΩ+12V
02657-A
Figure 27. Voltage Measurement Inputs
Setting Other Input Ranges
AIN0 to AIN9 can easily be scaled to voltages other than 2.5 V or
3 V. If the input voltage range is zero to some positive voltage, all
that is required is an input attenuator, as shown in Figure 28.
VINAIN(0–9)
02657-A
However, when scaling AIN0 to AIN5, it should be noted that
these inputs already have an on-chip attenuator, because their
primary function is to monitor SCSI termination voltages. This
attenuator loads any external attenuator. The input resistance of
the on-chip attenuator can be between 100 kΩ and 200 kΩ. For
this tolerance not to affect the accuracy, the output resistance
of the external attenuator should be very much lower than
this, that is, 1 kΩ in order to add not more than 1% to the
total unadjusted error (TUE). Alternatively, the input can be
buffered using an op amp. ()IN5IN0AAtofor0.3.3= ()IN9IN6AAtofor5.2.2=
Negative and bipolar input ranges can be accommodated by
using a positive reference voltage to offset the input voltage
range so that it is always positive. To monitor a negative input
voltage, an attenuator can be used as shown in Figure 29.
VIN
02657-A
Figure 29. Scaling and Offsetting AIN0 − AIN9 for Negative Inputs
This offsets the negative voltage so that the ADC always sees a
positive voltage. R1 and R2 are chosen so that the ADC input
voltage is zero when the negative input voltage is at its
maximum (most negative) value, that is: −=
This is a simple and low cost solution, but note the following: Because the input signal is offset but not inverted, the input
range is transposed. An increase in the magnitude of the
negative voltage (going more negative) causes the input
voltage to fall and give a lower output code from the ADC.
Conversely, a decrease in the magnitude of the negative
voltage causes the ADC code to increase. The maximum
negative voltage corresponds to zero output from the ADC.
This means that the upper and lower limits are transposed. For the ADC output to be full scale when the negative
voltage is zero, VOS must be greater than the full-scale
voltage of the ADC, because VOS is attenuated by R1 and
R2. If VOS is equal to or less than the full-scale voltage of
the ADC, the input range is bipolar but not necessarily
symmetrical.
Symmetrical bipolar input ranges can be accommodated easily
by making VOS equal to the full-scale voltage of the analog input,
and by adding a third resistor to set the positive full scale.
VIN
AIN(0–9)
+VOS
02657-A
Figure 30. Scaling and Offsetting AIN0 − AIN9 for Bipolar Inputs −=
Note that R3 has no effect as the input voltage at the device pin
is zero when VIN = negative full scale. ()IN5IN0AAtofor0.3.3−= ()IN9IN6AAtofor5.2.2−=
Also, note that R2 has no effect as the input voltage at the device
pin is equal to VOS when VIN = positive full scale.
Battery Measurement Input (VBAT)
The VBAT input allows the condition of a CMOS backup battery
to be monitored. This is typically a lithium coin cell such as a
CR2032. The VBAT input is accurate only for voltages greater
than 1.5 V (see Figure 15). Typically, the battery in a system is
required to keep some device powered on when the system is in
a powered-off state. The VBAT measurement input is specially
designed to minimize battery drain. To reduce current drain
from the battery, the lower resistor of the VBAT attenuator is not
connected, except whenever a VBAT measurement is being made.
The total current drain on the VBAT pin is 80 nA typical (for a
maximum VBAT voltage = 4 V), so a CR2032 CMOS battery
functions in a system in excess of the expected 10 years. Note
that when a VBAT measurement is not being made, the current
drain is reduced to 6 nA typical. Under normal voltage meas-
urement operating conditions, all measurements are made in a
round-robin format, and each reading is actually the result of
16 digitally averaged measurements. However, averaging is not
carried out on the VBAT measurement to reduce measurement
time and therefore reduce the current drain from the battery.
The VBAT current drain when a measurement is being made is
calculated by
PULSEBATVI×=Ωk100
For example, when VBAT = 3 V, n78ms273
711k1003=×=I
where TPULSE = VBAT measurement time (711 µs typical),
TPERIOD = time to measure all analog inputs (273 ms typical),
and VBAT input battery protection.
VBAT Input Battery Protection
In addition to minimizing battery current drain, the VBAT
measurement circuitry was specifically designed with battery
protection in mind. Internal circuitry prevents the battery from
being back-biased by the ADM1026 supply or through any
other path under normal operating conditions. In the unlikely
event of a catastrophic ADM1026 failure, the ADM1026
includes a second level of battery protection including a series
3 kΩ resistor to limit current to the battery, as recommended by
UL. Thus, it is not necessary to add a series resistor between the
battery and the VBAT input; the battery can be connected directly
to the VBAT input to improve voltage measurement accuracy.
VBAT
DIGITALCONTROL49.5kΩ
82.7kΩ
3kΩ
02657-A
Figure 31. Equivalent VBAT Input Protection Circuit
Reference Output (VREF)
The ADM1026 offers an on-chip reference voltage (Pin 24) that
can be used to provide a 1.82 V or 2.5 V reference voltage out-
put. This output is buffered and specified to sink or source a
load current of 2 mA. The reference voltage outputs 1.82 V if
Bit 2 of Configuration Register 3 (Address 07h) is 0; it outputs
2.5 V when this bit is set to 1. This voltage reference output can
be used to provide a stable reference voltage to external cir-
cuitry such as LDOs. The load regulation of the VREF output is
typically 0.15% for a sink current of 2 mA and 0.15% for 2 mA
source current. There may be some ripple present on the VREF
output that requires filtering (±4 m VMAX). Figure 32 shows the
recommended circuitry for the VREF output for loads less than
2 mA. For loads in excess of 2 mA, external circuitry, such as
that shown in Figure 33, can be used to buffer the VREF output.
VREF
-033
If the VREF output is not being used, it should be left uncon-
nected. Do not connect VREF to GND using a capacitor. The
internal output buffer on the voltage reference is capacitively
loaded, which can cause the voltage reference to oscillate. This
affects temperature readings reported back by the ADM1026.
The recommended interface circuit for the VREF output is shown
in Figure 33.
0.1µF
+12V
VREF
02657-A
Figure 33. VREF Interface Circuit for VREF Loads > 2 mA
TEMPERATURE MEASUREMENT SYSTEM
Local Temperature Measurement
The ADM1026 contains an on-chip band gap temperature
sensor whose output is digitized by the on-chip ADC. The
temperature data is stored in the local temperature value
register (Address 1Fh). As both positive and negative temper-
atures can be measured, the temperature data is stored in twos
complement format, as shown in Table 7. Theoretically, the
temperature sensor and ADC can measure temperatures from
−128°C to +127°C with a resolution of 1°C. Temperatures below
TMIN and above TMAX are outside the operating temperature
range of the device, however, so local temperature measure-
ments outside this range are not possible. Temperature
measurement from −128°C to +127°C is possible using a
remote sensor.
Remote Temperature Measurement
The ADM1026 can measure the temperature of two remote
diode sensors, or diode-connected transistors, connected to
Pins 25 and 26, or 27 and 28.
Pins 25 and 26 are a dedicated temperature input channel.
Pins 27 and 28 can be configured to measure a diode sensor by
clearing Bit 3 of Configuration Register 1 (Address 00h) to 0.
If this bit is 1, then Pins 27 and 28 are AIN8 and AIN9.
The forward voltage of a diode or diode-connected transistor,
operated at a constant current, exhibits a negative temperature
coefficient of about −2 mV/°C. Unfortunately, the absolute
value of Vbe varies from device to device, and individual
calibration is required to null this out, so the technique is
unsuitable for mass production.
The technique used in the ADM1026 is to measure the change
in Vbe when the device is operated at two different currents,
given by NnqKVbelogΔ××=
where K is Boltzmann’s constant, q is the charge on the carrier,
T is the absolute temperature in Kelvins, and N is the ratio of
the two currents.
Figure 34 shows the input signal conditioning used to measure
the output of a remote temperature sensor. This figure shows
the external sensor as a substrate transistor provided for
temperature monitoring on some microprocessors, but it could
equally well be a discrete transistor such as a 2N3904.
If a discrete transistor is used, the collector is not grounded
and should be linked to the base. If a PNP transistor is used,
the base is connected to the D− input and the emitter to the
D+ input. If an NPN transistor is used, the emitter is connected
to the D− input and the base to the D+ input.
To prevent ground noise from interfering with the measure-
ment, the more negative terminal of the sensor is not referenced
to ground but is biased above ground by an internal diode at the
D− input.
To measure ΔVbe, the sensor is switched between operating
currents of I and N × I. The resulting waveform is passed
through a 65 kHz low-pass filter to remove noise, and to a
chopper-stabilized amplifier that performs the functions of
amplification and rectification of the waveform to produce a
DC voltage proportional to ΔVbe. This voltage is measured
by the ADC to give a temperature output in 8-bit, twos
complement format. To further reduce the effects of noise,
digital filtering is performed by averaging the results of 16
measurement cycles. A remote temperature measurement
takes nominally 2.14 ms.
REMOTE
SENSING
VOUT+
TO ADC
VOUT–
CAPACITOR C1 IS OPTIONAL. IT IS ONLY NECESSARY IN NOISY ENVIRONMENTS.
C1 = 2.2nF TYPICAL, 3nF MAX.
02657-A
Figure 34. Signal Conditioning for Remote Diode Temperature Sensors
The results of external temperature measurements are stored in
8-bit, twos complement format, as illustrated in Table 7.
Table 7. Temperature Data Format
Layout Considerations
Digital boards can be electrically noisy environments. Take
these precautions to protect the analog inputs from noise,
particularly when measuring the very small voltages from a
remote diode sensor. Place the ADM1026 as close as possible to the remote
sensing diode. Provided that the worst noise sources such
as clock generators, data/address buses, and CRTs are
avoided, this distance can be 4 to 8 inches. Route the D+ and D− tracks close together, in parallel, with
grounded guard tracks on each side. Provide a ground
plane under the tracks if possible. Use wide tracks to minimize inductance and reduce noise
pickup. A 10 mil track minimum width and spacing is
recommended.
GND
GND
02657-A
Figure 35. Arrangement of Signal Tracks Try to minimize the number of copper/solder joints, which
can cause thermocouple effects. Where copper/solder
joints are used, make sure that they are in both the D+ and
D− paths and are at the same temperature. Thermocouple effects should not be a major problem
because 1°C corresponds to about 240 µV, and
thermocouple voltages are about 3 µV/°C of temperature
difference. Unless there are two thermocouples with a big
temperature differential between them, thermocouple
voltages should be much less than 200 mV. Place a 0.1 µF bypass capacitor close to the ADM1026. If the distance to the remote sensor is more than eight
inches, the use of twisted-pair cable is recommended.
This works from about 6 to 12 feet. For very long distances (up to 100 feet), use shielded
twisted pair such as Belden #8451 microphone cable.
Connect the twisted pair to D+ and D− and the shield to
GND close to the ADM1026. Leave the remote end of the
shield unconnected to avoid ground loops.
Because the measurement technique uses switched current
sources, excessive cable and/or filter capacitance can affect the
measurement. When using long cables, the filter capacitor may
be reduced or removed. Cable resistance can also introduce
errors. A 1 Ω series resistance introduces about 0.5°C error.
Limit Values
Limit values for analog measurements are stored in the appropri
ate limit registers. In the case of voltage measurements, high and
low limits can be stored so that an interrupt request is generated
if the measured value goes above or below acceptable values. In
the case of temperature, a hot temperature or high limit can be
programmed, and a hot temperature hysteresis or low limit can
be programmed, which is usually some degrees lower. This can
be useful because it allows the system to be shut down when the
hot limit is exceeded, and restarted automatically when it has
cooled down to a safe temperature.
Analog Monitoring Cycle Time
The analog monitoring cycle begins when a 1 is written to the
start bit (Bit 0), and a 0 to the INT_Clear bit (Bit 2) of the con-
figuration register. INT_Enable (Bit 1) should be set to 1 to
enable the INToutput. The ADC measures each analog input in
turn, starting with Remote Temperature Channel 1 and ending
with local temperature. As each measurement is completed, the
result is automatically stored in the appropriate value register.
This round-robin monitoring cycle continues until it is disabled
by writing a 0 to Bit 0 of the configuration register. Because the
ADC is typically left to free-run in this way, the most recently
measured value of any input can be read out at any time.
For applications where the monitoring cycle time is important,
it can easily be calculated.
The total number of channels measured is Five dedicated supply voltage inputs Ten general-purpose analog inputs 3.3 V MAIN 3.3 V STBY Local temperature Two remote temperature
Pins 28 and 27 are measured both as analog inputs AIN8/AIN9 and
as remote temperature input D2+/D2−, irrespective of which
configuration is selected for these pins.
If Pins 28 and 27 are configured as AIN8/AIN9, the measurements
for these channels are stored in Registers 27h and 29h, and the
invalid temperature measurement is discarded. On the other
hand, if Pins 28 and 27 are configured as D2+/D2−, the temper-
ature measurement is stored in Register 29h, and there is no
valid result in Register 27h.
As mentioned previously, the ADC performs a conversion every
711 µs on the analog and local temperature inputs and every
2.13 ms on the remote temperature inputs. Each input is
measured 16 times and averaged to reduce noise.
The total monitoring cycle time for voltage and temperature
inputs is therefore nominally
The ADC uses the internal 22.5 kHz clock, which has a toler-
ance of ±6%, so the worst-case monitoring cycle time is 290 ms.
The fan speed measurement uses a completely separate
monitoring loop, as described later.
Input Safety
Scaling of the analog inputs is performed on-chip, so external
attenuators are typically not required. However, because the
power supply voltages appear directly at the pins, it is advisable
to add small external resistors (that is, 500 Ω) in series with the
supply traces to the chip to prevent damaging the traces or
power supplies should an accidental short such as a probe
connect two power supplies together.
Because the resistors form part of the input attenuators, they
affect the accuracy of the analog measurement if their value
is too high. The worst such accident would be connecting
−12 V to +12 V where there is a total of 24 V difference. With
the series resistors, this would draw a maximum current of
approximately 24 mA.
ANALOG OUTPUT
The ADM1026 has a single analog output from an unsigned
8-bit DAC that produces 0 V to 2.5 V (independent of the refer-
ence voltage setting). The input data for this DAC is contained
in the DAC control register (Address 04h). The DAC control
register defaults to FFh during a power-on reset, which pro-
duces maximum fan speed. The analog output may be amplified
and buffered with external circuitry such as an op amp and a
transistor to provide fan speed control. During automatic fan
speed control, described later, the four MSBs of this register set
the minimum fan speed.
Suitable fan drive circuits are shown in Figure 36 through
Figure 40. When using any of these circuits, note the following: All of these circuits provide an output range from 0 V to
almost +12 V, apart from Figure 36, which loses the base-
emitter voltage drop of Q1 due to the emitter-follower
configuration. To amplify the 2.5 V range of the analog output up to 12 V,
the gain of these circuits needs to be about 4.8. Take care when choosing the op amp to ensure that its
input common-mode range and output voltage swing are
suitable. The op amp may be powered from the +12 V rail alone
or from ±12 V. If it is powered from +12 V, the input
common-mode range should include ground to accom-
modate the minimum output voltage of the DAC, and the
output voltage should swing below 0.6 V to ensure that the
transistor can be turned fully off. If the op amp is powered from −12 V, precautions such as
a clamp diode to ground may be needed to prevent the
base-emitter junction of the output transistor being
In all these circuits, the output transistor must have an ICMAX greater than the maximum fan current, and be
capable of dissipating power due to the voltage dropped
across it when the fan is not operating at full speed. If the fan motor produces a large back EMF when switched
off, it may be necessary to add clamp diodes to protect the
output transistors in the event that the output goes from
full scale to zero very quickly.
DAC
02657-A
Figure 36. Fan Drive Circuit with Op Amp and Emitter-Follower
DAC
02657-A
Figure 37. Fan Drive Circuit with Op Amp and PNP Transistor
DAC
Q1/Q2
MBT3904DUAL
DAC
100kΩ02657-A
Figure 39. Discrete Fan Drive Circuit with P-Channel MOSFET, Single Supply
DAC
–12V02657-A
Figure 40. Discrete Fan Drive Circuit with P-Channel MOSFET, Dual Supply
PWM Output Fan speed may also be controlled using pulse width modulation
(PWM). The PWM output (Pin 18) produces a pulsed output
with a frequency of approximately 75 Hz and a duty cycle
defined by the contents of the PWM control register (Address
05h). During automatic fan speed control, described below, the
four MSBs of this register set the minimum fan speed.
The open drain PWM output must be amplified and buffered
to drive the fans. The PWM output is intended to be used with
an NMOS driver, but may be inverted by setting Bit 1 of Test
Register 1 (Address 14h) if using PMOS drivers. Figure 41
shows how a fan may be driven under PWM control using an
N-channel MOSFET.
PWM
3.3V
10kΩ TYP
5V OR 12V
FAN-041
Automatic Fan Speed Control The ADM1026 offers a simple method of controlling fan speed
according to temperature without intervention from the host
processor. Monitoring must be enabled by setting Bit 0 of
Configuration Register 1 (Address 00h), to enable automatic fan
speed control. Automatic fan speed control can be applied to the
DAC output, the PWM output, or both, by setting Bit 5 and/or
Bit 6 of Configuration Register 1.
The TMIN registers (Addresses 10h to 12h) contain minimum
temperature values for the three temperature channels (on-chip
sensor and two remote diodes). This is the temperature at which
a fan starts to operate when the temperature sensed by the
controlling sensor exceeds TMIN. TMIN can be the same or
different for all three channels. TMIN is set by writing a twos
complement temperature value to the TMIN registers. If any
sensor channel is not required for automatic fan speed control,
TMIN for that channel should be set to 127°C (01111111).
In automatic fan speed control mode, (as shown Figure 42 and
Figure 43) the four MSBs of the DAC control register (Address
04h) and PWM control register (Address 05h) set the minimum
values for the DAC and PWM outputs. Note that, if both DAC
control and PWM control are enabled (Bits 5 and 6 of
Configuration Register 1 = 1), the four MSBs of the DAC
control register (Address 04h) define the minimum fan speed
values for both the DAC and PWM outputs. The value in the
PWM control register (Address 05h) has no effect.
Minimum DAC Code DACMIN = 16 × D
2565.2CodeVoltageOutputDAC×=
Minimum PWM Duty Cycle PWMMIN = 6.67 × D
where D is the decimal equivalent of Bits 7 to 4 of the register.
When the temperature measured by any of the sensors exceeds
the corresponding TMIN, the fan is spun up for 2 seconds with
the fan drive set to maximum (full scale from the DAC or 100%
PWM duty cycle). The fan speed is then set to the minimum as
previously defined. As the temperature increases, the fan drive
increases until the temperature reaches TMIN + 20°C.
The fan drive at any temperature up to 20°C above TMIN is
given by 20100MINACTUAL
MINMINTTPWMPWMPWM−×−+=
or 20240MINACTUAL
MINMINTTDACDACDAC−×−+=
For simplicity of the automatic fan speed algorithm, the DAC
output jumps to full scale. To ensure that the maximum cooling
capacity is always available, the fan drive is always set by the
sensor channel demanding the highest fan speed.
If the temperature falls, the fan does not turn off until the
temperature measured by all three temperature sensors has
fallen to their corresponding TMIN − 4°C. This prevents the fan
from cycling on and off continuously when the temperature is
close to TMIN.
Whenever a fan starts or stops during automatic fan speed
control, a one-off interrupt is generated at the INT output. This
is described in more detail in the section on the ADM1026
Interrupt Structure.
PWM
MIN
TEMPERATURE
TMIN
100%
TMIN– 4°CTMIN + 20°C02657-A
Figure 42. Automatic PWM Fan Control Transfer Function
DAC
MIN
TEMPERATURE
TMIN
TMIN– 4°CTMIN + 20°C02657-A
Figure 43. Automatic DAC Fan Control Transfer Function
Fan Inputs Pins 3 to 6 and 9 to 12 may be configured as fan speed
measuring inputs by clearing the corresponding bit(s) of
Configuration Register 2 (Address 01h), or as general-purpose
logic inputs/outputs by setting bits in this register. The power-
Signal conditioning in the ADM1026 accommodates the slow
rise and fall times typical of fan tachometer outputs. The fan
tach inputs have internal 10 kΩ pull-up resistors to 3.3 V STBY.
In the event that these inputs are supplied from fan outputs that
exceed the supply, either resistive attenuation of the fan signal
or diode clamping must be included to keep inputs within an
acceptable range. Figure 44 through Figure 47 show circuits for
common fan tach outputs.
If the fan tach output is open-drain or has a resistive pull-up to
VCC, then it can be connected directly to the fan input, as shown
in Figure 44.
02657-A
Figure 44. Fan with Tach Pull-Up to +VCC
If the fan output has a resistive pull-up to +12 V (or other
voltage greater than 3.3 V STBY), the fan output can be clamped
with a Zener diode, as shown in Figure 45. The Zener voltage
should be chosen so that it is greater than VIH but less than 3.3 V
STBY, allowing for the voltage tolerance of the Zener.
FAN(0–7)
*CHOOSE ZD1 VOLTAGE APPROXIMATELY 0.8×VCC
ZD1*ZENER02657-A
Figure 45. Fan with Tach Pull-Up to Voltage > VCC (e.g. 12 V),
Clamped with Zener Diode
If the fan has a strong pull-up (less than 1 kΩ) to +12 V, or a
totem pole output, a series resistor can be added to limit the
Zener current, as shown in Figure 46. Alternatively, a resistive
attenuator may be used, as shown in Figure 47.
R1 and R2 should be chosen such that STBYV3.3PULLUPV2V<++×
FAN(0–7)
VCC
*CHOOSE ZD1 VOLTAGE APPROXIMATELY 0.8×VCC
ZD1*
ZENER
10kΩ
02657-A
Figure 46. Fan with Strong Tach Pull-Up to > VCC or Totem Pole Output,
Clamped with Zener and Resistor
FAN(0–7)
R1*
*SEE TEXT02657-A
Figure 47. Fan with Strong Tach Pull-Up to >VCC or Totem Pole Output,
Attenuated with R1/R2
FAN SPEED MEASUREMENT
The fan counter does not count the fan tach output pulses
directly because the fan speed may be less than 1000 RPM and
it would take several seconds to accumulate a reasonably large
and accurate count. Instead, the period of the fan revolution is
measured by gating an on-chip 22.5 kHz oscillator into the
input of an 8-bit counter for two periods of the fan tach output,
as shown in Figure 48, so the accumulated count is actually
proportional to the fan tach period and inversely proportional
to the fan speed.
22.5kHzCLOCK
CONFIGURATIONREG. 1 BIT 0
FAN0INPUT
FAN0MEASUREMENT
PERIOD
FAN1MEASUREMENT
PERIOD
START OFMONITORING
CYCLE
FAN1
INPUT234
02657-A-048
Figure 48. Fan Speed Measurement
The monitoring cycle begins when a 1 is written to the monitor
bit (Bit 0 of Configuration Register 1). The INT_Enable (Bit 1)
should be set to 1 to enable the INT output.
The fan speed counter starts counting as soon as the fan
channel has been switched to. If the fan tach count reaches 0xFF,
the fan has failed or is not connected. If a fan is connected and
running, the counter is reset on the second tach rising edge, and
oscillator pulses are actually counted from the second rising
tach edge to the fourth rising edge. The measurement then
switches to the next fan channel. Here again, the counter begins
counting and is reset on the second tach rising edge, and
oscillator pulses are counted from the second rising edge to the
fourth rising edge. This is repeated for the other six fan
channels.
Note that fan speed measurement does not occur until 1.8
seconds after the monitor bit has been set. This is to allow the
fans adequate time to spin up. Otherwise, the ADM1026 could
generate false fan failure interrupts. During the 1.8 second fan
spin-up time, all fan tach registers read 0x00.
To accommodate fans of different speed and/or different
numbers of output pulses per revolution, a prescaler (divisor) of
1, 2, 4, or 8 may be added before the counter. Divisor values for
Fans 0 to 3 are contained in the Fan 0–3 divisor register
(Address 02h) and those for Fans 4 to 7 in the Fan 4–7 divisor
register (Address 03h). The default value is 2, which gives a
count of 153 for a fan running at 4400 RPM producing two
output pulses per revolution. The count is calculated by the
equation:
DivisorRPMCount××=60105.223
For constant-speed fans, fan failure is typically considered to
have occurred when the speed drops below 70% of nominal,
corresponding to a count of 219. Full scale (255) is reached if
the fan speed fell to 60% of its nominal value. For temperature-
controlled, variable-speed fans, the situation is different.
Table 8 shows the relationship between fan speed and time per
revolution at 60%, 70%, and 100% of nominal RPM for fan
speeds of 1100, 2200, 4400, and 8800 RPM, and the divisor that
would be used for each of these fans, based on two tach pulses
per revolution.
Limit Values
Fans generally do not over-speed if run from the correct
voltage, so the failure condition of interest is under speed due to
electrical or mechanical failure. For this reason, only low speed
limits are programmed into the limit registers for the fans. It
should be noted that because fan period rather than speed is
being measured, a fan failure interrupt occurs when the
measurement exceeds the limit value.
Fan Monitoring Cycle Time
The fan speeds are measured in sequence from 0 to 7. The
monitoring cycle time depends on the fan speed, the number
of tach output pulses per revolution, and the number of fans
being monitored.
If a fan is stopped or running so slowly that the fan speed
counter reaches 255 before the second tach pulse after initializa-
tion, or before the fourth tach pulse during measurement, the
measurement is terminated. This also occurs if an input is con-
figured as GPIO instead of fan. Any channels connected in this
manner time out after 255 clock pulses.
The worst-case measurement time for a fan-configured channel
occurs when the counter reaches 254 from start to the second
tach pulse and reaches 255 after the second tach pulse. Taking
into account the tolerance of the oscillator frequency, the worst-
case measurement time is
509 × D × 0.05 ms
where:
509 is the total number of clock pulses.
D is the divisor: 1, 2, 4, or 8.
0.05 ms is the worst-case oscillator period in ms.
The worst-case fan monitoring cycle time is the sum of the
worst-case measurement time for each fan.
Although the fan monitoring cycle and the analog input
monitoring cycle are started together, they are not synchronized
in any other way.
Table 8. Fan Speeds and Divisors
Chassis Intrusion Input
The chassis intrusion input is an active high input intended for
detection and signaling of unauthorized tampering with the
system. When this input goes high, the event is latched in Bit 6
of Status Register 4, and an interrupt is generated. The bit
remains set until cleared by writing a 1 to CI clear, Bit 1 of
Configuration Register 3 (05h), as long as battery voltage is
connected to the VBAT input. The CI clear bit itself is cleared by
writing a 0 to it.
The CI input detects chassis intrusion events even when the
ADM1026 is powered off (provided battery voltage is applied to
VBAT) but does not immediately generate an interrupt. Once a
chassis intrusion event is detected and latched, an interrupt is
generated when the system is powered on.
The actual detection of chassis intrusion is performed by an
external circuit that detects, for example, when the cover has
been removed. A wide variety of techniques may be used for the
detection, for example: A microswitch that opens or closes when the cover is
removed. A reed switch operated by magnet fixed to the cover. A hall-effect switch operated by magnet fixed to the cover. A phototransistor that detects light when the cover is
removed.
The chassis intrusion input can also be used for other types of
alarm input. Figure 49 shows a temperature alarm circuit using
an AD22105 temperature switch sensor. This produces a low-
going output when the preset temperature is exceeded, so the
output is inverted by Q1 to make it compatible with the CI
input. Q1 can be almost any small-signal NPN transistor, or a
TTL or CMOS inverter gate may be used if one is available.
See the AD22105 data sheet on the Analog Devices, Inc.
website () for information on selecting RSET.
RSET
02657-A
Figure 49. Using the CI Input with a Temperature Sensor
General-Purpose I/O Pins (Open Drain)
The ADM1026 has eight pins that are dedicated to general-
purpose logic input/output (Pins 1, 2, and 43 to 48), eight pins
that can be configured as general-purpose logic pins or fan
speed inputs (Pins 3 to 6, and 9 to 12), and one pin that can
be configured as GPIO16 or the bidirectional THERM pin
(Pin 42). The GPIO/FAN pins are configured as general-
purpose logic pins by setting Bits 0 to 7 of Configuration
Register 2 (Address 01h). Pin 42 is configured as GPIO16 by
setting Bit 0 of Configuration Register 3, or as the THERM
function by clearing this bit.
Each GPIO pin has four data bits associated with it, two bits in
one of the GPIO configuration registers (Addresses 08h to 0Bh),
one in the GPIO status registers (Addresses 24h and 25h), and
one in the GPIO mask registers (Addresses 1Ch and 1Dh)
Setting a direction bit = 1 in one of the GPIO configuration
registers makes the corresponding GPIO pin an output.
Clearing the direction bit to 0 makes it an input.
Setting a polarity bit = 1 in one of the GPIO configuration
registers makes the corresponding GPIO pin active high.
Clearing the polarity bit to 0 makes it active low.
When a GPIO pin is configured as an input, the corresponding
bit in one of the GPIO status registers is read-only, and is set
when the input is asserted (“asserted” may be high or low
depending on the setting of the polarity bit).
When a GPIO pin is configured as an output, the corresponding
bit in one of the GPIO status registers becomes read/write.
Setting this bit then asserts the GPIO output. (Here again,
“asserted” may be high or low depending on the setting of the
polarity bit.)
The effect of a GPIO status register bit on the INT output can
be masked out by setting the corresponding bit in one of the
GPIO mask registers. When the pin is configured as an output,
this bit is automatically masked to prevent the data written to
the status bit from causing an interrupt, with the exception of
GPIO16, which must be masked manually by setting Bit 7 of
Mask Register 4 (Reg 1Bh).
When configured as inputs, the GPIO pins may be connected to
external interrupt sources such as temperature sensors with
digital output. Another application of the GPIO pins would be
to monitor a processor’s voltage ID code (VID code).
ADM1026 Interrupt Structure
The Interrupt Structure of the ADM1026 is shown in Figure 53.
Interrupts can come from a number of sources, which are com-
bined to form a common INT output. When INT is asserted,
this output pulls low. The INT pin has an internal, 100 kΩ
pull-up resistor.
Analog/Temperature Inputs
As each analog measurement value is obtained and stored in the
appropriate value register, the value and the limits from the
corresponding limit registers are fed to the high and low limit
comparators. The device performs greater than comparisons to
the high limits. An out-of-limit is also generated if a result is
less than or equal to a low limit. The result of each comparison
(1 = out of limit, 0 = in limit) is routed to the corresponding
bit input of Interrupt Status Register 1, 2, or 4 via a data
demultiplexer, and used to set that bit high or low as appro-
priate. Status bits are self-clearing. If a bit in a status register is
set due to an out-of-limit measurement, it continues to cause
INT to be asserted as long as it remains set, as described later.
However, if a subsequent measurement is in limit, it is reset and
does not cause INT to be reasserted. Status bits are unaffected
by clearing the interrupt.
Interrupt Mask Registers 1, 2, and 4 have bits corresponding to
each of the interrupt status register bits. Setting an interrupt
mask bit high conceals an asserted status bit from display on
Interrupt Pin 17. Setting an interrupt mask bit low allows the
corresponding status bit to be asserted and displayed on Pin 17.
After mask gating, the status bits are all OR’ed together to
produce the analog and fan interrupt that is used to set a latch.
The output of this latch is OR’ed with other interrupt sources to
produce the INT output. This pulls low if any unmasked status
bit goes high, that is, when any measured value goes out of limit.
When an INT output caused by an out-of-limit analog/
temperature measurement is cleared by one of the methods
described later, the latch is reset. It is not set again, and INT is
not reasserted until after two local temperature measure-ments
have been taken, even if the status bit remains set or a new
analog/temperature event occurs, as shown in Figure 50. This
delay corresponds to almost two monitoring cycles, and is about
530 ms. However, interrupts from other sources such as a fan or
GPIO can still occur. This is illustrated in Figure 51.
MONITORING
CYCLE
OUT-OF-LIMITMEASUREMENT
INT
LOCAL
TEMPERATUREMEASUREMENT
START OF ANALOG
MONITORINGCYCLE
FULL MONITORING CYCLE = 273ms
TEMPERATURE
LOCAL
MEASUREMENT
02657-A
Figure 50. Delay After Clearing INT Before Reassertion
START OF ANALOG
MONITORING CYCLE
OUT-OF-LIMIT
MEASUREMENT
LOCAL TEMPEREATURE
MEASUREMENT
START OF ANALOG
MONITORING CYCLE
LOCAL TEMPERATURE
MEASUREMENT
START OF ANALOG
MONITORING CYCLE
NEWINT
FROM FANNEWINT
FROM GPIO
INT
INT
CLEARED
02657-A
Figure 51. Other Interrupt Sources Can Reassert INT Immediately
