ADM1026 ,Highly Integrated Thermal and System Monitor for Servers/High Reliability SystemsSPECIFICATIONSA MIN MAX CC MIN MAXParameter Min Typ Max Test Conditions/Comments UnitPOWER SUPPLYSu ..
ADM1026 ,Highly Integrated Thermal and System Monitor for Servers/High Reliability Systems3ADM1026Table 3. PIN ASSIGNMENTPin No. Mnemonic Type Description17 INT Digital Output Interrupt Req ..
ADM1026JST ,Complete Thermal and System Management ControllerSPECIFICATIONSParameter Min Typ Max Units Test Conditions/CommentsPOWER SUPPLYSupply Voltage, 3.3V ..
ADM1026JST-REEL ,Highly Integrated Thermal and System Monitor for Servers/High Reliability SystemsCharacteristics ........ 5 Analog Output.... 22 ESD Caution. 5 Fan Speed Measurement ..... 25 Pin C ..
ADM1026JST-REEL7 ,Highly Integrated Thermal and System Monitor for Servers/High Reliability SystemsCharacteristics 8 NAND Tree Tests 31 Product Description........ 10 Using the ADM1026 ... 33 Funct ..
ADM1026JSTZ ,Highly Integrated Thermal and System Monitor for Servers/High Reliability SystemsFEATURES Full SMBus 1.1 support includes packet error checking (PEC) Chassis intrusion detection Up ..
AH11 , High Dynamic Range Dual Amplifier
AH1-1 , High Dynamic Range Amplifier
AH110-89 , 0.2 Watt, High Linearity InGaP HBT Amplifier
AH114-89G , ¼ Watt, High Linearity InGaP HBT Amplifier
AH115-S8 , 1/2 Watt, High Linearity InGaP HBT Amplifier
AH116-S8 , 1/2 Watt, High Linearity InGaP HBT Amplifier
ADM1026
Highly Integrated Thermal and System Monitor for Servers/High Reliability Systems
REV.0
Complete Thermal System
Management Controller
FEATURES
Up to 19 Analog Measurement Channels
(Including Internal Measurements)
Up to 8 Fan Speed Measurement Channels
Up to 17 General Purpose Logic I/O Pins
Remote Temperature Measurement with Remote Diode
(Two Channels)
On-Chip Temperature Sensor
Analog and PWM Fan Speed Control Outputs
2-Wire Serial System Management Bus (SMBus)
8 kB On-Chip EEPROM
FUNCTIONAL BLOCK DIAGRAM
+VBAT (0 – +4.0V)
+5 VIN (0 – +6.66V)
–12 VIN (0 – –16V)
+12 VIN (0 – +16V)
+VCCPIN (0 – +3V)
AIN0 (0 – +3V)
AIN1 (0 – +3V)
AIN2 (0 – +3V)
AIN3 (0 – +3V)
AIN4 (0 – +3V)
AIN5 (0 – +3V)
AIN6 (0 – +2.5V)
AIN7 (0 – +2.5V)
D2+/AIN8 (0 – +2.5V)
D2–/AIN9 (0 – +2.5V)
D1+
D1–/NTESTIN
DGND
DAC
AGNDVREF (1.82V OR 2.5V)
SCLSDA3.3V MAIN
ADD/
NTESTOUT
FAN 7/GPIO7
FAN 6/GPIO6
FAN 5GPIO5
FAN 4/GPIO4
FAN 3/GPIO3
FAN 2/GPIO2
FAN 1/GPIO1
FAN 0/GPIO0
GPIO15
GPIO14
GPIO13
GPIO12
GPIO11
GPIO10
GPIO9
GPIO8
PWM
3.3V STBY
GPIO16/ THERM
INT
RESETMAIN
RESETSTBY
Full SMBus 1.1 Support Including Packet Error
Checking (PEC)
Chassis Intrusion Detection
Interrupt Output (SMBAlert)
Reset Input, Reset Outputs
Thermal Interrupt (THERM) Output
Limit Comparison of All Monitored Values
APPLICATIONS
Network Servers and Personal Computers
Telecommunications Equipment
Test Equipment and Measuring Instruments
ADM1026–SPECIFICATIONS(TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted.)
1, 2, 3ANALOG-TO-DIGITAL CONVERTER (INCLUDING MUX AND ATTENUATORS)
ANALOG OUTPUT (DAC)
ADM1026SERIAL BUS DIGITAL INPUTS (SCL, SDA)
RESETMAIN, RESETSTBY
NOTES
1All voltages are measured with respect to GND, unless otherwise specified.
2Typicals are at TA = 25°C and represent most likely parametric norm. Shutdown current typ is measured with VCC = 3.3V.
3Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge and VIH = 2.1 V for a rising edge.
4TUE (Total Unadjusted Error) includes Offset, Gain, and Linearity errors of the ADC, multiplexer, and on-chip input attenuators. VBAT input is only linear for VBAT
voltages greater than 1.5 V.
5Total analog monitoring cycle time is nominally 273 ms, made up of 18�11.38 ms measurements on analog input and internal temperature channels, and�34.13ms measurements on external temperature channels.
6The total fan count is based on two pulses per revolution of the fan tachometer output. The total fan monitoring time depends on the number of fans connected and
the fan speed. See Fan Speed Monitoring section for more details.
7ADD is a three-state input that may be pulled high, low, or left open-circuit.
8Logic inputs will accept input high voltages up to 5 V even when device is operating at supply voltages below 5 V.
9Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 method A117, and measured at –40°C, 25°C, and 85°C. Typical endurance at 25°C is 700,000 cycles.
10Retention lifetime equivalent at junction temperature (TJ) = 55°C as per JEDEC Std. 22 method A117. Retention lifetime based on an activation energy of 0.6 V
will derate with junction temperature as shown in Figure 2.
Specifications subject to change without notice.
ADM1026
ABSOLUTE MAXIMUM RATINGS*Positive Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . 6.5 V
Voltage on +12 V VIN Pin . . . . . . . . . . . . . . . . . . . . . . . +20 V
Voltage on –12 V VIN Pin . . . . . . . . . . . . . . . . . . . . . . . . –20 V
Voltage on Analog Pins . . . . . . . . . . . –0.3 V to (VCC + 0.3 V)
Voltage on Open Drain Digital Pins . . . . . . . –0.3 V to +6.5 V
Input Current at any Pin . . . . . . . . . . . . . . . . . . . . . . . ±5 mA
Package Input Current . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Maximum Junction Temperature (TJMAX) . . . . . . . . . . 150°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . .215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . .200°C
ESD Rating, –12 VIN Pin . . . . . . . . . . . . . . . . . . . . . . . 1000 V
ESD Rating, All Other Pins . . . . . . . . . . . . . . . . . . . . . 2000 V
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
THERMAL CHARACTERISTICS48-Lead LQFP Package
θJA = 50°C/W, θJC = 10°C/W
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADM1026 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
ORDERING GUIDEFigure 1.Serial Bus Timing Diagram
PIN FUNCTION DESCRIPTIONS
PIN CONFIGURATIONGPIO9
GPIO8
FAN0/GPIO0
FAN1/GPIO1
FAN2/GPIO2
FAN3/GPIO3
3.3V MAIN
DGND
FAN4/GPIO4
FAN5/GPIO5
FAN6/GPIO6
FAN7/GPIO7
SCL
SDA
ADD/NTESTOUT
INT
PWM
RESETSTBYRESETMAIN
AGND
3.3V STBY
DAC
REF
AIN5(0 – 3V)
AIN6(0 – 2.5V)
AIN7(0 – 2.5V)
VCCP(0 – 3V)
+12 VIN(0 – 16V)
–12 VIN(0 – 16V)
+5 VIN(0 – 6.66V)
+VBAT(0 – 4.4V)
D2+/AIN8(0 – 2.5V)
D2–/AIN9(0 – 2.5V)
D1+
D1–/NTESTIN
GPIO10GPIO11GPIO12GPIO13GPIO14GPIO15GPIO16/
THERM
IN0
(0 – 3V)
IN1
(0 – 3V)
IN2
(0 – 3V)
IN3
(0 – 3V)
IN4
(0 – 3V)
ADM1026
PIN FUNCTION DESCRIPTIONS (continued)LEAKAGE RESISTANCE – M�
TEMPERATURE ERROR –
–15TPC 1.Temperature Error vs. PCB Track Resistance
TPC 2.Temperature Error vs. Power Supply
Noise Frequency
TPC 3.Temperature Error vs. Common-Mode
Noise Frequency
TPC 4.Pentium® III Temperature vs. ADM1026 Reading
TPC 5.Temperature Error vs. Capacitance
Between D+ and D–
TPC 6.Temperature Error vs. Differential-Mode
Noise Frequency
ADM1026TPC 7.Power-up Reset Timeout vs. Temperature
TPC 8.Supply Current vs. Supply Voltage
TPC 9.Local Sensor Temperature Error
TPC 10.Remote Sensor Temperature Error
TPC 11.Response to Thermal Shock
Pins 34 to 41 are general-purpose analog inputs with a range of
0V to 2.5 V or 0V to 3 V. These are mainly intended for moni-
toring SCSI termination voltages, but may be used for other
purposes.
The ADC also accepts input from an on-chip band-gap temperature
sensor that monitors system ambient temperature.
Finally, the ADM1026 monitors the supply from which it is
powered, 3.3 VSTBY, so there is no need for a separate pin to
monitor this power supply voltage.
The ADM1026 has eight pins that are general-purpose logic I/O
pins (Pins 1, 2, and 43 to 48), a pin that can be configured as
GPIO or as a bidirectional thermal interrupt (THERM) pin
(Pin42), and eightpins that can be configured for fan speed mea-
surement or as general-purpose logic pins (Pins 3 to 6 and 9 to 12).
Sequential MeasurementWhen the ADM1026 monitoring sequence is started, it cycles
sequentially through the measurement of analog inputs and the
temperature sensor, while at the same time the fan speed inputs
are independently monitored. Measured values from these inputs
are stored in value registers. These can be read out over the serial
bus, or can be compared with programmed limits stored in the
limit registers. The results of out-of-limit comparisons are
stored in the interrupt status registers, and will generate an inter-
rupt on the INT line (Pin 17).
Any or all of the interrupt status bits can be masked by appro-
priate programming of the interrupt mask registers.
Chassis IntrusionA chassis intrusion input (Pin 16) is provided to detect unautho-
rized tampering with the equipment. This event is latched in a
battery-backed register bit.
ResetsThe ADM1026 has two power-on reset outputs, RESETMAIN
and RESETSTBY, that are asserted when 3.3V MAIN or 3.3V
STBY fall below the reset threshold. These give a 180ms reset
pulse at power-up. RESETMAIN also functions as an active-low
RESET input.
Fan Speed Control OutputsThe ADM1026 has two outputs intended to control fan speed,
though they can also be used for other purposes.
Pin 18 is an open drain, pulsewidth modulated (PWM) output
with a programmable duty cycle and an output frequency of 75Hz.
Pin 23 is connected to the output of an on-chip, 8-bit digital-to-
analog converter with an output range of 0V to 2.5V.
Either or both of these outputs may be used to implement a
temperature-controlled fan by controlling the speed of a fan depen-
dent upon the temperature measured by the on-chip temperature
sensor or remote temperature sensors.
PRODUCT DESCRIPTIONThe ADM1026 is a complete system hardware monitor for
microprocessor-based systems, providing measurement and limit
comparison of various system parameters. The ADM1026 has
up to 19 analog measurement channels. Fifteen analog voltage
inputs are provided, five of which are dedicated to monitoring
+3.3V, +5 V, and ±12V power supplies, and the processor
core voltage. The ADM1026 can monitor two further power
supply voltages by measuring its own VCC and the main system
supply. One input (two pins) is dedicated to a remote temperature
sensing diode. Two further pins can be configured as general
purpose analog inputs to measure 0 to 2.5 V, or as a second
temperature sensing input. The eight remaining inputs are general-
purpose analog inputs with a range of 0V to 2.5 V or 0V to
3V. Finally, the ADM1026 has an on-chip temperature sensor.
The ADM1026 has eight pins that can be configured for fan speed
measurement or as general-purpose logic I/O pins. A further
eightpins are dedicated to general-purpose logic I/O. An addi-
tional pin can be configured as a general-purpose I/O or as the
bidirectional THERM pin.
Measured values can be read out via a 2-wire serial system man-
agement bus, and values for limit comparisons can be programmed
in over the same serial bus. The high speed, successive approxi-
mation ADC allows frequent sampling of all analog channels to
ensure a fast interrupt response to any out-of-limit measurement.
FUNCTIONAL DESCRIPTION
General DescriptionThe ADM1026 is a complete system hardware monitor for
microprocessor-based systems. The device communicates with the
system via a serial system management bus. The serial bus con-
troller has a hardwired address line for device selection (ADD,
Pin15), a serial data line for reading and writing addresses and
data (SDA, Pin 14), and an input line for the serial clock (SCL,
Pin 13). All control and programming functions of the ADM1026
are performed over the serial bus.
Measurement InputsProgrammability of the analog and digital measurement inputs
makes the ADM1026 extremely flexible and versatile. The device
has an 8-bit A/D converter, and 17 analog measurement input
pins that can be configured in different ways.
Pins 25 and 26 are dedicated temperature inputs and may be
connected to the cathode and anode of a remote temperature-
sensing diode.
Pins 27 and 28 may be configured as temperature inputs and
connected to a second temperature-sensing diode, or may be
reconfigured as analog inputs with a range of 0V to 2.5V.
Pins 29 to 33 are dedicated analog inputs with on-chip attenuators
configured to monitor VBAT, +5 V, –12 V, +12 V, and the pro-
cessor core voltage VCCP, respectively.
ADM1026
INTERNAL REGISTERSThe ADM1026 contains a large number of data registers. A
brief description of the principal registers is given below. More
detailed descriptions are given in the relevant sections and in the
tables at the end of the data sheet.
Address Pointer Register: This register contains the address that
selects one of the other internal registers. When writing to the
ADM1026, the first byte of data is always a register address,
which is written to the address pointer register.
Configuration Registers: Provide control and configuration for
various operating parameters of the ADM1026.
Fan Divisor Registers: Contain counter pre-scaler values for fan
speed measurement.
DAC/PWM Control Registers: Contain speed values for PWM
and DAC fan drive outputs.
GPIO Configuration Registers: These configure the GPIO pins
as input or output and for signal polarity.
Value and Limit Registers: The results of analog voltage inputs,
temperature and fan speed measurements are stored in these
registers, along with their limit values.
Status Registers: These registers store events from the various
interrupt sources.
Mask Registers: Allow masking of individual interrupt sources.
EEPROMThe ADM1026 has 8 kB of nonvolatile, Electrically-Erasable
Programmable Read-Only Memory (EEPROM) from register
addresses 8000h to 9FFFh. This may be used for permanent
storage of data that will not be lost when the ADM1026 is powered
down, unlike the data in the volatile registers. Although referred
to as read-only memory, the EEPROM can be written to (as well as
read from) via the serial bus in exactly the same way as the other
registers. The only major differences between the EEPROM and
other registers are:An EEPROM location must be blank before it can be written to.
If it contains data, it must first be erased.Writing to EEPROM is slower than writing to RAM.Writing to the EEPROM should be restricted because it has
a limited cycle life of 100,000 write operations, due to the
usual EEPROM wear-out mechanisms.
The EEPROM in the ADM1026 has been qualified for two key
EEPROM memory characteristics: memory cycling endurance
and memory data retention.
Endurance qualifies the ability of the EEPROM to be cycled
through many Program, Read, and Erase cycles. In real terms,single endurance cycle is composed of four independent,
sequential events. These events are defined as follows:
(a)initial page erase sequence
(b)read/verify sequence
(c)program sequence
(d)second read/verify sequence
Figure 2.Typical EEPROM Memory Retention
Retention quantifies the ability of the memory to retain its pro-
grammed data over time. The EEPROM in the ADM1026 has
been qualified in accordance with the formal JEDEC Retention
Lifetime Specification (A117) at a specific junction temperature
(TJ = 55°C) to guarantee a minimum of 10 years retention time.
As part of this qualification procedure, the EEPROM memory is
cycled to its specified endurance limit described above before
data retention is characterized. This means that the EEPROM
memory is guaranteed to retain its data for its full specified
retention lifetime every time the EEPROM is reprogrammed. It
should be noted that retention lifetime based on an activation
energy of 0.6 V will derate with TJ, as shown in Figure 2.
Serial Bus InterfaceControl of the ADM1026 is carried out via the serial System
Management Bus (SMBus). The ADM1026 is connected to
this bus as a slave device, under the control of a master device.
The ADM1026 has a 7-bit serial bus slave address. When the
device is powered up, it will do so with a default serial bus address.
The five MSB’s of the address are set to 01011, the two LSB’s
are determined by the logical states of Pin 15 (ADD/NTESTOUT).
This is a three-state input that can be grounded, connected to VCC,
or left open-circuit to give three different addresses.
Table I.Address Pin Truth TableIf ADD is left open-circuit, the default address will be 0101110
(0x5C). ADD is sampled only at power-up on the first valid
SMBus transaction, so any changes made while power is on
(and the address is locked) will have no effect.
The facility to make hardwired changes to device address allows the
user to avoid conflicts with other devices sharing the same serial
bus, for example if more than one ADM1026 is used in a system.
General SMBus TimingFigures 3a and 3b show timing diagrams for general read and
write operations using the SMBus. The SMBus specification
defines specific conditions for different types of read and write
operation, which are discussed later.
The general SMBus protocol* operates as follows:The master initiates data transfer by establishing a START
condition, defined as a high to low transition on the serial data
line SDA while the serial clock line SCL remains high. This
indicates that a data stream will follow. All slave peripherals
connected to the serial bus respond to the START condition
and shift in the next 8 bits, consisting of a 7-bit slave address
(MSB first) plus an R/W bit, which determines the direction
of the data transfer, i.e. whether data will be written to or
read from the slave device (0 = write, 1 = read).
The peripheral whose address corresponds to the transmitted
address responds by pulling the data line low during the low
period before the ninth clock pulse, known as the acknowledge
bit, and holding it low during the high period of this clock
pulse. All other devices on the bus now remain idle while the
selected device waits for data to be read from or written to it.
If the R/W bit is a 0, then the master will write to the slave
device. If the R/W bit is a 1, the master will read from the
slave device.Data is sent over the serial bus in sequences of nine clock
pulses, 8bits of data followed by an acknowledge bit from
the slave device. Data transitions on the data line must occur
during the low period of the clock signal and remain stable
during the high period, as a low to high transition when the
clock is high may be interpreted as a STOP signal.
If the operation is a write operation, the first data byte after the
slave address is a command byte. This tells the slave device what
to expect next. It may be an instruction telling the slave device
to expect a block write, or it may simply be a register address
that tells the slave where subsequent data is to be written.
Since data can flow in only one direction as defined by the R/W
bit, it is not possible to send a command to a slave device during
a read operation. Before doing a read operation, it may first
be necessary to do a write operation to tell the slave what sort
of read operation to expect and/or the address from which
data is to be read.When all data bytes have been read or written, stop conditions
are established. In WRITE mode, the master will pull the data
line high during the 10th clock pulse to assert a STOP condition.
In READ mode, the master device will release the SDA line
during the low period before the 9th clock pulse, but the slave
device will not pull it low. This is known as No Acknowledge.
The master will then take the data line low during the low
period before the 10th clock pulse, then high during the 10th
clock pulse to assert a STOP condition.
Figure 3a.General SMBus Write Timing Diagram
ADM1026
SMBUS PROTOCOLS FOR RAM AND EEPROMThe ADM1026 contains volatile registers (RAM) and nonvolatile
EEPROM. RAM occupies address locations from 00h to 6Fh,
while EEPROM occupies addresses from 8000h to 9FFFh.
Data can be written to and read from both RAM and EEPROM as
single data bytes and as block (sequential) read or write operations
of 32 data bytes, the maximum block size allowed by the SMBus
specification.
Data can only be written to unprogrammed EEPROM locations.
To write new data to a programmed location, it is first necessary
to erase it. EEPROM erasure cannot be done at the byte level; the
EEPROM is arranged as 128 pages* of 64 bytes, and an entire
page must be erased.
The EEPROM has three RAM registers associated with it,
EEPROM Registers 1, 2, and 3 at addresses 06h, 0Ch and 13h.
EEPROM Registers 1 and 2 are for factory use only. EEPROM
Register 3 is used to set up the EEPROM operating mode.
Setting Bit 0 of EEPROM Register 3 puts the EEPROM into read
mode. Setting Bit 1 puts it into Programming Mode. Setting Bit2
puts it into erase mode.
One, and only one of these bits must be set before the EEPROM
may be accessed. Setting no bits or more than one of them will
cause the device to respond with No Acknowledge if an EEPROM
read, program, or erase operation is attempted.
It is important to distinguish between SMBus write operations,
such as sending an address or command, and EEPROM program-
ming operations. It is possible to write an EEPROM address over
the SMBus, whatever the state of EEPROM Register3. However,
EEPROM Register3 must be correctly set before a subsequent
EEPROM operation can be performed. For example, when read-
ing from the EEPROM, Bit 0 of EEPROM Register 3 can be set,
even though SMBus write operations are required to set up the
EEPROM address for reading.
Bit 3 of EEPROM Register 3 is used for EEPROM write protection.
Setting this bit will prevent accidental programming or erasure
of the EEPROM. If an EEPROM write or erase operation is
attempted with this bit set, the ADM1026 will respond withAcknowledge. This bit is write once and can only be cleared
by power ON reset.
EEPROM Register 3 Bit 7 is used for clock extend. Programming
an EEPROM byte takes approximately 250 µs, which would limit
the SMBus clock for repeated or block write operations. Since
EEPROM block read/write access is slow, it is recommended that
this Clock Extend bit normally be set to 1. This allows the ADM1026
to pull SCL low and extend the clock pulse when it cannot
accept any more data.
ADM1026 SMBus OperationsThe SMBus specification defines several protocols for different
types of read and write operations. The ones used in the ADM1026
are discussed below. The following abbreviations are used in the
diagrams:
S – STARTW – WRITE
P – STOPA – ACKNOWLEDGE
R – READA – NO ACKNOWLEDGE
The ADM1026 uses the following SMBus write protocols:
Send ByteIn this operation, the master device sends a single command
byte to a slave device, as follows:The master device asserts a start condition on SDA.The master sends the 7-bit slave address followed by the
write bit (low).The addressed slave device asserts ACK on SDA.The master sends a command code.The slave asserts ACK on SDA.The master asserts a STOP condition on SDA and the
transaction ends.
In the ADM1026, the send byte protocol is used to write a register
address to RAM for a subsequent single byte read from the same
address or block read or write starting at that address. This is
illustrated in Figure 4a.
Figure 3b.General SMBus Read Timing Diagram
If it is required to read data from the RAM immediately after
setting up the address, the master can assert a repeat start con-
dition immediately after the final ACK and carry out a single
byte read, block read, or block write operation without asserting
an intermediate stop condition.
Write Byte/WordIn this operation the master device sends a command byte and
one or two data bytes to the slave device as follows:The master device asserts a start condition on SDA.The master sends the 7-bit slave address followed by the
write bit (low).The addressed slave device asserts ACK on SDA.The master sends a command code.The slave asserts ACK on SDA.The master sends a data byte.The slave asserts ACK on SDA.The master sends a data byte (or may assert STOP at this point).The slave asserts ACK on SDA.
10.The master asserts a STOP condition on SDA to end the
transaction.
In the ADM1026, the write byte/word protocol is used for four
purposes. The ADM1026 knows how to respond by the value of
the command byte and EEPROM Register 3.Write a single byte of data to RAM. In this case, the command
byte is the RAM address from 00h to 6Fh and the (only)
data byte is the actual data. This is illustrated in Figure 4b.
Figure 4b.Single Byte Write To RAMSet up a 2-byte EEPROM address for a subsequent read or
block read. In this case, the command byte is the high byte of
the EEPROM address from 80h to 9Fh. The (only) data byte
is the low byte of the EEPROM address. This is illustrated in
Figure4c.
Figure 4c. Setting An EEPROM Address
If it is required to read data from the EEPROM immediately
after setting up the address, the master can assert a repeat
start condition immediately after the final ACK and carry out
a single byte read, or block read operation without asserting
an intermediate stop condition. In this case, Bit 0 of
EEPROM Register 3 should be set.Erase a page of EEPROM memory. EEPROM memory can
be written to only if it is previously erased. Before writing to
one or more EEPROM memory locations that are already
As the EEPROM consists of 128 pages of 64 bytes, the
EEPROM page address consists of the EEPROM address
high byte (from 80h to 9Fh) and the two MSBs of the low
byte. The lower sixbits of the EEPROM address low byte
only specify addresses within a page and are ignored during
an erase operation.
Figure 4d.EEPROM Page Erasure
Page erasure takes approximately 20ms. If the EEPROM is
accessed before erasure is complete, the ADM1026 will
respond with No Acknowledge.Write a single byte of data to EEPROM. In this case, the
command byte is the high byte of the EEPROM address from
80h to 9Fh. The first data byte is the low byte of the EEPROM
address and the second data byte is the actual data. Bit 1EEPROM Register 3 must be set. This is illustrated in
Figure4e.
Figure 4e.Single Byte Write To EEPROM
Block WriteIn this operation, the master device writes a block of data to a
slave device. The start address for a block write must previously
have been set. In the case of the ADM1026, this is done by a
Send Byte operation to set a RAM address or a Write Byte/Word
operation to set an EEPROM address.The master device asserts a start condition on SDA.The master sends the 7-bit slave address followed by the
write bit (low).The addressed slave device asserts ACK on SDA.The master sends a command code that tells the slave device
to expect a block write. The ADM1026 command code for
a block write is A0h (10100000).The slave asserts ACK on SDA.The master sends a data byte (20h) that tells the slave devicedata bytes will be sent to it. The master should always
send 32 data bytes to the ADM1026.The slave asserts ACK on SDA.The master sends 32 data bytes.The slave asserts ACK on SDA after each data byte.
10.The master sends a PEC (Packet Error Checking) byte.
11.The ADM1026 checks the PEC byte and issues an ACK if
correct. If incorrect (NACK), the master should resend the
data bytes.
12.The master asserts a STOP condition on SDA to end the
ADM1026Figure 4f.Block Write To EEPROM or RAM
When performing a block write to EEPROM, Bit 1 of EEPROM
Register 3 must be set.
Unlike some EEPROM devices that limit block writes to within
a page boundary, there is no limitation on the start address
when performing a block write to EEPROM, except:There must be at least 32 locations from the start address to
the highest EEPROM address (9FFF) to avoid writing to
invalid addresses.If the addresses cross a page boundary, both pages must be
erased before programming.
ADM1026 READ OPERATIONSThe ADM1026 uses the following SMBus read protocols:
Receive ByteIn this operation, the master device receives a single byte from a
slave device as follows:The master device asserts a START condition on SDA.The master sends the 7-bit slave address followed by the
read bit (high).The addressed slave device asserts ACK on SDA.The master receives a data byte.The master asserts NO ACK on SDA.The master asserts a STOP condition on SDA and the trans-
action ends.
In the ADM1026, the receive byte protocol is used to read a
single byte of data from a RAM or EEPROM location whose
address has previously been set by a send byte or write byte/word
operation. This is illustrated in Figure 4g. When reading from
EEPROM, Bit 0 of EEPROM Register 3 must be set.
Figure 4g.Single Byte Read From EEPROM or RAM
Block ReadIn this operation, the master device reads a block of data from a
slave device. The start address for a block read must previously
have been set. In the case of the ADM1026 this is done by a
Send Byte operation to set a RAM address, or a Write Byte/Word
operation to set an EEPROM address. The block read operation
itself consists of a Send Byte operation that sends a block read
command to the slave, immediately followed by a repeated start
and a read operation that reads out multiple data bytes as follows:The master device asserts a START condition on SDA.The master sends the 7-bit slave address followed by the
write bit (low).The addressed slave device asserts ACK on SDA.The master sends a command code that tells the slave de-
vice to expect a block read. The ADM1026 command code
for a block read is A1h (10100001).The slave asserts ACK on SDA.The master asserts a repeat start condition on SDA.The master sends the 7-bit slave address followed by the
read bit (high).The slave asserts ACK on SDA.The ADM1026 sends a byte count data byte that tells the
master how many data bytes to expect. The ADM1026 will
always return 32 data bytes (20h), the maximum allowed by
the SMBus 1.1 specification.
10.The master asserts ACK on SDA.
11.The master receives 32 data bytes.
12.The master asserts ACK on SDA after each data byte.
13.The ADM1026 issues a PEC byte to the master. The master
should check the PEC byte and issue another block read if
the PEC byte is incorrect.
14.A NACK is generated after the PEC byte to signal the end
of the read.
15.The master asserts a STOP condition on SDA to end the
transaction.
Figure 4h.Block Read From EEPROM or RAM
When block reading from EEPROM, Bit 0 of EEPROM
Register3 must be set.
NOTE
Although the ADM1026 supports Packet Error Checking (PEC), its use is
optional. The PEC byte is calculated using CRC-8. The Frame Check Sequence
(FCS) conforms to CRC-8 by the polynomial:
MEASUREMENT INPUTSThe ADM1026 has 17 external analog measurement pins, which
can be configured to perform various functions. It also measures
two supply voltages, 3.3 V MAIN and 3.3 V STBY, and the
internal chip temperature.
Pins 25 and 26 are dedicated to remote temperature measurement,
while Pins 27 and 28 can be configured as analog inputs with a
range of 0V to 2.5 V or as inputs for a second remote tempera-
ture sensor.
Pins 29 to 33 are dedicated to measuring VBAT, +5V, –12V, +12V
supplies and the processor core voltage VCCP. The remaining
analog inputs, Pins 34 to 41, are general-purpose analog inputs
with a range of 0V to 2.5V (Pins 34 and 35) or 0V to 3V
(Pins 36 to 41).
A to D Converter (ADC)These inputs are multiplexed into the on-chip, successive approxi-
mation, analog-to-digital converter. This has a resolution of 8bits.
The basic input range is 0 V to 2.5V, which is the input range
of AIN6 to AIN9, but five of the inputs have built-in attenuators to
allow measurement of VBAT, +5V, –12V, +12V and the processor
core voltage VCCP, without any external components. To allow
for the tolerance of these supply voltages, the A to D converter
produces an output of 3/4 full scale (decimal 192) for the nominal
input voltage, and so has adequate headroom to cope with over-
voltages. Table II shows the input ranges of the analog inputs
and output codes of the A to D converter (ADC).
When the ADC is running, it samples and converts an analog or
local temperature input every 711 µs (typical value). Each input
is measured 16 times and the measurements averaged to reduce
noise, so the total conversion time for each input is 11.38 ms.
Measurements on the remote temperature (D1 and D2) inputs
take 2.13 ms. These are also measured 16 times and averaged,
so the total conversion time for a remote temperature input34.13 ms.
Voltage Measurement InputsThe internal structure for all the analog inputs is shown in Fig-
ure 5. Each input circuit consists of an input protection diode, an
attenuator, plus a capacitor to form a first-order low-pass filter
that gives each voltage measurement input immunity to high fre-
quency noise. The –12 V input also has a resistor connected to the
on-chip reference to offset the negative voltage range so that it is
always positive and can be handled by the ADC. This allows
most popular power supply voltages to be monitored directly by
the ADM1026 without requiring any additional resistor scaling.
Table II.A to D Output Code vs. VIN12.000–12.063
ADM1026Figure 5.Voltage Measurement Inputs
Setting Other Input RangesAIN0 to AIN9 can easily be scaled to voltages other than 2.5 V or
3 V. If the input voltage range is zero to some positive voltage, then
all that is required is an input attenuator, as shown in Figure 6.
However, when scaling AIN0 to AIN5, it should be noted that these
inputs already have an on-chip attenuator, since their primary
function is to monitor SCSI termination voltages. This attenuator
will load any external attenuator. The input resistance of the
on-chip attenuator can be between 100 kΩ and 200 kΩ. For this
tolerance not to affect the accuracy, the output resistance of the
external attenuator should be very much lower than this, i.e., 1kΩ
in order to add not more than 1% to the TUE (Total Unadjusted
Error). Alternatively, the input can be buffered using an opamp.
Negative and bipolar input ranges can be accommodated by
using a positive reference voltage to offset the input voltage
range so that it is always positive.
To monitor a negative input voltage, an attenuator can be used
as shown in Figure 7.
Figure 7.Scaling and Offsetting AIN0 – AIN9 for
Negative Inputs
This offsets the negative voltage so that the ADC always seespositive voltage. R1 and R2 are chosen so that the ADC input
voltage is zero when the negative input voltage is at its maximum
(most negative) value, i.e.:
This is a simple and low cost solution, but the following points
should be noted:Since the input signal is offset but not inverted, the input
range is transposed. An increase in the magnitude of the negative
voltage (going more negative) will cause the input voltage to
fall and give a lower output code from the ADC. Conversely,decrease in the magnitude of the negative voltage will cause
the ADC code to increase. The maximum negative voltage
corresponds to zero output from the ADC. This means that
the upper and lower limits will be transposed.For the ADC output to be full scale when the negative voltage
is zero, VOS must be greater than the full-scale voltage of the
ADC, because VOS is attenuated by R1 and R2. If VOS is equal
to or less than the full-scale voltage of the ADC, the input range
is bipolar but not necessarily symmetrical.
This is only a problem if the ADC output must be full scale
when the negative voltage is zero.
Symmetrical bipolar input ranges can easily be accommodated
by making VOS equal to the full-scale voltage of the analog input,
and adding a third resistor to set the positive full scale.
Figure 8.Scaling and Offsetting AIN0 – AIN9 for Bipolar Inputs
(R3 has no effect as the input voltage at the device pin is zero
when VIN = minus full scale)
(R2 has no effect as the input voltage at the device pin is equal to
VOS when VIN = plus full scale).
Battery Measurement Input (VBAT)The VBAT input allows the condition of a CMOS backup battery
to be monitored. This is typically a lithium coin cell such as a
CR2032. Normally, the battery in a system is required to keep
some device powered when the system is in a powered-off state.
The VBAT measurement input is specially designed to minimize
battery drain. To reduce current drain from the battery, the
lower resistor of the VBAT attenuator is not connected, except
whenever aVBAT measurement is being made. The total current
drain on the VBAT pin is 80 nA typical (for a maximum VBAT
voltage = 4V), so a CR2032 CMOS battery will function in a
system in excess of the expected 10 years. Note that when a VBAT
measurement is not being made, the current drain is reduced to
6nA typical. Under normal voltage measurement operating
conditions, all measurements are made in a round-robin format,
and each reading is actually the result of 16 digitally averaged
measurements. However, averaging is not carried out on the
VBAT measurement to reduce measurement time and therefore
reduce the current drain from the battery. The VBAT current
drain when a measurement is being made is calculated by:
For VBAT = 3 V,
where TPULSE = VBAT measurement time (711 µs typical),
TPERIOD = time to measure all analog inputs (273 ms typical),
and VBAT input battery protection.
VBAT Input Battery ProtectionIn addition to minimizing battery current drain, the VBAT measure-
ment circuitry was specifically designed with battery protection in
mind. Internal circuitry prevents the battery from being back-
biased by the ADM1026 supply or through any other path under
normal operating conditions. In the unlikely event of some
catastrophic ADM1026 failure, the ADM1026 includes a second
level of battery protection including a series 3kΩ resistor to limit
current to the battery, as recommended by UL. It is therefore
not necessary to add a series resistor between the battery and the
VBAT input; the battery should be connected directly to the
VBATinput to improve voltage measurement accuracy.
Figure 9.Equivalent VBAT Input Protection Circuit
Reference Output (VREF)The ADM1026 offers an on-chip reference voltage (Pin 24) that
can be used to provide a 1.82 V or 2.5 V reference voltage output.
This output is buffered and specified to sink or source a load
current of 2 mA. The reference voltage outputs 1.82 V if Bit2
of Configuration Register 3 (address 07h) is 0; it outputs 2.5V
when this bit is set to 1. This voltage reference output can be
used to provide a stable reference voltage to external circuitry
such as LDOs. The load regulation of the VREF output is typi-
cally 0.15% for a sink current of 2mA and 0.15% for 2mA
source current. There may be some ripple present on the VREF
output that requires filtering (±4 m VMAX). Figure 11 shows the
recommended circuitry for the VREF output for loads less thanmA. For loads in excess of 2mA, external circuitry, such as that
shown in Figure12, should be used to buffer the VREF output.
ADM1026The technique used in the ADM1026 is to measure the change in
Vbe when the device is operated at two different currents, given by:
where K is Boltzmann’s constant, q is charge on the carrier,isabsolute temperature in Kelvins, and N is the ratio of the
two currents.
Figure 10 shows the input signal conditioning used to measure
the output of a remote temperature sensor. This figure shows the
external sensor as a substrate transistor provided for temperature
monitoring on some microprocessors, but it could equally well
be a discrete transistor such as a 2N3904.
If a discrete transistor is used, the collector will not be grounded
and should be linked to the base. If a PNP transistor is used, the
base is connected to the D– input and the emitter to the D+ input.
If an NPN transistor is used, the emitter is connected to theinput and the base to the D+ input.
To prevent ground noise interfering with the measurement, the
more negative terminal of the sensor is not referenced to ground
but is biased above ground by an internal diode at the D– input.
To measure �Vbe, the sensor is switched between operating cur-
rents of I and N� I. The resulting waveform is passed through akHz low-pass filter to remove noise, and to a chopper-stabilized
amplifier that performs the functions of amplification and recti-
fication of the waveform to produce a DC voltage proportional to
�Vbe. This voltage is measured by the ADC to give a temperature
output in 8-bit two’s complement format. To further reduce the
effects of noise, digital filtering is performed by averaging the
results of 16 measurement cycles. A remote temperature mea-
surement takes nominally 2.14ms.
The results of external temperature measurements are stored in
8-bit, two’s complement format, as illustrated in Table III.
Table III.Temperature Data FormatFigure 11.VREF Interface Circuit for VREF Loads < 2 mA
If the VREF output is not being used, it should be left unconnected.
Do not connect VREF to GND using a capacitor. The internal
output buffer on the voltage reference will be capacitively loaded
and this can cause the voltage reference to oscillate. This will
affect temperature readings reported back by the ADM1026. The
recommended interface circuit for the VREF output is shown in
Figure 12.
Figure 12.VREF Interface Circuit for VREF Loads > 2 mA
TEMPERATURE MEASUREMENT SYSTEM
Local Temperature MeasurementThe ADM1026 contains an on-chip bandgap temperature sensor
whose output is digitized by the on-chip ADC. The temperature
data is stored in the Local Temperature Value Register (address
1Fh). As both positive and negative temperatures can be measured,
the temperature data is stored in two’s complement format, as
shown in Table III. Theoretically, the temperature sensor and
ADC can measure temperatures from –128oC to +127oC with a
resolution of 1oC. However, temperatures below TMIN and above
TMAX are outside the operating temperature range of the device, so
local temperature measurements outside this range are not possible.
Temperature measurement from –128oC to +127oC is possible
using a remote sensor.
Remote Temperature MeasurementThe ADM1026 can measure the temperature of two remote diode
sensors or diode-connected transistors, connected to Pins 25 and
26, or 27 and 28.
Pins 25 and 26 are a dedicated temperature input channel. Pins27
and 28 can be configured to measure a diode sensor by clearing
Bit 3 of Configuration Register 1 (address 00h) to 0. If this bit
is 1, then Pins 27 and 28 are AIN8 and AIN9.
The forward voltage of a diode or diode-connected transistor,
operated at a constant current, exhibits a negative temperature
coefficient of about –2 mV/oC. Unfortunately, the absolute value
Layout ConsiderationsDigital boards can be electrically noisy environments and care
must be taken to protect the analog inputs from noise, particularly
when measuring the very small voltages from a remote diode
sensor. The following precautions should be taken:Place the ADM1026 as close as possible to the remote sensing
diode. Provided that the worst noise sources such as clock
generators, data/address buses and CRTs are avoided, this
distance can be 4 to 8 inches.Route the D+ and D– tracks close together, in parallel, with
grounded guard tracks on each side. Provide a ground plane
under the tracks if possible.Use wide tracks to minimize inductance and reduce noise pickup.
10 mil track minimum width and spacing is recommended.
Figure 13.Arrangement of Signal TracksTry to minimize the number of copper/solder joints, which can
cause thermocouple effects. Where copper/solder joints are
used, make sure that they are in both the D+ and D– path
and at the same temperature.
Thermocouple effects should not be a major problem as 1oC
corresponds to about 240 µV, and thermocouple voltages are
about 3µV/oC of temperature difference. Unless there are two
thermocouples with a big temperature differential between
them, thermocouple voltages should be much less than 200mV.Place a 0.1 µF bypass capacitor close to the ADM1026.If the distance to the remote sensor is more than 8 inches, the
use of twisted pair cable is recommended. This will work up
to about 6 to 12 feet.For very long distances (up to 100 feet), use shielded twisted
pair such as Belden #8451 microphone cable. Connect the
twisted pair to D+ and D– and the shield to GND close to the
ADM1026. Leave the remote end of the shield unconnected
to avoid ground loops.
Because the measurement technique uses switched current sources,
excessive cable and/or filter capacitance can affect the measure-
ment. When using long cables, the filter capacitor may be reduced
or removed.
Cable resistance can also introduce errors. 1Ω series resistance
introduces about 0.5oC error.
Limit ValuesLimit values for analog measurements are stored in the appro-
priate limit registers. In the case of voltage measurements, high
and low limits can be stored so that an interrupt request will be
allows the system to be shut down when the hot limit is exceeded,
and restarted automatically when it has cooled down to a safe
temperature.
Analog Monitoring Cycle TimeThe analog monitoring cycle begins when a one is written to the
start bit (Bit 0), and a 0 to the INT_Clear bit (Bit 2) of the
configuration register. INT_Enable (Bit 1) should be set to one
to enable the INT output. The ADC measures each analog
input in turn, starting with remote temperature channel 1 and
ending with local temperature. As each measurement is com-
pleted the result is automatically stored in the appropriate value
register. This “round-robin” monitoring cycle continues until it
is disabled by writing a 0 to Bit 0 of the Configuration Register.
As the ADC will normally be left to free-run in this manner, the
time taken to monitor all the analog inputs will normally not be
of interest, as the most recently measured value of any input can
be read out at any time.
For applications where the monitoring cycle time is important,
it can easily be calculated.
The total number of channels measured is:
Five dedicated supply voltage inputs
Ten general purpose analog inputs
3.3 V MAIN
3.3 V STBY
Local temperature
Two remote temperature
Pins 28 and 27 are measured both as analog inputs AIN8/AIN9
and as remote temperature input D2+/D2–, irrespective of
which configuration is selected for these pins.
If Pins 28 and 27 are configured as AIN8/AIN9, the measurements
for these channels are stored in Registers 27h and 29h and the
invalid temperature measurement is discarded. On the other hand,
if Pins 28 and 27 are configured as D2+/D2–, the temperature
measurement is stored in Register 29h and there will be no valid
result in Register 27h.
As mentioned previously, the ADC performs a conversion every
711µs on the analog and local temperature inputs and every
2.13ms on the remote temperature inputs. Each input is mea-
sured 16 times and averaged to reduce noise.
The total monitoring cycle time for voltage and temperature
inputs is therefore nominally:
The ADC uses the internal 22.5 kHz clock, which has a tolerance
of ±6%, so the worst case monitoring cycle time is 290ms. The
fan speed measurement uses a completely separate monitoring
loop, as described later.
Input SafetyScaling of the analog inputs is performed on-chip, so external
attenuators are normally not required. However, since the power
supply voltages will appear directly at the pins, it is advisable to
add small external resistors (i.e., 500 Ω) in series with the supply
traces to the chip to prevent damaging the traces or power supplies
should an accidental short such as a probe connect two power
ADM1026The worst such accident would be connecting –12 V to +12 V–
a total of 24V difference. With the series resistors, this would
draw a maximum current of approximately 24mA.
ANALOG OUTPUTThe ADM1026 has a single analog output from an unsigned 8-bit
DAC that produces 0V to 2.5 V (independent of the reference
voltage setting). The input data for this DAC is contained in the
DAC control register (address 04h) The DAC control register
defaults to FFh during powerON reset, which produces maximum
fan speed. The analog output may be amplified and buffered with
external circuitry such as an opamp and transistor to provide fan
speed control. During automatic fan speed control, described
later, the four MSBs of this register set the minimum fan speed.
Suitable fan drive circuits are given in Figures 14a to 14e. When
using any of these circuits, the following points should be noted:All of these circuits will provide an output range from zero to
almost +12 V, apart from Figure 14a, which loses the base-
emitter voltage drop of Q1 due to the emitter-follower
configuration.To amplify the 2.5 V range of the analog output up to 12 V,
the gain of these circuits needs to be around 4.8.Care must be taken when choosing the op amp to ensure that
its input common-mode range and output voltage swing are
suitable.The op amp may be powered from the +12 V rail alone or from12 V. If it is powered from +12 V then the input common-
mode range should include ground to accommodate the
minimum output voltage of the DAC, and the output voltage
should swing below 0.6 V to ensure that the transistor can be
turned fully off.If the op amp is powered from –12 V then precautions such as
a clamp diode to ground may be needed to prevent the base-
emitter junction of the output transistor being reverse-biased in
the unlikely event that the output of the op amp should swing
negative for any reason.In all these circuits, the output transistor must have an ICMAX
greater than the maximum fan current, and be capable of
dissipating power due to the voltage dropped across it when
the fan is not operating at full speed.If the fan motor produces a large back EMF when switched off,
it may be necessary to add clamp diodes to protect the output
transistors in the event that the output goes from full scale to
zero very quickly.
PWM OutputFan speed may also be controlled using pulsewidth modulation
(PWM). The PWM output (Pin 18) produces a pulsed output
with a frequency of approximately 75 Hz and a duty cycle defined
by the contents of the PWM Control Register (address 05h).
During automatic fan speed control, described below, the four
MSBs of this register set the minimum fan speed.
The open drain PWM output must be amplified and buffered to
drive the fans. The PWM output is intended to be used with an
NMOS driver, but may be inverted by setting Bit 1 of Test Regis-
Automatic Fan Speed ControlThe ADM1026 offers a simple method of controlling fan speed
according to temperature without intervention from the host
processor.
To enable automatic fan speed control, monitoring must be
enabled by setting Bit 0 of Configuration Register 1 (address 00h).
Automatic fan speed control can be applied to the DAC output,
the PWM output, or both, by setting Bit 5 and/or Bit 6 of Con-
figuration Register 1.
The TMIN registers (addresses 10h to 12h) contain minimum
temperature values for the three temperature channels (on-chip
sensor and two remote diodes). This is the temperature at which a
fan will start to operate when the temperature sensed by the control-
ling sensor exceeds TMIN. TMIN can be the same or different for
all three channels. TMIN is set by writing a two’s complement
temperature value to the TMIN registers. If any sensor channel is
not required for automatic fan speed control, TMIN for that channel
should be set to +127oC (01111111).
In Automatic Fan Speed Control Mode, (Figure 15a and 15b)
the four MSBs of the DAC Control Register (address 04h) and
PWM Control Register (address 05h) set the minimum values
for the DAC and PWM outputs. Note, if both DAC Control and
PWM Control is enabled (Bits 5 and 6 of Configuration Regis-
ter 1 = 1), the four MSBs of the DAC Control Register (address
04h) define the minimum fan speed values for both the DAC and
PWM outputs. The value in the PWM Control Register (address
05h) has no effect.
Minimum DAC Code DACMIN = 16 × D
Minimum PWM Duty Cycle PWMMIN = 6.67 × D
where D is the decimal equivalent of Bits 7 to 4 of the register.
When the temperature measured by any of the sensors exceeds
the corresponding TMIN, the fan is spun up for 2 seconds with
the fan drive set to maximum (full scale from the DAC or 100%
PWM duty cycle. The fan speed is then set to the minimum as
previously defined. As the temperature increases, the fan drive
will increase until the temperature reaches TMIN + 20oC.
Figure 14b.Fan Drive Circuit with Op Amp and
PNP Transistor
Figure 14c.Fan Drive Circuit with Op Amp and
P-Channel MOSFET
DACFigure 14d.Discrete Fan Drive Circuit with
P-Channel MOSFET, Single Supply
Figure 14e.Discrete Fan Drive Circuit with
P-Channel MOSFET, Dual Supply
PWMFigure 14f.PWM Fan Drive Circuit Using an
N-Channel MOSFET
The fan drive at any temperature up to 20oC above TMIN is
given by:
or,
For simplicity of the automatic fan speed algorithm, the DAC code
increases linearly up to 240, not its full scale of 255. However,
when the temperature exceeds TMIN +20oC, the DAC output will
jump to full scale. To ensure that the maximum cooling capacity
is always available, the fan drive is always set by the sensor channel
demanding the highest fan speed.
If the temperature falls, the fan will not turn off until the tempera-
ture measured by all three temperature sensors has fallen to their
corresponding TMIN – 4oC. This prevents the fan from cycling
on and off continuously when the temperature is close to TMIN.
Whenever a fan starts or stops during automatic fan speed control,
a one-off interrupt is generated at the INT output. This is described
in more detail in the section on the ADM1026 Interrupt Structure.
ADM1026Figure 15a.Automatic PWM Fan Control Transfer Function
Figure 15b.Automatic DAC Fan Control Transfer Function
Fan InputsPins 3 to 6 and 9 to 12 may be configured as fan speed measur-
ing inputs by clearing the corresponding bit(s) of Configuration
Register 2 (Address 01h), or as general-purpose logic inputs/
outputs by setting bits in this register. The power-on default
value for this register is 00h, which means all the inputs are set
for fan speed measurement.
Signal conditioning in the ADM1026 accommodates the slow
rise and fall times typical of fan tachometer outputs. The Fan
Tach inputs have internal 10 kΩ pull-up resistors to 3.3 V
STBY. In the event that these inputs are supplied from fan
outputs that exceed the supply, either resistive attenuation of
the fan signal or diode clamping must be included to keep in-
puts within an acceptable range.
Figures 16a to 16d show circuits for most common fan tacho
outputs.
If the fan tacho output is open-drain or has a resistive pull-up to
VCC, then it can be connected directly to the fan input, as
shown in Figure 16a.
Figure 16a.Fan With Tach Pull-Up To +VCC
If the fan output has a resistive pull-up to +12V (or other voltage
greater than 3.3V STBY) then the fan output can be clamped
with a zener diode, as shown in Figure 16b. The zener voltage
should be chosen so that it is greater than VIH but less than
3.3V STBY, allowing for the voltage tolerance of the zener.
Figure 16b.Fan with Tach Pull-Up to Voltage
>VCC (e.g. 12 V) Clamped with Zener Diode
If the fan has a strong pull-up (less than 1k Ω) to +12 V, or a
totem-pole output, then a series resistor can be added to limit the
zener current, as shown in Figure 16c. Alternatively, a resistive
attenuator may be used, as shown in Figure 16d.
R1 and R2 should be chosen such that:
Figure 16c.Fan with Strong Tach Pull-Up to > VCC or
Totem Pole Output, Clamped with Zener and Resistor
Figure 16d.Fan with Strong Tach Pull-Up to >VCC or
Totem Pole Output, Attenuated with R1/R2
FAN SPEED MEASUREMENTThe fan counter does not count the fan tacho output pulses
directly because the fan speed may be less than 1000 RPM and
it would take several seconds to accumulate a reasonably large
and accurate count. Instead, the period of the fan revolution is
measured by gating an on-chip 22.5 kHz oscillator into the input of
an 8-bit counter for two periods of the fan tacho output, as shown
in Figure 17, so the accumulated count is actually proportional to
the fan tacho period and inversely proportional to the fan speed.
Figure 17.Fan Speed Measurement
The monitoring cycle begins when a 1 is written to the Monitor
bit (Bit 0 of Configuration Register 1). The INT_Enable (Bit 1)
should be set to one to enable the INT output.
The fan speed counter starts counting as soon as the Fan Chan-
nel has been switched to. If the Fan Tach Count reaches 0xFF,
the fan has failed or is not connected. If a fan is connected and
running, the counter gets reset on the second tach rising edge,
and oscillator pulses are actually counted from the second rising
tach edge to the fourth rising edge. The measurement then
switches to the next fan channel. Here again, the counter begins
counting and is reset on the second tach rising edge, and oscilla-
tor pulses are counted from the second rising edge to the fourth
rising edge. This is repeated for the other six fan channels.
Note that fan speed measurement does not occur until 1.8 sec-
onds after the monitor bit has been set. This is to allow the fans
adequate time to spin up. Otherwise, the ADM1026 could
generate false fan failure interrupts. During the 1.8 second fan
spin-up time, all Fan Tach Registers read 0x00.
To accommodate fans of different speed and/or different numbers
of output pulses per revolution, a pre-scaler (divisor) of 1, 2, 4,
or 8 may be added before the counter. Divisor values for Fans 03 are contained in the Fan 0–3 Divisor Register (Address 02h)
and those for Fans 4 to 7 in the Fan 4–7 Divisor Register (Address
03h). The default value is 2, which gives a count of 153 for a fan
running at 4400 RPM producing two output pulses per revolution.
The count is calculated by the equation:
For constant speed fans, fan failure is normally considered to
have occurred when the speed drops below 70% of nominal, which
would correspond to a count of 219. Full scale (255) would be
Table IV shows the relationship between fan speed and time per
revolution at 60%, 70%, and 100% of nominal RPM for fan
speeds of 1100, 2200, 4400, and 8800 RPM, and the divisor
that would be used for each of these fans, based on two tacho
pulses per revolution.
Table IV.Fan Speeds and Divisors
Limit ValuesFans generally do not overspeed if run from the correct voltage,
so the failure condition of interest is underspeed due to electrical or
mechanical failure. For this reason, only low speed limits are pro-
grammed into the limit registers for the fans. It should be noted
that since fan period rather than speed is being measured, a fan
failure interrupt will occur when the measurement exceeds the
limit value.
Fan Monitoring Cycle TimeThe fan speeds are measured in sequence from 0 to 7. The moni-
toring cycle time depends on the fan speed, the number of tacho
output pulses per revolution and the number of fans being monitored.
If a fan is stopped or running so slowly that the fan speed counter
reaches 255 before the second tach pulse after initialization, or
before the fourth tach pulse during measurement, the measure-
ment will be terminated. This will also occur if an input is
configured as GPIO instead of fan. Any channels so connected
will time out after 255 clock pulses.
The worst-case measurement time for a fan-configured channel
occurs when the counter reaches 254 from start to the second
tach pulse and reaches 255 after the second tach pulse. Taking
into account the tolerance of the oscillator frequency, the worst-
case measurement time is:
where:
509 is the total number of clock pulses.
D is the divisor: 1, 2, 4, or 8.
0.047 is the worst-case oscillator period in ms.
The worst-case fan monitoring cycle time is the sum of the
worst case measurement time for each fan.
Although the fan monitoring cycle and the analog input monitoring
cycle are started together, they are not synchronized in any
other way.
Chassis Intrusion InputThe Chassis Intrusion input is an active high input intended for
detection and signalling of unauthorized tampering with the system.
When this input goes high, the event is latched in Bit 6 of Status
Register 4 and an interrupt will be generated. The bit will remain
ADM1026VBAT) but will not immediately generate an interrupt. Once a
chassis intrusion event has been detected and latched, an interrupt
will be generated when the system is powered up.
The actual detection of chassis intrusion is performed by an
external circuit that will detect, for example, when the cover has
been removed. A wide variety of techniques may be used for the
detection, for example:
•A microswitch that opens or closes when the cover is removed.
•Reed switch operated by magnet fixed to the cover.
•Hall-effect switch operated by magnet fixed to the cover.
•Phototransistor that detects light when cover is removed.
The chassis intrusion input can also be used for other types of
alarm input. Figure 18 shows a temperature alarm circuit using an
AD22105 temperature switch sensor. This produces a low-going
output when the preset temperature is exceeded, so the output
is inverted by Q1 to make it compatible with the CI input. Q1 can
be almost any small-signal NPN transistor, or a TTL or CMOS
inverter gate may be used if one is available. See the AD22105
data sheet for information on selecting RSET.
Figure 18.Using the CI Input with a Temperature Sensor
GENERAL-PURPOSE I/O PINS (OPEN DRAIN)The ADM1026 has eight pins that are dedicated to general-
purpose logic input/output (Pins 1, 2, and 43 to 48), eight pins
that can be configured as general-purpose logic pins or fan
speed inputs (Pins 3 to 6, and 9 to 12), and one pin that can be
configured as GPIO16 or the bidirectional THERM pin (Pin 42).
The GPIO/FAN pins are configured as general-purpose logic pins
by setting Bits 0 to7 of Configuration Register 2 (Address 01h).
Pin42 is configured as GPIO16 by setting Bit 0 of Configuration
Register3, or as the THERM function by clearing this bit.
Each GPIO pin has four data bits associated with it, two bits in
one of the GPIO Configuration Registers (Addresses 08h to 0Bh),
one in the GPIO Status Registers (Addresses 24h and 25h), and
one in the GPIO Mask Registers (Addresses 1Ch and 1Dh)
SETTING a Direction Bit = 1 in one of the GPIO configuration
registers makes the corresponding GPIO pin an OUTPUT.
CLEARING the direction bit to 0 makes it an INPUT.
SETTING a Polarity Bit = 1 in one of the GPIO configuration
registers makes the corresponding GPIO pin active HIGH.
CLEARING the polarity bit to 0 makes it active LOW.
When a GPIO pin is configured as an INPUT, the corresponding
bit in one of the GPIO status registers is read-only, and is set when
the input is asserted (“asserted” may be high or low depending
this bit will then assert the GPIO output. (Here again, “asserted”
may be high or low depending on the setting of the polarity bit.)
The effect of a GPIO Status Register bit on the INT output can
be masked out by setting the corresponding bit in one of the
GPIO mask registers. When the pin is configured as an output,
this bit will automatically be masked to prevent the data written
to the status bit from causing an interrupt, with the exception of
GPIO16, which must be masked manually by setting Bit 7 of
Mask Register 4 (Reg 1Bh).
When configured as inputs, the GPIO pins may be connected to
external interrupt sources such as temperature sensors with
digital output. Another application of the GPIO pins would be
to monitor a processor’s Voltage ID code (VID code).
The ADM1026 Interrupt StructureThe Interrupt Structure of the ADM1026 is shown in Figure19.
Interrupts can come from a number of sources, which are com-
bined to form a common INT output. When INT is asserted,
this output pulls low. The INT pin has an internal, 100 kΩ pull-up
resistor.Analog/Temperature Inputs. As each analog measurement
value is obtained and stored in the appropriate value register,
the value and the limits from the corresponding limit registers
are fed to the high and low limit comparators. The ADM1026
performs greater than comparisons to the high limits. An
out-of-limit is also generated if a result is less than or equal
to a low limit. The result of each comparison (1 = out of
limit, 0 = in limit) is routed to the corresponding bit input of
Interrupt Status Register 1, 2, or 4 via a data demultiplexer,
and used to set that bit high or low as appropriate. Status
bits are self-clearing. If a bit in a status register is set due to
an out-of-limit measurement, it will continue to cause INT to
be asserted as long as it remains set, as described below. How-
ever, if a subsequent measurement is in limit it will be reset and
will not cause INT to be reasserted. Status bits are unaffected
by clearing the interrupt.
Interrupt Mask Registers, 1, 2, and 4 have bits corresponding
to each of the interrupt status register bits. Setting an inter-
rupt mask bit high forces the corresponding status bit output
low, while setting an interrupt mask bit low allows the corre-
sponding status bit to be asserted. After mask gating, the
status bits are all OR’d together to produce the analog and
fan interrupt, which is used to set a latch. The output of this
latch is OR’d with other interrupt sources to produce the INT
output. This will pull low if any unmasked status bit goes
high, i.e. when any measured value goes out of limit.
When an INT output due to an out-of-limit analog/tempera-
ture measurement is cleared by one of the methods described
later, the latch is reset. It will not be set again, and INT will
not be reasserted until after two Local Temperature Measure-
ments have been taken, even if the status bit remains set or a
new analog/temperature event occurs, as shown in Figure20.
This delay corresponds to almost 2 monitoring cycles, and is
about 530 ms. However, interrupts from other sources such
as a fan or GPIO can still occur. This is illustrated in Figure21.
Status Register 4 also stores inputs from two other interrupt
Figure19.Interrupt Structure
ADM1026It is cleared during the next monitoring cycle and if INT has
been cleared, it will not cause INT to be reasserted.
Figure 22.Assertion of INT Due to AFC Event
In a similar way, a change of state at the THERM output
(described in more detail later), sets bit 3 of Status Register 4
and causes a one-off INT output. A change of state at the
THERM output also causes Bit 0 of Status Register 1, Bit1
of Status Register 1, or Bit 0 of Status Register 4 to be set,
depending on which temperature channel caused the THERM
event. This bit will be reset during the next monitoring cycle,
provided the temperature channel is within the normal high
and low limits.Fan Inputs. Fan inputs generate interrupts in a similar way to
analog/temp inputs, but as the analog/temperature inputs and
fan inputs have different monitoring cycles, they have separate
interrupt circuits. As the speed of each fan is measured, the
output of the fan speed counter is stored in a value register.
The result is compared to the fan speed limit and used to set or
clear a bit in Status Register 3. In this case, the fan is only
monitored for under-speed (fan counter > fan speed limit).
Mask Register3 is used to mask fan interrupts. After mask
gating, the fan status bits are OR’d together and used to set a
latch, whose output is OR’d with other interrupt sources to
produce the INT output.
Like the analog/temp interrupt, an INT output caused by anGPIO and CI Pins. When GPIO pins are configured as inputs,
asserting a GPIO input (high or low, depending on polarity)
sets the corresponding GPIO status bit in Status Registers 5
and 6, or Bit 7 of Status Register4 (GPIO16). A chassis
intrusion event sets Bit 6 of Status Register4.
The GPIO and CI status bits, after mask gating, are OR’d
together and OR’d with other interrupt sources to produce
the INT output. GPIO and CI interrupts are not latched and
cannot be cleared by normal interrupt clearing. They can
only be cleared by masking the status bits or by removing the
source of the interrupt.
ENABLING AND CLEARING INTERRUPTSThe INT output is enabled when Bit 1 of Configuration Regis-
ter1 INT_Enable) is high, and Bit 2 (INT_Clear) is low.
INT may be cleared if:Status Register 1 is read. Ideally, if polling the status registers
trying to identify interrupt sources, Status Register1 should
be polled last, since a read of Status Register 1 clears all the
other interrupt status registers.The ADM1026 receives the Alert Response Address (0001 100)
over the SMBus.Bit 2 of Configuration Register 1 is set.
Bidirectional THERM PinThe ADM1026 has a second interrupt pin (GPIO16/THERM,
Pin 42) that responds only to critical thermal events. The THERM
pin goes low whenever a THERM limit is exceeded. This function
is useful for CPU throttling or system shutdown. In addition,
whenever THERM is activated, the PWM and DAC outputs go
full scale to provide failsafe system cooling. This output is enabled
by setting Bit 4 of Configuration Register1 (Regular 00h). When-
ever a THERM limit gets exceeded, Bit3 of Status Register4
START OF ANALOG
MONITORING
CYCLE
OUT-OF-LIMIT
MEASUREMENT
INT
LOCAL
TEMPERATURE
MEASUREMENT
START OF ANALOG
MONITORING
CYCLE
FULL MONITORING CYCLE = 273ms
LOCAL TEMPERATURE
MEASUREMENTFigure20.Delay After Clearing INT Before Re-Assertion
START OF ANALOG
MONITORING CYCLE
OUT-OF-LIMIT
MEASUREMENT
LOCAL TEMPEREATURE
MEASUREMENT
START OF ANALOG
MONITORING CYCLE
LOCAL TEMPERATURE
MEASUREMENT
START OF ANALOG
MONITORING CYCLE
NEW INT
FROM FAN
NEW INT
FROM GPIO
INT
INT
CLEAREDFigure21.Other Interrupt Sources Can Re-Assert INT Immediately
