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AH0019CD ,Dual DPST-TTL/DTL Compatible MOS Analog SwitchesFeaturesries is available in hermetic dual-in-line package.YgLarge analog voltage switching 10VThes ..
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AH0019CD ,Dual DPST-TTL/DTL Compatible MOS Analog SwitchesAH0014/AH0014CDPDT,AH0015/AH0015CQuadSPST,AH0019/AH0019CDualDPST-TTL/DTLCompatibleMOSAnalogSwitches ..
ADL5390ACPZ-REEL7
10MHz to 2.7GHz RF Vector Multiplier
RF/IF Vector Multiplier
Rev. 0
FEATURES
Matched pair of multiplying VGAs
Broad frequency range 20 MHz to 2.4 GHz
Continuous magnitude control from +5 dB to −30 dB
Output third-order intercept 24 dBm
Output 1 dB compression point 11 dBm
Output noise floor −148 dBm/Hz
Adjustable modulation bandwidth up to 230 MHz
Fast output power disable
Single-supply voltage 4.75 V to 5.25 V
APPLICATIONS
PA linearization and predistortion
Amplitude and phase modulation
Variable matched attenuator and/or phase shifter
Cellular base stations
Radio links
Fixed wireless access
Broadband/CATV
RF/IF analog multiplexer
FUNCTIONAL BLOCK DIAGRAM
VPS2OBBMQBBP
INPI
INMI
DSOPIBBMIBBP
RFOP
RFOMVPRF
CMOP
INMQ
INPQ
CMRF
Figure 1.
GENERAL DESCRIPTION The ADL5390 vector multiplier consists of a matched pair of
broadband variable gain amplifiers whose outputs are summed.
The separate gain controls for each amplifier are linear-in-
magnitude. If the two input RF signals are in quadrature, the
vector multiplier can be configured as a vector modulator or as
a variable attenuator/phase shifter by using the gain control pins
as Cartesian variables. In this case, the output amplitude can be
controlled from a maximum of +5 dB to less than –30 dB, and
the phase can be shifted continuously over the entire 360°
range. Since the signal paths are linear, the original modulation
on the inputs is preserved. If the two signals are independent,
then the vector multiplier can function as a 2:1 multiplexer or
can provide fading from one channel to another.
The ADL5390 operates over a wide frequency range of 20 MHz
to 2400 MHz. For a maximum gain setting on one channel at
380 MHz, the ADL5390 delivers an OP1dB of 11 dBm, an OIP3
of 24 dBm, and an output noise floor of −148 dBm/Hz. The gain
and phase matching between the two VGAs is better than 0.5 dB
and 1°, respectively, over most of the operating range.
The gain control inputs are dc-coupled with a +/−500 mV dif-
ferential full-scale range centered about a 500 mV common
mode. The maximum modulation bandwidth is 230 MHz,
which can be reduced by adding external capacitors to limit the
noise bandwidth on the control lines.
Both the RF inputs and outputs can be used differentially or
single-ended and must be ac-coupled. The impedance of each
VGA RF input is 250 Ω to ground, and the differential output
impedance is nominally 50 Ω over the operating frequency
range. The DSOP pin allows the output stage to be disabled
quickly to protect subsequent stages from overdrive. The
ADL5390 operates off supply voltages from 4.75 V to 5.25 V
while consuming 135 mA.
The ADL5390 is fabricated on Analog Devices’ proprietary,
high performance 25 GHz SOI complementary bipolar IC
process. It is available in a 24-lead, Pb-free CSP package and
operates over a −40°C to +85°C temperature range. Evaluation
boards are available.
TABLE OF CONTENTS Specifications.....................................................................................3
Absolute Maximum Ratings............................................................5
ESD Caution..................................................................................5
Pin Configuration and Function Descriptions.............................6
Typical Performance Characteristics.............................................7
General Structure...........................................................................11
Theory of Operation..................................................................11
Noise and Distortion..................................................................11
Applications.....................................................................................12
Using the ADL5390....................................................................12
RF Input and Matching..............................................................12
RF Output and Matching..........................................................13
Driving the I-Q Baseband Gain Controls...............................13
Interfacing to High Speed DACs..............................................14
Generalized Modulator.............................................................15
Vector Modulator.......................................................................15
Vector Modulator Example—CDMA2000.............................15
Quadrature Modulator..............................................................17
RF Multiplexer............................................................................18
Evaluation Board............................................................................19
Outline Dimensions.......................................................................23
Ordering Guide..........................................................................23
REVISION HISTORY
10/04—Revision 0: Initial Version SPECIFICATIONS VS = 5 V, TA = 25°C, ZO = 50 Ω, FRF = 380 MHz, single-ended source drive to INPI and INPQ, and INMI and INMQ are ac-coupled to
common, unless otherwise noted. 66.5 Ω termination resistors before ac-coupling capacitors on INPI and INPQ. The specifications refer
to one active channel with the other channel input terminated in 50 Ω. The common-mode level for the gain control inputs is 0.5 V. A
maximum gain setpoint of 1.0 refers to a differential gain control voltage of 0.5 V.
Table 1.
ABSOLUTE MAXIMUM RATINGS
Table 2. Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational sec-
tion of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
TOP VIEW
(Not to Scale)
ADL5390
VPRF
QFLP
QFLM
QBBP
QBBM
VPS2
VPRF
IFLP
IFLM
IBBP
IBBM
DSOPCMRFINPQINMQINMIINPICMRF
CMOPCMOP
RFOP
RFOMCMOPCMOP
Figure 2. LFCSP Pin Configuration
Table 3. Pin Function Descriptions TYPICAL PERFORMANCE CHARACTERISTICS
GAIN (dB)
GAIN SETPOINTFigure 3. Gain Magnitude vs. Gain Setpoint, RF Frequency = 70 MHz,
140 MHz, 380 MHz, 900 MHz, 2400 MHz (Channel I or Channel Q)
GAIN (
GAIN SETPOINTFigure 4. Gain Magnitude vs. Gain Setpoint, Temp = +85°C, +25°C, −40°C,
RF Frequency = 380 MHz (Channel I or Channel Q)
0.250.500.751.0
GAIN E
RROR (dB)
GAIN SETPOINTFigure 5. Gain Conformance Error vs. Gain Setpoint, RF Frequency = 70 MHz,
140 MHz, 380 MHz, 900 MHz, 2400 MHz
030060090012001500180021002400
CHANNE
L GAI
MATCH (dB)
FREQUENCY (MHz)Figure 6. Channel Gain Matching (I to Q) vs. RF Frequency,
Gain Setpoint = 1.0
GAIN (
FREQUENCY (MHz)Figure 7. Channel Gain vs. RF Frequency, Temp = +85°C, +25°C, −40°C,
Gain Setpoint = 1.0
0.250.500.751.0
SE ER
egrees)
GAIN SETPOINTFigure 8. Single-Channel Phase Deviation vs. Gain Setpoint, Normalized to
Gain Setpoint = 1.0, RF Frequency = 70 MHz, 140 MHz, 380 MHz,
900 MHz, 2400 MHz
SE D
IFFER
egrees)
GAIN SETPOINTFigure 9. Channel-to-Channel Phase Matching vs. Gain Setpoint,
RF Frequency = 70 MHz, 140 MHz, 380 MHz, 900 MHz, 2400 MHz
SE D
IFFER
egrees)600120018002400
FREQUENCY (MHz)Figure 10. Channel-to-Channel Phase Matching vs. RF Frequency, Temp =
+85°C, +25°C, −40°C, Gain Setpoint = 1.0
NOIS
(dBm/Hz)0.10.20.30.40.50.60.70.80.91.0
GAIN SETPOINTFigure 11. Output Noise Floor vs. Gain Setpoint, No RF Carrier,
RF Frequency = 70 MHz, 140 MHz, 380 MHz, 900 MHz, 2400 MHz
NOIS
(dBm/Hz)0.10.20.30.40.50.60.70.80.91.0
GAIN SETPOINTFigure 12. Output Noise Floor vs. Gain Setpoint, No Carrier, with Carrier
(20 MHz Offset), RF PIN = −5, −10, −15, No Carrier, RF Frequency = 380 MHz
NOIS
(dBm/Hz)4008001200160020002400
FREQUENCY (MHz)
Figure 13. Output Noise Floor vs. RF Frequency, Gain Setpoint = 1.0,
No RF Carrier
FREQUENCY(MHz)
GAINFigure 14. Gain vs. RF Frequency, Gain Setpoint = 1.0, 0.5, 0.1
RF OUTP
UT S
IDE
BAND P
R (dBm)
DIFF. BASEBAND INPUT LEVEL (mV p-p)Figure 15. Baseband Harmonic Distortion, (Channel I and Channel Q),
RF PIN = −5 dBm, (Balun and Cable Losses Not Included)
4008001200160020002400
FREQUENCY (MHz)
B (dBm)Figure 16. Output 1 dB Compression Point vs. RF Frequency,
Temp = +85°C, +25°C, −40°C, Gain Setpoint = 1.0
4008001200160020002400
FREQUENCY (MHz)
OIP3 (Figure 17. Output IP3 vs. RF Frequency, Temp = +85°C, +25°C, −40°C,
Gain Setpoint = 1.0
50100150200250300350400
BB FREQUENCY (MHz)
IDE
BAND P
R (dBm)Figure 18. IQ Modulation Bandwidth vs. Baseband Magnitude
GAIN SETPOINT
B (dBm)Figure 19. Output 1 dB Compression vs. Gain Setpoint, RF Frequency =
70 MHz, 140 MHz, 380 MHz, 900 MHz, 2400 MHz
0.10.20.30.40.50.60.70.80.91.0
OIP3 (
Bm)
GAIN SETPOINTFigure 20. Output IP3 vs. Gain Setpoint, RF Frequency = 70 MHz, 140 MHz,
380 MHz, 900 MHz, 2400 MHz
2204206208201020122014201620182020202220FRF (MHz)
INP
T S
HUNT RE
ANCEINP
T S
HUNT CAP
ACITANCE
(pF)
Figure 21. S11 of RF Input (Shunt R/C Representation)
|GRIDZ|IADL5390 SDD2290
ARG(GRIDZ), RADS(S11TERMANGI)
IMPEDANCE CIRCLE
SDD22 NOM WFR DUT 1
S22 NOM WFR
10MHz
2.7GHz
10MHz
Figure 22. S22 of RF Output (Differential and Single-Ended through Balun)
CURRE
NT (mA)
TEMPERATURE (°C)DSOP VOLTAGE (V)
RF OUTP
UT P
R (dBm)
Figure 24. Power Shutdown Attenuation, RF = 380 MHz
TEK RUN ENVELOPE12 AUG 04 16:48:01
CH1 500mVΩ
CH3 2.0VΩ DS
M 10.0ns 5.0GS/s ET 200ps/pt
A CH3 760mVFigure 25. Power Shutdown Response Time, RF = 380 MHz
GENERAL STRUCTURE
THEORY OF OPERATION The simplified block diagram given in Figure 26 shows a
matched pair of variable gain channels whose outputs are
summed and presented to the final output. The RF/IF signals
propagate from the left to the right, while the baseband gain
controls are placed above and below. The proprietary linear-
responding variable attenuators offer excellent linearity, low
noise, and greater immunity from mismatches than other
commonly used methods.
Since the two independent RF/IF inputs can be combined in
arbitrary proportions, the overall function can be termed
“vector multiplication” as expressed by
VOUT = VIRF × (VIBB/VO) + VQRF × (VQBB/VO)
where:
VIRF and VQRF are the RF/IF input vectors.
VIBB and VQBB are the baseband input scalars.
VO is the built-in normalization factor, which is designed to be
0.285 V (1/3.5 V).
The overall voltage gain, in linear terms, of the I and Q channels
is proportional to its control voltage and scaled by the normali-
zation factor, i.e., a full-scale gain of 1.75 (5 dB) for VI (Q)BB of
500 mV. A full-scale voltage gain of 1.75 defines a gain setpoint
of 1.0.
Due to its versatile functional form and wide signal dynamic
range, the ADL5390 can form the core of a variety of useful
functions such as quadrature modulators, gain and phase ad-
justers, and multiplexers. At maximum gain on one channel, the
output 1 dB compression point and noise floor referenced to
50 Ω are 11 dBm and −148 dBm/Hz, respectively. The broad
frequency response of the RF/IF and gain control ports allows
the ADL5390 to be used in a variety of applications at different
frequencies. The bandwidth for the RF/IF signal path extends
from approximately 20 MHz to beyond 2.4 GHz, while the gain
controls signals allow for modulation rates greater than 200 MHz.
Matching between the two gain channels is ensured by careful
layout and design. Since they are monolithic and arranged
symmetrically on the die, thermal and process gradients are
minimized. Typical gain and phase mismatch at maximum gain
are <0.5 dB and <0.5°.
VQBB
Q CHANNEL
BASEBAND INPUT
VIRF,
ICHANNEL
SINGLE-ENDED
OR DIFFERENTIAL
VIBB
OUTPUT
DISABLE
SINGLE-ENDEDOR DIFFERENTIAL
50Ω OUTPUTVQRF,CHANNELSINGLE-ENDED
OR DIFFERENTIAL
I CHANNEL
BASEBAND INPUT
Figure 26. Simplified Architecture of the ADL5390
NOISE AND DISTORTION The signal path for a particular channel of the ADL5390 con-
sists basically of a preamplifier followed by a variable attenuator
and then an output driver. Each subblock contributes some level
of noise and distortion to the desired signal. As the channel gain
is varied, these relative contributions change. The overall effect
is a dependence of output noise floor and output distortion
levels on the gain setpoint.
For the ADL5390, the distortion is always determined by the
preamplifier. At the highest gain setpoint, the signal capacity, as
described by the 1 dB compression point (P1dB) and the third-
order intercept (OIP3), are at the highest levels. As the gain is
reduced, the P1dB and OIP3 are reduced in exact proportion.
At the higher gain setpoints, the output noise is dominated by
the preamplifier as well. At lower gains, the contribution from
the preamplifier is correspondingly reduced and eventually a
noise floor, set by the output driver, is reached. As Figure 27
illustrates, the overall dynamic range defined as a ratio of OIP3
to output noise floor remains constant for the higher gain
setpoints. At some gain level, the noise floor levels off and the
dynamic range degrades commensurate with the gain reduction.
NAMIC RANGE
(dB
Hz)0.10.20.30.40.50.60.70.80.91.0
GAIN SETPOINT04954-027
APPLICATIONS
USING THE ADL5390 The ADL5390 is designed to operate in a 50 Ω impedance system.
Figure 29 illustrates an example where the RF/IF inputs are
driven in a single-ended fashion, while the differential RF out-
put is converted to a single-ended output with a RF balun. The
baseband gain controls for the I and Q channels are typically
driven from differential DAC outputs. The power supplies,
VPRF and VPS2, should be bypassed appropriately with 0.1 µF
and 100 pF capacitors. Low inductance grounding of the CMOP
and CMRF common pins is essential to prevent unintentional
peaking of the gain. The exposed paddle on the underside of the
package should be soldered to a low thermal and electrical
impedance ground plane.
RF INPUT AND MATCHING The RF/IF inputs present 250 Ω resistive terminations to
ground. In general, the input signals should be ac-coupled
through dc-blocking capacitors. The inputs may be driven dif-
ferentially or single-ended, in which case the unused inputs are
connected to common via the dc-blocking capacitors. The
ADL5390’s performance is not degraded by driving these inputs
single-ended. The input impedance can be reduced by placing
external shunt termination resistors to common on the source
side of the dc-blocking capacitors so that the quiescent dc-bias
level of the ADL5390 inputs is not affected, as shown in Figure
29. Capacitive reactance at the RF inputs can be compensated
for with series inductance. In fact, the customer evaluation
board has high impedance line traces between the shunt termi-
nation pads and the device input pins, which provides series in-
ductance and improves the return loss at 1.9 GHz to better than
−15 dB with the shunt termination removed, as shown in Figure
28.
FREQUENCY (MHz)Figure 28. ADL5390 Customer Evaluation Board RF Input Return Loss.
C12
(SEE TEXT)
C11
(SEE TEXT)
100pF
0.1µF
0.1µF
SW1
IBBMIBBP
QBBPQBBM
10nF
RFIN_QR22
66.5Ω
10nF
RFIN_I
66.5Ω
C10
100pF
0.1µF
RFOP4T1
ETC1-1-13
(M/A-COM)
100pF
Figure 29. Basic Connections
