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ADL5330ACPZ-WP
1MHz to 3GHz VGA with 60dB Gain Control Range
Rev. PrK
1 MHz - 3 GHz VGA witha
60dB Gain Control Range FEATURES
Voltage-Controlled Amplifier/Attenuator
Operating Frequency 1 MHz to 3 GHz
Optimized for Controlling Output Power
High Linearity: OIP3 31 dBm @ 900 MHz
Output Noise Floor -150 dBm/Hz @ 900 MHz
Fully-Balanced Differential Signal Path
Differential Input at 50 Ω
Wide Gain-Control Range: -34 dB to +22 dB @ 900 MHz
Linear-in-dB Gain Control Function, 20 mV/dB
Single Supply 4.75 – 6 V
APPLICATIONS
Output Power Control for Wireless Infrastructure
PRODUCT DESCRIPTION The ADL5330 is a high-performance voltage-controlled variable-
gain amplifier/attenuator, for use up to 3 GHz. The signal path is
fully differential; the balanced structure minimizes distortion, and
reduces the risk of spurious feed-forward at low gains and high
frequencies due to substrate coupling. While operation between a
balanced source and load is recommended, a single-sided input is
internally converted to differential from. The input impedance is
50-Ω from INHI to INLO. The outputs will usually be coupled
into a 50-Ω grounded load via a 1:1 balun. However, the output
pins, OPHI and OPLO, may also be used separately, with some
noise degradation. A single supply of 4.75 to 6 V is required.
With a 2140 MHz W-CDMA 3GPP forward path signal, the
ADL5330 is capable of producing greater than –3 dBm output
power while maintaining ACPR greater than 55 dB, and an output
noise floor less than -144 dBm/Hz.
Three cascaded sections are used. The 50-Ω input system converts the
applied voltage to a pair of differential currents with high linearity and
good common rejection if driven by a single-sided source. The signal
currents are then applied to a proprietary voltage-controlled attenuator,
which provides precise definition of the overall gain, under the control
of the Linear-in-dB interface. Pin GAIN accepts a voltage from 0 V at
minimum gain to 1.4 V at full gain. The scaling factor is 20 mV/dB.
Optional external control of the input-stage and/or output-stage biasing
is provided using pins IPBS and OPBS respectively.
The output of the high-accuracy wideband attenuator is applied to a
differential trans-impedance output stage. Higher output power is
attainable at the lower operating frequencies by raising the supply
voltage to 6 V. When powered-down by a logic LO input on the ENBL
pin, the current consumption is < TBD µA.
The ADL5330 is available in a 24-lead (4 x 4mm) CSP package and is
specified for operation from ambient temperatures of −40°C to +85°C.
Multiple Patents Pending
ADL5330 SPECIFICATIONS Table 1. VS = 5 V; TA = 25°C; 800 MHz < f < 2.2GHz.1:1 balun at input and output for single-ended 50 Ω match
Table 2. Pin Function Description Figure 2. ADL5330 Evaluation Board Schematic
Typical Performance Characteristics
Vgain - Volts
rro
r -
Vgain - VFigure 3. Gain and Gain Law Conformance vs. Vgain Figure 5. OIP3 vs. Gain 0.20.40.60.811.21.41.6
Vgain - V
Inp
t R
efe
rre
d P
1dB - dBVgain - V
tput
1dB
- dB
Figure 4. Input Referred Compression Point vs. Gain Figure 7. Output Referred Compression Point vs. Gain
VGAIN
ut P
er -
e - 2
0 M
z Ca
rrier O
ffse
t - d
/Hz
VGAIN
ise -
20 M
z C
arrie
r O
ffsetFigure 8. Pout and Noise Floor vs. Gain, 900 MHz. Pin = -21 dBm Figure 8. Pout and Noise Floor vs. Gain 1.9 GHz. Pin = -22 dBm
OUTLINE DIMENSIONS
:
www.ic-phoenix.com
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