ADG752BRM Fast Delivery |IC PHOENIX CO.,LIMITED

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ADG752BRM
CMOS, Low Voltage RF/Video, SPDT Switch
REV. 0
FUNCTIONAL BLOCK DIAGRAM
CMOS, Low Voltage
RF/Video, SPDT Switch
SWITCH SHOWN FOR A LOGIC "1" INPUT
FEATURES
High Off Isolation –80 dB at 30 MHz
–3 dB Signal Bandwidth 250 MHz
+1.8 V to +5.5 V Single Supply
Low On-Resistance (15 V Typically)
Low On-Resistance Flatness
Fast Switching Times
tON Typically 8 ns
tOFF Typically 3 ns
Typical Power Consumption < 0.01 mW
TTL/CMOS Compatible
APPLICATIONS
Audio and Video Switching
RF Switching
Networking Applications
Battery Powered Systems
Communication Systems
Relay Replacement
Sample-and-Hold Systems
GENERAL DESCRIPTION
The ADG752 is a low voltage SPDT (single pole, double throw)
switch. It is constructed using switches in a T-switch configura-
tion, which results in excellent Off Isolation while maintaining
good frequency response in the ON condition.
High off isolation and wide signal bandwidth make this part
suitable for switching RF and video signals. Low power con-
sumption and operating supply range of +1.8 V to +5.5 V make
it ideal for battery powered, portable instruments.
The ADG752 is designed on a submicron process that provides
low power dissipation yet gives high switching speed and low on
resistance. This part is a fully bidirectional switch and can handle
signals up to and including the supply rails. Break-before-make
switching action ensures the input signals are protected against
momentary shorting when switching between channels.
The ADG752 is available in 6-lead SOT-23 and 8-lead mSOIC
packages.
PRODUCT HIGHLIGHTSHigh Off Isolation –80 dB at 30 MHz.–3 dB Signal Bandwidth 250 MHz.Low On Resistance (15 W).Low Power Consumption, typically <0.01 mW.Break-Before-Make Switching Action.Tiny 6-lead SOT-23 and 8-lead mSOIC packages.
ADG752–SPECIFICATIONS(VDD = +5 V 6 10%, GND = 0 V, unless otherwise noted.)
DYNAMIC CHARACTERISTICS
POWER REQUIREMENTS
NOTESGuaranteed by design, not subject to production test.
Specifications subject to change without notice.
ADG752(VDD = +3 V 6 10%, GND = 0 V, unless otherwise noted.)
DYNAMIC CHARACTERISTICS
POWER REQUIREMENTS
NOTESGuaranteed by design, not subject to production test.
Specifications subject to change without notice.
SPECIFICATIONS
ADG752
Table I.Truth Table
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
ABSOLUTE MAXIMUM RATINGS1
(TA = +25°C unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +6 V
Analog, Digital Inputs2 . . . . . . . . . . . .–0.3 V to VDD +0.3 V or
30 mA, Whichever Occurs First
Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . .100 mA
(Pulsed at 1 ms, 10% Duty Cycle Max)
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . .30 mA
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . .–40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . .(TJ Max–TA)/qJA
Junction Temperature (TJ Max) . . . . . . . . . . . . . . . . . .+150°CSOIC Package
qJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . .206°C/W
qJC Thermal Impedance . . . . . . . . . . . . . . . . . . . . . .44°C/W
SOT-23 Package
qJA Thermal Impedance . . . . . . . . . . . . . . . . . . . .229.6°C/W
qJC Thermal Impedance . . . . . . . . . . . . . . . . . . . .91.99°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability. Only one absolute maxi-
mum rating may be applied at any one time.Overvoltages at IN, S or D will be clamped by internal diodes. Current should be
limited to the maximum ratings given.
ORDERING GUIDE
*Brand on these packages is limited to three characters due to space constraints.
TERMINOLOGY
PIN CONFIGURATIONS
6-Lead SOT-23
(RT-6)
VDD
GND
8-Lead mSOIC
(RM-8)
NC = NO CONNECT
VDDS2
GND
VD OR VS DRAIN SOURCE VOLTAGE – Volts01
– 45
5.5
Figure 1.On Resistance as a Function of VD (VS) Single
Supplies
VD OR VS DRAIN SOURCE VOLTAGE – Volts00.5
–
VDD = +3V
Figure 2.On Resistance as a Function of VD (VS) for
Different Temperatures VDD = 3 V
VD OR VS DRAIN SOURCE VOLTAGE – Volts
– 0
Figure 3.On Resistance as a Function of VD (VS) for
Different Temperatures VDD = 5 V
FREQUENCY – Hz
10n
IDD
– Amps10k
100n
10m
10m
100k100M10M
Figure 4.Supply Current vs. Input Switching Frequency
FREQUENCY – MHz
OFF ISOLATION – dB1
–40
Figure 5.Off Isolation vs. Frequency
FREQUENCY – MHz
CROSSTALK – dB
–100
Figure 6.Crosstalk vs. Frequency
ADG752
FREQUENCY – MHz
ATTENUATION – dB1
Figure 7.On Response vs. Frequency
GENERAL DESCRIPTION
The ADG752 is an SPDT switch constructed using switches in
a T configuration to obtain high “OFF” isolation while main-
taining good frequency response in the “ON” condition.
Figure 8 shows the T-switch configuration. While the switch is
in the OFF state, the shunt switch is closed and the two series
switches are open. The closed shunt switch provides a signal
path to ground for any of the unwanted signals that find their
way through the off capacitances of the series’ MOS devices.
This results in more improved isolation between the input and
output than with an ordinary series switch. When the switch is
in the ON condition, the shunt switch is open and the signal
path is through the two series switches which are now closed.
Figure 8.Basic T-Switch Configuration
LAYOUT CONSIDERATIONS
Where accurate high frequency operation is important, careful
consideration should be given to the printed circuit board layout
and to grounding. Wire wrap boards, prototype boards and
sockets are not recommended because of their high parasitic
inductance and capacitance. The part should be soldered di-
rectly to a printed circuit board. A ground plane should cover all
unused areas of the component side of the board to provide a
low impedance path to ground. Removing the ground planes
from the area around the part reduces stray capacitance.
Good decoupling is important in achieving optimum perfor-
mance. VDD should be decoupled with a 0.1 mF surface mount
capacitor to ground mounted as close as possible to the device
itself.
VDD
ADG752
75VVOUT
75V
CH1
CH2
250V
250V
75V
75V
Figure 9.Multiplexing Between Two Video Signals

Partno	Mfg	Dc	Qty	Available	Descript
ADG752BRM	AD	N/a	1445	avai	CMOS, Low Voltage RF/Video, SPDT Switch