ADG732 ,32-Channel, Serially Controlled 3.5 Ohm 1.8 V to 5.5 V, ?.5 V, Analog MultiplexerCHARACTERISTICSt 34 ns typ R = 300 Ω , C = 35 pF; Test Circuit 5TRANSITION L L52 62 ns max V = 2 V/ ..
ADG732BSU ,16-/32- Channel, 3.5 з 1.8 V to 5.5 V, ?.5 V, Analog MultiplexersGENERAL DESCRIPTIONand have an input signal range which extends to the sup-The ADG726/ADG732 are mo ..
ADG732BSUZ , 16-/32-Channel, 4 1.8 V to 5.5 V, 2.5 V Analog Multiplexers
ADG732BSUZ , 16-/32-Channel, 4 1.8 V to 5.5 V, 2.5 V Analog Multiplexers
ADG733BRQ ,CMOS, 2.5 ohm Low Voltage, Triple/Quad SPDT SwitchesCHARACTERISTICSt 19 ns typ R = 300 Ω , C = 35 pF;ON L L34 ns max V = 3 V, Test Circuit 4St 7 ns typ ..
ADG733BRU ,CMOS, 2.5 ohm Low Voltage, Triple/Quad SPDT SwitchesSPECIFICATIONS B Version–40CParameter 25C to +85C Unit Test Conditions/Comments ANALOG SWITCH ..
AFS600-FGG256 , Fusion Family of Mixed Signal FPGAs
AG201-86 , InGaP HBT Gain Block
AG201-86 , InGaP HBT Gain Block
AG302-86G , InGaP HBT Gain Block
AG303-86 , InGaP HBT Gain Block
AG402-86 , InGaP HBT Gain Block
ADG732
16-/32- Channel, 3.5 ohms 1.8 V to 5.5 V, ?.5 V, Analog Multiplexer
REV.0
16-/32-Channel, 4 �
+1.8 V to +5.5 V, �2.5 V Analog Multiplexers
FEATURES
1.8 V to 5.5 V Single Supply�2.5 V Dual-Supply Operation
4 � On Resistance
0.5 � On Resistance Flatness
48-Lead TQFP or 48-Lead 7 mm � 7 mm CSP Packages
Rail-to-Rail Operation
30 ns Switching Times
Single 32-to-1 Channel Multiplexer
Dual/Differential 16-to-1 Channel Multiplexer
TTL/CMOS Compatible Inputs
For Functionally Equivalent Devices with Serial Interface
See ADG725/ADG731
APPLICATIONS
Optical Applications
Data Acquisition Systems
Communication Systems
Relay Replacement
Audio and Video Switching
Battery-Powered Systems
Medical Instrumentation
Automatic Test Equipment
FUNCTIONAL BLOCK DIAGRAMS
PRODUCT HIGHLIGHTS+1.8 V to +5.5 V single- or ±2.5 V dual-supply operation.
These parts are specified and guaranteed with +5 V ± 10%,
+3 V ± 10% single-supply, and ±2.5 V ± 10% dual-
supply rails.On resistance of 4 ΩGuaranteed break-before-make switching action7 mm × 7 mm 48-lead chip scale package (CSP)
or 48-lead TQFP package
GENERAL DESCRIPTIONThe ADG726/ADG732 are monolithic CMOS 32-channel/dual
16-channel analog multiplexers. The ADG732 switches one of
32 inputs (S1-S32) to a common output, D, as determined by
the 5-bit binary address lines A0, A1, A2, A3, and A4. The
ADG726 switches one of 16 inputs as determined by the 4-bit
binary address lines A0, A1, A2, and A3.
On-chip latches facilitate microprocessor interfacing. The
ADG726 device may also be configured for differential opera-
tion by tying CSA and CSB together. An EN input is used to
enable or disable the devices. When disabled, all channels are
switched OFF.
These multiplexers are designed on an enhanced submicron
process that provides low power dissipation yet gives high
switching speed, very low on resistance, and leakage currents.
They operate from a single supply of +1.8 V to +5.5 V and a ±2.5 V
dual supply, making them ideally suited to a variety of applications.
On resistance is in the region of a few ohms and is closely
matched between switches and very flat over the full signal
range. These parts can operate equally well as either multiplexers
or demultiplexers and have an input signal range that extends to
the supplies. In the OFF condition, signal levels up to the supplies
are blocked. All channels exhibit break-before-make switching
action, preventing momentary shorting when switching channels.
They are available in either 48-lead CSP or TQFP packages.
ADG726/ADG732–SPECIFICATIONS1
(VDD = 5 V � 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.)LEAKAGE CURRENTS
DYNAMIC CHARACTERISTICS
NOTESTemperature range is as follows: B Version: –40°C to +85°C.Guaranteed by design; not subject to production test.
Specifications subject to change without notice.
ADG726/ADG732LEAKAGE CURRENTS
IDD
NOTESTemperature ranges are as follows: B Version: –40°C to +85°C.
SPECIFICATIONS1
(VDD = 3 V � 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.)
NOTES
ADG726/ADG732 SPECIFICATIONS1
(VDD = +2.5 V � 10%, VSS = –2.5 V � 10%, GND = 0 V, unless otherwise noted.)DUAL SUPPLY
TIMING CHARACTERISTICS1,2,3NOTESSee Figure 1.All input signals are specified with tr =tf = 1 ns (10% to 90% of VDD).Guaranteed by design and characterization, not production tested.
Specifications subject to change without notice.
Figure 1. Timing Diagram
Figure 1 shows the timing sequence for latching the switch
address and enable inputs. The latches are level sensitive; there-
fore, while WR is held low, the latches are transparent and the
switches respond to changing the address and enable the inputs.
Input data is latched on the rising edge of WR. The ADG726
has two CS inputs. This enables the part to be used either as a
dual 16-1 channel multiplexer or a differential 16-channel
multiplexer. If a differential output is required, tie CSA and
CSB together.
ADG726/ADG732
PIN CONFIGURATIONS
LFCSP and TQFP
ABSOLUTE MAXIMUM RATINGS1(TA = 25°C, unless otherwise noted.)
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 V
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . .+0.3 V to –7 V
Analog Inputs2 . . . . . . . . . . . . . .VSS – 0.3 V to VDD + 0.3 V or
30 mA, Whichever Occurs First
Digital Inputs2 . . . . . . . . . . . . . . . . . .–0.3 V to VDD + 0.3 V or
30 mA, Whichever Occurs First
Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . .60 mA
(Pulsed at 1 ms, 10% Duty Cycle Max)
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . .30 mA
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . .–40°C to +85°C
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADG726/ADG732 features proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . .150°C
Thermal Impedence (Four-layer board)
48-Lead LFCSP . . . . . . . . . . . . . . . . . . . . . . . . . . .25�C/W
48-Lead TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . .54.6�C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . .300°C
IR Reflow, Peak Temperature (<20 sec) . . . . . . . . . . . .235°C
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
2Overvoltages at A, EN, WR, CS, S, or D will be clamped by internal diodes.
Current should be limited to the maximum ratings given.
ORDERING GUIDE
