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ADG726BCP-ADG732BSU
16-/32- Channel, 3.5 з 1.8 V to 5.5 V, ?.5 V, Analog Multiplexers
�REV. PrD 2001
16-/32- Channel, 3.5 ΩΩΩΩΩ
1.8 V to 5.5 V, ±2.5 V, Analog Multiplexers
PRELIMINARY TECHNICAL DATA
FEATURES
1.8 V to 5.5 V Single Supply
±2.5 V Dual Supply Operation
3.5 ΩΩΩΩΩ On Resistance
0.5 ΩΩΩΩΩ On Resistance Flatness
Rail to Rail Operation
30ns Switching Times
Single 32 to 1 Channel Multiplexer
Dual/Differential 16 to 1 Channel Multiplexer
TTL/CMOS Compatible Inputs
For Functionally Equivalent devices with Serial Interface
See ADG725/ADG731
APPLICATIONS
Optical Applications
Data Acquisition Systems
Communication Systems
Relay replacement
Audio and Video Switching
Battery Powered Systems
Medical Instrumentation
Automatic Test Equipment
GENERAL DESCRIPTIONThe ADG726/ADG732 are monolithic CMOS 32
channel/dual 16 channel analog multiplexers. The
ADG732 switches one of thirty-two inputs (S1-S32) to a
common output, D, as determined by the 5-bit binary
address lines A0, A1, A2, A3 and A4. The ADG726
switches one of sixteen inputs as determined by the four
bit binary address lines, A0, A1, A2 and A3.
On chip latches facilitate microprocessor interfacing. The
ADG726 device may also be configured for differential
operation by tying CSA and CSB together. An �� input
is used to enable or disable the devices. When disabled, all
channels are switched OFF.
These multiplexers are designed on an enhanced submi-
cron process that provides low power dissipation yet gives
high switching speed, very low on resistance and leakage
currents. They operate from single supply of 1.8V to 5.5V
and ±2.5 V dual supply, making them ideally suited to a
variety of applications. On resistance is in the region of a
few Ohms and is closely matched between switches and
very flat over the full signal range. These parts can operate
equally well as either Multiplexers or De-Multiplexers
PRODUCT HIGHLIGHTS+1.8 V to +5.5 V Single or ±2.5 V Dual Supply
operation. These parts are specified and guaranteed
with +5 V ±10%, +3 V ±10% single supply and
±2.5 V ±10% dual supply rails.On Resistance of 3.5 Ω.Guaranteed Break-Before-Make Switching Action.7mm x 7mm 48 lead LF Chip Scale Package (CSP)
or 48 lead TQFP package.
FUNCTIONAL BLOCK DIAGRAMSand have an input signal range which extends to the sup-
plies. In the OFF condition, signal levels up to the
supplies are blocked. All channels exhibit break before
make switching action preventing momentary shorting
when switching channels.
They are available in either 48 lead LFCSP or TQFP
package.
ADG726/ADG732–SPECIFICATIONS1
PRELIMINARY TECHNICAL DATANOTESTemperature range is as follows: B Version: –40°C to +85°C.Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
(VDD = 5V ± 10%, VSS = 0V, GND = 0 V, unless otherwise noted)
ADG726/ADG732
PRELIMINARY TECHNICAL DATANOTESTemperature ranges are as follows: B Version: –40°C to +85°C.Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
(VDD = 3V ± 10%, VSS = 0V, GND = 0 V, unless otherwise noted)SPECIFICATIONS1
ADG726/ADG732–SPECIFICATIONS1
PRELIMINARY TECHNICAL DATANOTESTemperature range is as follows: B Version: –40°C to +85°C.Guaranteed by design, not subject to production test.
(VDD = +2.5 V ±10%, VSS = -2.5 V ±10%, GND = 0 V, unless otherwise noted)Dual Supply
ADG726/ADG732
PRELIMINARY TECHNICAL DATA
TIMING CHARACTERISTICS1,2, 3
ParameterLimit at TMIN, TMAXUnitsConditions/Comments0ns min�� to �� Setup Time0ns min�� to �� Hold Time20ns min�� pulse width10ns minTime between �� cycles5ns minAddress, Enable Setup Time2ns minAddress, Enable Hold Time
NOTESSee Figure 1.All input signals are specified with tr =tf = 5ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.Guaranteed by design and characterisation, not production tested.
Specifications subject to change without notice.
Figure 1. Timing Diagram
Figure 1 shows the timing sequence for latching the switch address and enable inputs. The latches are level sensitive;
therefore, while �� is held low, the latches are transparent and the switches respond to the address and enable inputs.
This input data is latched on the rising edge of ��. The ADG726 has two �� inputs. This enables the part to be used
either as a dual 16-1 channel multiplexer or a differential 16 channel multiplexer. If a differential output is required, tie
��� and ��� together.
ADG726/ADG732
PRELIMINARY TECHNICAL DATA
ABSOLUTE MAXIMUM RATINGS1(TA = +25°C unless otherwise noted)
VDD to VSS+7 V
VDD to GND–0.3 V to +7 V
VSS to GND+0.3 V to -7 V
Analog Inputs2VSS - 0.3 V to VDD +0.3 Vor
30 mA, Whichever Occurs First
Digital Inputs2-0.3V to VDD +0.3 V or
30 mA, Whichever Occurs First
Peak Current, S or D60mA
(Pulsed at 1 ms, 10% Duty Cycle max)
Continuous Current, S or D30mA
Operating Temperature Range
Industrial (B Version)–40°C to +85°C
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADG726/ADG732 features proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
Storage Temperature Range–65°C to +150°C
Junction Temperature+150°C
48 lead CSP θJA Thermal ImpedanceTBD°C/W
48 lead TQFP θJA Thermal ImpedanceTBD°C/W
Lead Temperature, Soldering (10seconds)300°C
IR Reflow, Peak Temperature+220°C
NOTESStresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only and functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Only one absolute maximum rating may
be applied at any one time.Overvoltages at A, ��, ��, S or D will be clamped by internal diodes. Current should
be limited to the maximum ratings given.
ORDERING GUIDE
PIN CONFIGURATIONS
CSP & TQFP
PIN 1
INDICATOR
TOP VIEW
ADG732
S12
S11
S10
NC = NO CONNECT
13
14
A0 15A1 16A2 17A3 1
A4 19
CS 20
WR 21
EN 22
24
36 S28
35 S27
34 S26
33 S25
32 S24
31 S23
30 S22
29 S21
28 S20
27 S19
26 S18
25 S17
48 S1347 S1446 S1545 S1644 NC43 D42 NC41 NC40 S3239 S3138 S3037 S29
PIN 1
INDICATOR
TOP VIEW
ADG726S12AS11AS10AS9AS8AS7AS6AS5AS4AS3AS2AS1A
NC = NO CONNECT
13
14
A0 15A1 16A2 17A3 1
CSA 19CSB 20
WR 21
EN 22
24
36 S12B
35 S11B
34 S10B
33 S9B
32 S8B
31 S7B
30 S6B
29 S5B
28 S4B
27 S3B
26 S2B
25 S1B
48 S13A47 S14A46 S15A45 S16A44 NC43 D
42 NC41 DB
40 S16B39 S15B38 S14B37 S13B
PRELIMINARY TECHNICAL DATA
Table 2. ADG732 Truth TableA3A2A1A0������
Switch ConditionXXXXX1L->HRetains previous switch conditionXXXXX1XNo Change in Switch ConditionXXXX100NONE000000010001000200100003001100040100000501010006011000070111000810000009100100010101000011101100012110000013110100014111000015111100016000000017000100018001000019001100020010000021010100022011000023011100024100000025100100026101000027101100028
Table 1. ADG726 Truth TableA2A1A0����������
ON SwitchXXXX11L->HRetains previous switch conditionXXXX11XNo Change in Switch conditionXXX1000NONE0000000S1A - DA, S1B - DB0010000S2A - DA, S2B - DB0100000S3A - DA, S3B - DB0110000S4A - DA, S4B - DB1000000S5A - DA, S5B - DB1010000S6A - DA, S6B - DB1100000S7A - DA, S7B - DB1110000S8A - DA, S8B - DB0000000S9A - DA, S9B - DB0010000S10A - DA, S10B - DB0100000S11A - DA, S11B - DB0110000S12A - DA, S12B - DB1000000S13A - DA, S13B - DB1010000S14A - DA, S14B - DB1100000S15A - DA, S15B - DB1110000S16A - DA, S16B - DB
