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ADG725BCP
16-/32- Channel, Serially Controlled 4 з 1.8 V to 5.5 V, ?.5 V, Analog Multiplexers
�REV. PrD May 2002
16-/32- Channel, Serially Controlled 4 ΩΩΩΩΩ
1.8 V to 5.5 V, ±2.5 V, Analog Multiplexers
PRELIMINARY TECHNICAL DATA
FEATURES
3-Wire SPI Serial Interface
1.8 V to 5.5 V Single Supply
±2.5 V Dual Supply Operation
4 ΩΩΩΩΩ On Resistance
0.5 ΩΩΩΩΩ On Resistance Flatness
7mm x 7mm 48 lead Chip Scale Package (CSP)
or 48 lead TQFP package.
Rail to Rail Operation
Power On Reset
Fast Switching Times
Single 32 to 1 Channel Multiplexer
Dual/Differential 16 to 1 Channel Multiplexer
TTL/CMOS Compatible Inputs
For Functionally Equivalent devices with Parallel Interface
See ADG726/ADG732
APPLICATIONS
Optical Applications
Data Acquisition Systems
Communication Systems
Relay replacement
Audio and Video Switching
Battery Powered Systems
Medical Instrumentation
Automatic Test Equipment
GENERAL DESCRIPTIONThe ADG725/ADG731 are monolithic CMOS 32
channel/dual 16 channel analog multiplexers with a
serially controlled 3-wire interface. The ADG732 switches
one of thirty-two inputs (S1-S32) to a common output, D.
The ADG725 can be configured as a dual mux switching
one of sixteen inputs to one output or a differential mux
switching one of sixteen inputs to a differential output.
These mulitplexers utilize a 3-wire serial interface that is
compatible with SPITM, QSPITM, MICROWIRETM and
some DSP interface standards. On power-up, the internal
shift register contains all zeros and all switch are in the
OFF state.
These multiplexers are designed on an enhanced submi-
cron process that provides low power dissipation yet gives
high switching speed, very low on resistance and leakage
currents. They operate from single supply of 1.8V to 5.5V
and ±2.5 V dual supply, making them ideally suited to a
variety of applications. On resistance is in the region of a
few Ohms and is closely matched between switches and
very flat over the full signal range. These parts can operate
equally well as either Multiplexers or De-Multiplexers
PRODUCT HIGHLIGHTS3-Wire Serial Interface.+1.8 V to +5.5 V Single or ±2.5 V Dual Supply
operation. These parts are specified and guaranteed
with +5 V ±10%, +3 V ±10% single supply and
±2.5 V ±10% dual supply rails.On Resistance of 4 Ω.Guaranteed Break-Before-Make Switching Action.7mm x 7mm 48 lead Chip Scale Package (CSP)
or 48 lead TQFP package.
FUNCTIONAL BLOCK DIAGRAMSand have an input signal range which extends to the sup-
plies. In the OFF condition, signal levels up to the
supplies are blocked. All channels exhibit break before
make switching action preventing momentary shorting
when switching channels.
They are available in either 48 lead CSP or TQFP
package.
ADG725/ADG731–SPECIFICATIONS1
PRELIMINARY TECHNICAL DATANOTESTemperature range is as follows: B Version: –40°C to +85°C.Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
(VDD = 5V ± 10%, VSS = 0V, GND = 0 V, unless otherwise noted)
ADG725/ADG731
PRELIMINARY TECHNICAL DATANOTESTemperature ranges are as follows: B Version: –40°C to +85°C.Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
(VDD = 3V ± 10%, VSS = 0V, GND = 0 V, unless otherwise noted)SPECIFICATIONS1
ADG725/ADG731–SPECIFICATIONS1
PRELIMINARY TECHNICAL DATANOTESTemperature range is as follows: B Version: –40°C to +85°C.Guaranteed by design, not subject to production test.
(VDD = +2.5 V ±10%, VSS = -2.5 V ±10%, GND = 0 V, unless otherwise noted)Dual Supply
ADG725/ADG731
PRELIMINARY TECHNICAL DATA
TIMING CHARACTERISTICS1,2
ParameterLimit at TMIN, TMAXUnitsConditions/Comments33ns minSCLK Cycle time13ns minSCLK High Time13ns minSCLK Low Time13ns min�����to SCLK falling edge setup time40ns minMinimum ���� low time5ns minData Setup Time4.5ns minData Hold Time33ns minMinimum �����high time
NOTESSee Figure 1.All input signals are specified with tr =tf = 5ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
Specifications subject to change without notice.
Figure 1.3-Wire Serial Interface Timing Diagram.
Figure 2. ADG725 Input Shift Register ContentsFigure 3. ADG731 Input Shift Register Contents
ADG725/ADG731
PRELIMINARY TECHNICAL DATA
ABSOLUTE MAXIMUM RATINGS1(TA = +25°C unless otherwise noted)
VDD to VSS+7 V
VDD to GND–0.3 V to +7 V
VSS to GND+0.3 V to -7 V
Analog Inputs2VSS - 0.3 V to VDD +0.3 Vor
30 mA, Whichever Occurs First
Digital Inputs2-0.3V to VDD +0.3 V or
30 mA, Whichever Occurs First
Peak Current, S or D60mA
(Pulsed at 1 ms, 10% Duty Cycle max)
Continuous Current, S or D30mA
Operating Temperature Range
Industrial (B Version)–40°C to +85°C
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADG725/ADG731 features proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
Storage Temperature Range–65°C to +150°C
Junction Temperature+150°C
48 lead CSP θJA Thermal ImpedanceTBD°C/W
48 lead TQFP θJA Thermal ImpedanceTBD°C/W
Lead Temperature, Soldering (10seconds)300°C
IR Reflow, Peak Temperature+220°C
NOTESStresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only and functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Only one absolute maximum rating may
be applied at any one time.Overvoltages at SCLK, ����, DIN����, S or D will be clamped by internal diodes.
Current should be limited to the maximum ratings given.
ORDERING GUIDE
PRELIMINARY TECHNICAL DATA
PIN FUNCTION DESCRIPTION
ADG725ADG731MnemonicFunctionSCLKSerial Clock Input. Data is clocked into the input shift register on the falling edge of
the serial clock input. These devices can accomodate serial input rates of up to
30MHz.Active low control input that clears the input register and turns all switches to the
OFF condition.
DINSerial Data Input. Data is clocked into the 8-bit input register on the falling edge of
the serial clock input.
SXXSource. May be an input or output.Drain. May be an input or output.
VDDPower Supply Input. These parts can be operated from a supply of +1.8V to +5.5V
and dual supply of +/-2.5V.
GNDGround reference.
����Active Low Control Input. This is the frame synchronization signal for the input
data. When ���� goes low, it powers on the SCLK and DIN buffers and the input
shift register is enabled. An 8-bit counter is also enabled. Data is transferred on the
falling edges of the followingclocks. After 8 falling clock edges, switch conditions
are automaticaly updated. ���� may be used to frame the signal, or just pulled low
for a short period of time to enable the counter and input buffers.
PIN CONFIGURATIONS
CSP & TQFP
S28
S27
S26
S25
S24
S23
S22
S12
S11
S10
NC = NO CONNECT
S21
S20
S19
S18S17
S13S14S15S16NCDNCNCS32S31S30S29NCNC
SYNC
DIN
SCLKNCNC
GND
S12B
S11B
S10B
S9B
S8B
S7B
S6B
S12A
S11A
S10A
S9A
S8A
S7A
S6A
NC = NO CONNECT
S5A
S4A
S3A
S2A
S5B
S4B
S3B
S2B
S1AS1B
S13AS14AS15AS16ANCDANCDBS16AS15BS14BS13BNCNC
SYNC
DIN
SCLKNCNC
GND
ADG725/ADG731
PRELIMINARY TECHNICAL DATA
Table 2. ADG731 Truth TableA3A2A1A0����
Switch ConditionXXXXX1Retains previous switch conditionXXXX11All Switches OFF000000100010020010003001100401000050101006011000701110081000009100100101010001110110012110000131101001411100015111100160000001700010018001000190011002001000021010100220110002301110024100000251001002610100027101100281100002911010030
Table 1. ADG725 Truth TableA2A1A0��������
Switch ConditionXXXX11Retains previous switch conditionXXX111All Switches OFF000000S1A - DA, S1B - DB001000S2A - DA, S2B - DB010000S3A - DA, S3B - DB011000S4A - DA, S4B - DB100000S5A - DA, S5B - DB101000S6A - DA, S6B - DB110000S7A - DA, S7B - DB111000S8A - DA, S8B - DB000000S9A - DA, S9B - DB001000S10A - DA, S10B - DB010000S11A - DA, S11B - DB011000S12A - DA, S12B - DB100000S13A - DA, S13B - DB101000S14A - DA, S14B - DB110000S15A - DA, S15B - DB111000S16A - DA, S16B - DB
