ADG715BRU ,CMOS, Low Voltage Serially-Controlled, Octal SPST SwitchesSPECIFICATIONSDD SS B Version–40CParameter +25C to +85C Unit Test Conditions/CommentsANAL ..
ADG715BRUZ , CMOS, Low Voltage Serially Controlled, Octal SPST Switches
ADG715BRUZ-REEL7 , CMOS, Low Voltage Serially Controlled, Octal SPST Switches
ADG719BRM ,CMOS Low Voltage 4 ohm SPDT Switchspecifications –408C to +858C, unless otherwise noted.)DD B Version–408C toParameter +258C +8 ..
ADG719BRT ,CMOS Low Voltage 4 ohm SPDT SwitchCHARACTERISTICSt 14 ns typ R = 300 W , C = 35 pFON L L20 ns max V = 3 V, Test Circuit 4St 3 ns typ ..
ADG719BRT-500RL7 , CMOS 1.8 V to 5.5 V, 2.5 Ω 2:1 Mux/SPDT Switch in SOT-23
AFS600-FGG256 , Fusion Family of Mixed Signal FPGAs
AG201-86 , InGaP HBT Gain Block
AG201-86 , InGaP HBT Gain Block
AG302-86G , InGaP HBT Gain Block
AG303-86 , InGaP HBT Gain Block
AG402-86 , InGaP HBT Gain Block
ADG714BRU-ADG715BRU
CMOS, Low Voltage Serially-Controlled, Octal SPST Switches
REV.0
CMOS, Low Voltage
Serially-Controlled, Octal SPST Switches
FUNCTIONAL BLOCK DIAGRAMS
FEATURES
ADG714 SPI™/QSPI™/MICROWIRE™-Compatible Interface
ADG715 I2C™-Compatible Interface
2.7 V to 5.5 V Single Supply�3 V Dual Supply
2.5 � On Resistance
0.6 � On Resistance Flatness
100 pA Leakage Currents
Octal SPST
Power-On Reset
Fast Switching Times
TTL/CMOS-Compatible
Small TSSOP Package
APPLICATIONS
Data Acquisition Systems
Communication Systems
Relay Replacement
Audio and Video Switching
GENERAL DESCRIPTIONThe ADG714/ADG715 are CMOS, octal SPST (single-pole,
single-throw) switches controlled via either a two- or 3-wire
serial interface. On resistance is closely matched between switches
and very flat over the full signal range. Each switch conducts
equally well in both directions and the input signal range extends
to the supplies. Data is written to these devices in the form of
8 bits, each bit corresponding to one channel.
The ADG714 utilizes a 3-wire serial interface that is compatible
with SPI , QSPI and MICROWIRE and most DSP interface
standards. The output of the shift register DOUT enables a
number of these parts to be daisy chained.
The ADG715 utilizes a 2-wire serial interface that is compatible
with the I2C interface standard. The ADG715 has four hard wired
addresses, selectable from two external address pins (A0 and A1).
This allows the 2 LSBs of the 7-bit slave address to be set by the
user. A maximum of four of these devices may be connected to
the bus.
On power-up of these devices, all switches are in the OFF con-
dition, and the internal registers contain all zeros.
Low power consumption and operating supply range of 2.7 V to
5.5 V make this part ideal for many applications. These parts
may also be supplied from a dual ±3 V supply. The ADG714
and ADG715 are available in a small 24-lead TSSOP package.
PRODUCT HIGHLIGHTS2-3-Wire Serial Interface.Single/Dual Supply Operation. The ADG714 and ADG715
are fully specified and guaranteed with 3 V, 5 V, and ±3 V
supply rails.Low On Resistance, typically 2.5 Ω.Low Leakage.Power-On Reset.Small 24-lead TSSOP package.
I2C is a trademark of Philips Corporation.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.
ADG714/ADG715–SPECIFICATIONS(VDD = 5 V � 10%, VSS = 0 V, GND = 0 V unless otherwise noted)ANALOG SWITCH
DIGITAL INPUTS (SCLK, DIN, SYNC, A0, A1)
DIGITAL OUTPUT ADG714 DOUT
LOGIC OUTPUT (SDA)
ADG714/ADG715SPECIFICATIONS1(VDD = 3 V � 10%, VSS = 0 V, GND = 0 V unless otherwise noted)
ADG714/ADG715–SPECIFICATIONS
DUAL SUPPLY1
(VDD = +3 V � 10%, VSS = 3 V � GND = 0 V unless otherwise noted)
ADG714 TIMING CHARACTERISTICS1, 2
fSCLK
NOTESSee Figure 1.All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.CL = 20 pF, RL = 1 kΩ.
Specifications subject to change without notice.
Figure 1.3-Wire Serial Interface Timing Diagram
(VDD = 2.7 V to 5.5 V. All specifications –40�C to +85�C unless otherwise noted.)
ADG714/ADG715
ADG715 TIMING CHARACTERISTICS1
NOTESSee Figure 2.A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal) in order to bridge the undefined region of
SCL’s falling edge.Cb is the total capacitance of one bus line in pF. tR and tF measured between 0.3 VDD and 0.7 VDD.Input filtering on both the SCL and SDA inputs suppress noise spikes that are less than 50 ns.
Specifications subject to change without notice.
Figure 2.2-Wire Serial Interface Timing Diagram
(VDD = 2.7 V to 5.5 V. All specifications –40�C to +85�C unless otherwise noted.)
ABSOLUTE MAXIMUM RATINGS1
(TA = 25°C unless otherwise noted)
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 V
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . .+0.3 V to –3.5 V
Analog Inputs2 . . . . . . . . . . . . . . .VSS – 0.3 V to VDD + 0.3 V
or 30 mA, Whichever Occurs First
Digital Inputs2 . . . . . . . . . . . . . . . . . . .–0.3 V to VDD + 0.3 V
or 30 mA, Whichever Occurs First
Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . .100 mA
(Pulsed at 1 ms, 10% Duty Cycle Max)
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . .30 mA
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . .–40°C to +85°C
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . .150°C
TSSOP Package
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . .128°C/W
θJC Thermal Impedance . . . . . . . . . . . . . . . . . . . . .42°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . .215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220°C
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.Overvoltages at IN, S, or D will be clamped by internal diodes. Current should be
limited to the maximum ratings given.
ORDERING GUIDE
PIN CONFIGURATIONS
24-Lead TSSOP
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADG714/ADG715 feature proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
ADG714/ADG715
ADG714 PIN FUNCTION DESCRIPTIONS
ADG715 PIN FUNCTION DESCRIPTIONS
2VDD
