ADG527AKP ,CMOS LATCHED 8/16 CHANNEL ANALOG MULTIPLEXERSGENERAL DESCRIPTION
The ADG526A and ADG527A are CMOS monolithic analog
multiplexers with 16 cha ..
ADG527AKP ,CMOS LATCHED 8/16 CHANNEL ANALOG MULTIPLEXERSSpecifications
Wide Supply Ranges (10.8V to 16.5V)
Microprocessor Compatible (100ns WE Pulse)
Ex ..
ADG527ATQ ,CMOS LATCHED 8/16 CHANNEL ANALOG MULTIPLEXERSCHARACTERISTICS'
Vl = A 10V,V2= T-l0V;TestCircuit4
VI = t 10V, V2 = T 10V; Test Circuit 5
..
ADG528ABQ ,CMOS LATCHED 4/8 CHANNEL ANALOG MULTIPLEXERSViIIVUft Channstl Analna Iilhdtinlo3rorn-
WIUIIU"
H V VIIHIIIIVI nnluiua
"'""'e"""" "thlnf ..
ADG528AKN ,CMOS LATCHED 4/8 CHANNEL ANALOG MULTIPLEXERSViIIVUft Channstl Analna Iilhdtinlo3rorn-
WIUIIU"
H V VIIHIIIIVI nnluiua
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ADG528AKP ,CMOS LATCHED 4/8 CHANNEL ANALOG MULTIPLEXERSViIIVUft Channstl Analna Iilhdtinlo3rorn-
WIUIIU"
H V VIIHIIIIVI nnluiua
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AFBR-1529Z , DC to 10 Mbd Versatile Link Fiber Optic Analog Transmitter for 1 mm POF and 200 μm PCS
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AFBR-2419TZ , 50 MBd Miniature Link Fiber Optic Receiver
AFBR-2529Z , DC, 50 Megabaud Versatile Link Fiber Optic Transmitter and Receiver for 1 mm POF
AFBR-57R5APZ , Digital Diagnostic SFP, 850 nm, 4.25/2.125/1.0625 GBd, RoHS Compliant Optical Transceiver
AFBR-5803ATZ ,Packard) - FDDI, 100 Mb/s ATM, and Fast Ethernet Transceivers in Low Cost 1 x 9 Package Style
ADG526ABQ-ADG526AKN-ADG526AKP-ADG526AKR-ADG526ATQ-ADG527AKN-ADG527AKP-ADG527ATQ
CMOS LATCHED 8/16 CHANNEL ANALOG MULTIPLEXERS
Cy ANALOG
DEVICES Latched 8/16 Channel Analog Multiplexers
AM52M/lllmlhl
FEATURES
44V Supply Maximum Rating
Vss to Vor, Analog Signal Range
Single/Dual Supply Specifications
a Wide Supply Ranges (10.8V to 16.5V)
I Microprocessor Compatible (100ns Wh- Pulse)
Extended Plastic Temperature Range
I l-40''C to +85''Cl
. Low Leakage (20PA typ)
_ Low Power Dissipation (28mW max)
Available in DIP, SOIC, PLCC and LCCC Packages
Superior Alternative to:
GENERAL DESCRIPTION
The ADG526A and ADG527A are CMOS monolithic analog
multiplexers with 16 channels and dual 8 channels respectively.
On-chip latches facilitate microprocessor interfacing. The
ADG526A switches one of 16 inputs to a common output de-
pending on the state of four binary addresses and an enable
input. The ADG527A switches one of 8 differential inputs to a
common differential output depending on the state of three
binary addresses and an enable input. Both devices have TTL
and 5V CMOS logic compatible digital inputs.
The ADG526A and ADGS27A are designed on an enhanced
LCZMOS process which gives an increased signal capability of
Vss to VDD and enables operation over a wide range of supply
voltages. The devices can comfortably operate anywhere in the
10.8V to 16.5V single or dual supply range. These multiplexers
also feature high switching speeds and low RON.
mnrmn Ia}! -
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
FUNCTIONAL BLOCK DIAGRAMS
ADG526A ADG527A
DECODER/ - DECODERI
LATCHES LATCHES
AOA1A2A3 ENE A0 A1 A2 EN a_s
PRODUCT HIGHLIGHTS
Single/Dual Supply Specifications with a Wide Tolerance:
The devices are specified in the 10.8V to 16.5V range for
both single and dual supplies.
. Easily Interfaced:
The ADG526A and ADG527A can be easily interfaced with
microprocessors. The W signal latches the state of the
Address control lines and the Enable line. The R_S signal
clears both the address and enable data in the latches resulting
in no output (all switches off). 1% can be tied to the micro-
processor reset pin.
. Extended Signal Range:
The enhanced LCZMOS processing results in a high breakdown
and an increased analog signal range of Vss to VDD.
4. Break-Before-Make Switching:
Switches are guaranteed break-before-make so that input
signals are protected against momentary shorting.
. Low Leakage:
Leakage currents in the range of 20pA make these multiplexers
suitable for high precision circuits.
One Technology Way, P.O. Box 9106, Norwood, MA 02082-9106, U.S.A.
Tel: 617/329-4700
Telex: 924491
Fax: 617/326-8703 wa: 710/394-6577
Cabie: ANALOG NORWOODMASS
hliM2WhlM27h-SPEClFliyirl0lG
Dual Supply (h, = +10.av to +16.5V, Ilss = =10.8ll to -16.5V unless otherwise noted.)
ADG526A ADG526A ADGSZGA
ADG527A ADG527A ADG527A
K Version B Version T Version
- 40''C to - 40''C to - 55''C to
Parameter + 25''C + 85''C + 25°C + 85''C + 25°C + 125°C, Units Comments
ANALOG SWITCH
Analog Signal Range Vss Vss Vss Vss Vss Vss V min
Voo Vor, Vor, VDD Voo Von V max
RON 280 280 280 n typ -10Vsvss +10v,Ios = lmA;TestCircuit1
450 600 450 600 450 600 n max
300 400 300 400 nmax VryD--l5V(tl0%),Vss--- - 15V(t 10%)
300 400 nrnax V01): 15V(t5%), V55: -15V(t5%)
RON Drift 0.6 0.6 0.6 %/°C typ -10VsaVssa +10VAxs---1rnh
RONMatch 5 5 5 %typ -10VssVsss+10v,IDs=imA
ls (OFF), Offlnput Leakage 0.02 0.02 0.02 nA typ V) = 1 10V, V2 = T 10V; Test Circuit 2
1 50 1 50 l 50 nA max
lo (OFF), OffOutput Leakage 0.04 0.04 0.04 nA typ Vl = 110V, V2 = -r-10V;TestCircuit 3
ADG526A 1 200 1 200 l 200 nA max
ADG527A l 100 l 100 l 100 nA max
ID(ON), On Channel Leakage 0.04 0.04 0.04 nA typ Vl = t 10V, V2 = $10V;Tcst Circuit 4
ADGSZGA I 200 l 200 l 200 nA max
ADG527A 1 100 l 100 l 100 nA max
IDIFFJ Differential OffOutput
Leakage (ADG527A only) 25 25 25 nA max VI = t 10V, V2 = Tl0V;Testcircuit 5
DIGITAL CONTROL
VIN", Input High Voltage 2.4 2.4 L4 V min
Vom, Input Low Voltage 0.8 0.8 0.8 V max
IINL or Istm 1 1 1 " max VIN=OIO VDD
Cm Digital Input Capacitance 8 8 8 pF max
DYNAMIC CHARACTERISTICS'
tmmsmon 200 200 200 ns typ V1 = t 10V, V2 = rr10V;TestCircuit 6
300 400 300 400 300 400 ns max
[OPEN 50 50 50 ns typ Test Circuit 7
25 10 25 10 25 10 ns min
:0N(EN,VTR) 200 200 200 ns typ TestCircuits 8and9
300 400 300 400 300 400 ns max
[opp (EN,WS) 200 200 200 ns typ Test Circuits 8 and 10
300 400 300 400 300 400 ns max
tw Write Pulse Width 100 120 100 120 100 130 ns min See Figure]
ts Address, Enable Setup Time 100 100 100 ns min See Figure l
ttt Address, Enable Hold Time 10 10 10 ns min See Figure l
Ins Reset Pulse Width 100 100 100 ns min See Figure 2
OFF Isolation 68 68 68 dB typ VEN = 0.8V, IU. = Ikft, CL = 15pF,
50 50 50 dB min Vs = 7V rms, f= 100kHz
Cs (OF F ) 5 5 5 pF typ VEN = 0.8V
CD (OFF)
ADG526A 44 44 44 pF typ VEN = 0.8V
ADG527A 22 22 22 pF typ
Qrrn, Charge injection 4 4 4 pC typ Rs = on, Vs = 0V; Test Circuit ll
POWER SUPPLY
loo 0.6 0.6 0.6 mA typ an = VINL or Vom
1.5 1.5 1.5 mA max
Iss 20 20 . 20 " typ VIN = VINL or VIN}!
0.2 0.2 0.2 mA max
Power Dissipation 10 10 10 mW typ
28 28 28 mW max
'Sample tetted at + 25'C to ensure compliance.
Specifications subiect to change without notice.
REV. A
Single Supply (h, = +10.BV to +16.5V, Ilss = Mil = IN unless otherwise noted.)
AlyyiflWh08527h
ADG526A ADG526A ADG526A
ADG527A ADG527A ADG527A
K Version B Version T Version
- 40°C to -Atrc to - 55°C to
Parameter + 25''C + 85''C + 25°C + 85''C + 25''C + 125''C Units Comments
ANALOG SWITCH
Analog Signal Range Vss Vss Vss Vss Vss Vss V min
VDD VDD Von V01) VDD Vor, V max
RON 500 500 500 Qtyp OVsVss +10V,Ios--0.5rnA;TestCircuit1
700 1000 700 1000 700 1000 n max
RON Drift 0.6 0.6 0.6 %/°C typ OVSVSS +10V,IDS= 0.5mA
RON Match 5 5 S %typ OvraVrs +10V,ios--0.5mh
15(OFF), OffInput Leakage 0.02 0.02 0.02 nA typ VI = + 10V/0V, V2 = 0V/ + 10V;
1 50 l 50 l 50 nA max Test Circuit 2
[B(OFF), OffOutput Leakage 0.04 0.04 0.04 nA typ V]: + 10V/0V, V2 = 0V/+ 10V;
ADG526A l 200 l 200 1 200 nA max Test Circuit 3
ADG527A 1 100 l 100 l 100 nA max
lo (ON), On Channel Leakage 0.04 0.04 0.04 M typ V1= + 10V/0V, V2 = 0V/ ' 10V;
ADG526A l 200 1 200 l 200 nA max Test Circuit 4
ADG527A 1 100 1 100 l 100 nA max
IDIFF, Differential OffOulput VI = + 10V/0V, V2 =0V/ + 10V;
Leakage (ADG527A only) 25 25 25 nA max Test Circuit 5
DIGITAL CONTROL
VIN", Input High Voltage 2.4 2.4 2.4 V min
me Input Low Voltage 0.8 0.8 0.8 V max
IINL or Iom 1 1 l p.A max VIN = 0 to Hoo
Cm Digital Input Capacitance g 8 8 pF max
DYNAM IC CHARACTERISTICS'
tmmsmon 300 300 300 ns typ Vl = + lOV/OV, V2 = 0V/ + 10V;
450 600 450 600 450 600 ns max Test Circuit 6
tOPEN 50 50 50 ns typ Test Circuit 7
25 10 25 10 25 10 ns min
t0N(EN,WT{) 250 250 250 nstyp TestCircuits 8and9
450 600 450 600 450 600 ns max
Ion.- (EN,R-S) 250 250 250 ns typ Test Circuits 8 and 10
450 600 450 600 450 600 ns max
tw Write Pulse Width 100 120 100 120 100 130 ns min See Figure 1
ts Address, Enable Setup Time 100 100 100 ns min See Figure l
t” Address, Enable Hold Time 10 10 10 ns min See Figure 1
IRS Reset Pulse Width 100 100 100 ns min See Figure 2
OFF Isolation 68 68 68 dBtyp VEN=0.8V, RL---lkn,CL--l5PF,
50 50 50 dB min Vs=3.5Vrms,f=100kHz
Cs (OFF) 5 S 5 pF typ VEN = 0.8V
CD (OFF)
ADG526A 44 44 44 pF typ VEN = 0. 8V
ADG527A 22 22 22 pF typ
QIN], Charge Injection 4 4 4 pCtyp Rs = on,vs = 0V; Test Circuit ll
POWER SUPPLY
IDD 0.6 0.6 0.6 mAtyp Vm=V1NLOIV1NH
1 .5 1 .5 l .5 mA max
Power Dissipation 1 l 1 l 1 1 mW typ
25 25 25 mW max
'Sample tested ttt ' 25°C to ensure compliance.
Specifications subject to change without notice.
REV. A -.3-.
AM52M/Nm527h
TIMING DIAGRAMS
WR . -
o l w Rs 1.5V
l:-- ‘w__J w
-- tres
F-- t -ot t -
3V s " F- f--tttrr rem-ol
EN, A0, M, A2, (A3) 2.0V 03v gwrch Vo -"-'7'r'irv"'Pt Ito
0 . U PU
l l ov
Figure 1.
Figure 1 shows the timing sequence for latching the switch
address and enable inputs. The latches are level sensitive; therefore,
while W is held low, the latches are transparent and the switches
respond to the address and enable inputs. This input data is
latched on the rising edge of W.
Figure 2.
Figure 2 shoes. the Reset Pulse Width, Ins, and Reset Tum-off
Time, tOFF (RS).
Note: All digital input signals rise ahd fall times measured from
10% to 90% of 3V. tR---trr---20ns.
ABSOLUTE MAXIMUM RATINGS'
(TA = + 25°C unless otherwise noted)
Vor, to Vss ........................ 44V
Vor, to GND ....................... 25V
Vss to GND ....................... - 25V
Analog Inputsl
Voltage at S, D ................. Vss - 2V to
VDD + 2V or
20mA, Whichever Occurs First
Continuous Current, S or D ............. 20mA
Pulsed Current S or D
lms Duration, 10% Duty Cycle .......... 40mA
Digital Inputsl
Voltage at A, EN, W, R-s ........... Vss -4V to
VDD + 4V or
20mA, Whichever Occurs First
Potver Dissipation (Any Package)
Upto+75°C....................470mW
Derates above +75°C by ............. 6mWf'C
CAUTION:
Operating Temperature
Commerical (K Version) -4iPC to + 85°C
Industrial (B Version) ........... -4iPC to + 85°C
Extended (T Version) ........... - 55°C to + 125°C
Storage Temperature Range ......... - 65°C to + 150°C
Lead Temperature (Soldering, 10sec) ......... + 300°C
lOvervoltage at A, EN, W, E, S or D will be clamped by diodes. Current
should be limited to the maximum rating above.
*COMMENT: Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not
implied, Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected;
however, permanent damage may occur on unconnected devices subject to high energy electro-
static fields. Unused devices must be stored in conductive foam or shunts. The protective foam
should be discharged to the destination socket before devices are inserted.
ORDERING GUIDE
Temperature Package NOTES
Model Range Option 1To order MIL-STD-883, Class B processed parts, add
ADG526AKN - 40"C to + 85°C N-28 /883B to part number. See Analog Devices Military
- o o - Products Databook (1990) for military data.
23g§26AKR 40°C to + 85°C R 28 2E = Leadless Ceramic Chip Carrier; N = Narrow Plastic
MAKP -40 Cm + 85 C P-28A DIP; P = Plastic Leaded Chip Carrier; Q = Cerdip;
ADG526ABQ -40''C to + 85°C Q-28 R = 0.3" Small Outline IC (5010).
ADG526ATQ3 - 55°C to + 125°C Q-28 'Standard Military Drawing (SMD) assigned by DESC.
ADG526ATIY - 55°C to + 125°C E-28A SMD numbers are
5962-89710013X (ADG526ATE/883B)
ADG527AKN - 40°C to + 85°C N-28 S962-8971001XX (ADGS26ATQ/883B)
ADG527AKR - 40°C to + 85°C R-28 5962-89710023x (ADGS27ATE/883B)
ADG527AKP _ 40°C to + 85°C P-28A 5962-8971002XX (ADG527ATQ/883B)
ADG527ABQ - 40°C to + 85°C Q-28
ADG527ATQ3 - 55°Cto + 125°C Q-28
ADG527ATE3 - 55°C to + 125°C E-28A
-4- REV. A
hinSlM/Nhyill7h
TRUTH TABLES
A2 A1 A0 EN WE Tig ON SWITCH PAIR
X X X x I Retains Previous Switch Condition
X X X X X 0 NONE (Address and Enable
Latches Cleared)
X X X 0 0 l NON E
0 0 0 l 0 l l
0 0 I l 0 l 2
0 l 0 l 0 l 3
0 l l l 0 l 4
l 0 0 l 0 l 5
l 0 l l 0 l 6
1 l 0 1 0 l 7
l l l l 0 l 8
X = Don't Care
ADG 52 7A
PIN CONFIGURATIONS
A3 A2 A1 A0 ENTrt " ONSWITCH
x x X x X -r l Retains Previous Switch Condition
X X X X X X 0 NONE (Address and Enable
LatchesCleared)
x x X X 0 0 l NONE
O 0 0 0 l 0 l 1
0 0 0 l l 0 1 2
0 0 l 0 l t) l 3
0 0 1 l l 0 l 4
0 I 0 0 l 0 l 5
0 l 0 l l 0 l 6
0 l l 0 l 0 1 7
0 l 1 l l 0 l 8
l 0 0 0 l 0 l 9
l 0 0 I l O 1 10
l 0 1 0 l 0 l 11
l 0 l l l 0 l 12
I l 0 0 l 0 1 13
l 1 0 l l 0 l 14
l l l 0 l 0 l 15
l l l I l 0 1 16
X--Dun'tCare
ADG526A
DIP, SOIC
VnoE o " o
ncE " VS:
R-SCE 26 "
" E Ei S7
s1sE " S6
su E Ei] ss
ADGSZGA
suf: " S4
TOP VIEW
suE (NolloScnlal 21 S3
snE 20 S2
s10 " " St
" " " EN
GND 12 17 Au
w-R " " A1
A3 u " A2
ND = NO CONNECT
va . " DA
DEE " v.a
EE " 88A
song " 57A
smE " Mia
$63 " 55A
[E ADGSZTA
553E 22 S4A
TOP VIEW
543E (Not tothastel " S3A
533E 20 52A
523 " " StA
Slit 11 " EN
GND " " A0
W " " At
NC-NO CONNECT
NC = N0 CONNECT
REV. A
ADGSZGA
TOP VIEW
Wot ttt Salt)
ADGSZTA
TOP VIEW
Plot to Scale)
ADG526A
su tt TOPVIEW
S11 9 (NotIoSuIel
" " " " " " "
g b'' a 2 li a E
Me = NO CONNECT
tt I: 2 g' g , if,
. 3 2 , 28 27 "
823 10
Slit It
ADG527A
TOP VIEW
(Nut to Scale)
" " " 15 " " "
t'i'il''ia''e 225
NC = NO CONNECT
