ADG508FBN ,4/8 Channel Fault-Protected Analog MultiplexersGENERAL DESCRIPTIONThe ADG508F, ADG509F and ADG528F are CMOS analog3. Low RON.multiplexers, the AD ..
ADG508FBNZ , 8-Channel/4-Channel Fault-Protected Analog Multiplexers
ADG508FBRN ,4/8 Channel Fault-Protected Analog MultiplexersGENERAL DESCRIPTIONThe ADG508F, ADG509F and ADG528F are CMOS analog3. Low RON.multiplexers, the AD ..
ADG508FBRNZ , 8-Channel/4-Channel Fault-Protected Analog Multiplexers
ADG508FBRW ,4/8 Channel Fault-Protected Analog MultiplexersSPECIFICATIONSDual Supply (V = +15 V 6 10%, V = –15 V 6 10%, GND = 0 V, unless otherwise noted)DD S ..
ADG509ABQ ,CMOS 4/8 CHAANNEL ANALOG MULTIPLEXERSSpecifications subject to change without notice.
REV. Bh0MiBh/h0tyMIh
SINGLE SUPPLY (h, = +10 ..
AF9410N , N-Channel 30-V (D-S) MOSFET
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AF9435P , P-Channel 30-V (D-S) MOSFET
AFBR-1529Z , DC to 10 Mbd Versatile Link Fiber Optic Analog Transmitter for 1 mm POF and 200 μm PCS
AFBR-1629Z , DC, 50 Megabaud Versatile Link Fiber Optic Transmitter and Receiver for 1 mm POF
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ADG508FBN-ADG508FBRN-ADG508FBRW-ADG509FBN-ADG509FBRN-ADG509FBRW-ADG509FTQ-ADG528FBN-ADG528FTQ
4/8 Channel Fault-Protected Analog Multiplexers
ON channel turns off while fault exists.3. Low RON.
4. Fast Switching Times.
5. Break-Before-Make Switching.
Switches are guaranteed break-before-make so that input
signals are protected against momentary shorting.
6. Trench Isolation Eliminates Latch-up.
A dielectric trench separates the p and n-channel MOSFETs
thereby preventing latch-up.
ORDERING GUIDENOTESTo order MIL-STD-883, Class B processed parts, add /883B to T grade part
numbers.N = Plastic DIP; P = Plastic Leaded Chip Carrier (PLCC); Q = Cerdip;
RN = 0.15" Small Outline IC (SOIC), RW = 0.3" Small Outline IC (SOIC).
FUNCTIONAL BLOCK DIAGRAMSA2EN
ADG528F
ONLY
S1A
S4A
S1B
S4BREV.C
4/8 Channel Fault-Protected
Analog Multiplexers*Patent Pending.
GENERAL DESCRIPTIONThe ADG508F, ADG509F and ADG528F are CMOS analog
multiplexers, the ADG508F and ADG528F comprising eight
single channels and the ADG509F comprising four differential
channels. These multiplexers provide fault protection. Using a
series n-channel, p-channel, n-channel MOSFET structure,
both device and signal source protection is provided in the event
of an overvoltage or power loss. The multiplexer can withstand
continuous overvoltage inputs from –40 V to +55 V. During
fault conditions, the multiplexer input (or output) appears as an
open circuit and only a few nanoamperes of leakage current will
flow. This protects not only the multiplexer and the circuitry
driven by the multiplexer, but also protects the sensors or signal
sources that drive the multiplexer.
The ADG508F and ADG528F switch one of eight inputs to a
common output as determined by the 3-bit binary address lines
A0, A1 and A2. The ADG509F switches one of four differential
inputs to a common differential output as determined by the 2-
bit binary address lines A0 and A1. The ADG528F has on-chip
address and control latches that facilitate microprocessor inter-
facing. An EN input on each device is used to enable or disable
the device. When disabled, all channels are switched OFF.
PRODUCT HIGHLIGHTSFault Protection.
The ADG508F/ADG509F/ADG528F can withstand con-
tinuous voltage inputs from –40 V to +55 V. When a fault
occurs due to the power supplies being turned off, all the
channels are turned off and only a leakage current of a few
nanoamperes flows.
FEATURES
Low On Resistance (300 V typ)
Fast Switching Times
tON 250 ns max
tOFF 250 ns max
Low Power Dissipation (3.3 mW max)
Fault and Overvoltage Protection (–40 V to +55 V)
All Switches OFF with Power Supply OFF
Analog Output of ON Channel Clamped Within Power
Supplies If an Overvoltage Occurs
Latch-Up Proof Construction
Break Before Make Construction
TTL and CMOS Compatible Inputs
APPLICATIONS
Existing Multiplexer Applications (Both Fault-Protected
and Nonfault-Protected)
New Designs Requiring Multiplexer Functions
(VDD = +15 V 6 10%, VSS = –15 V 6 10%, GND = 0 V, unless otherwise noted)Dual SupplyLEAKAGE CURRENTS
FAULT
DIGITAL INPUTS
DYNAMIC CHARACTERISTICS
POWER REQUIREMENTS
ADG508F/ADG509F/ADG528F–SPECIFICATIONS1
Table I.ADG508F Truth TableX = Don’t Care
Table II.ADG509F Truth TableX = Don’t Care
Table III.ADG528F Truth TableX = Don’t Care
TIMING DIAGRAMS (ADG528F)Figure 1.
Figure 1 shows the timing sequence for latching the switch
address and enable inputs. The latches are level sensitive; there-
fore, while WR is held low, the latches are transparent and the
switches respond to the address and enable inputs. This input
data is latched on the rising edge of WR.
0.8VO
SWITCH
OUTPUTFigure 2.
Figure 2 shows the Reset Pulsewidth, tRS, and the Reset Turn-
off Time, tOFF (RS).
Note: All digital input signals rise and fall times are measured
from 10% to 90% of 3 V. tR = tF = 20 ns.
ADG508F/ADG509F/ADG528F
ABSOLUTE MAXIMUM RATINGS*(TA = +25°C unless otherwise noted)
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+44 V
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +25 V
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . .+0.3 V to –25 V
VEN, VA Digital Input . . . . . . .– 0.3 V to VDD + 2 V or 20 mA,
Whichever Occurs First
VS, Analog Input Overvoltage with Power ON . . . . .VSS – 25 V
to VDD + 40 V
VS,AnalogInputOvervoltagewithPowerOFF
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–40 Vto+55V
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . .20 mA
Peak Current, S or D
(Pulsed at 1 ms, 10% Duty Cycle max) . . . . . . . . . . .40 mA
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . .–40°C to +85°C
Extended (T Version) . . . . . . . . . . . . . . . .–55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Cerdip PackageJA, Thermal Impedance
16-Lead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76°C/W
18-Lead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73°C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . .+300°C
Plastic PackageJA, Thermal Impedance
16-Lead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117°C
18-Lead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110°C
Lead Temperature, Soldering (10 sec) . . . . . . . . . . .+260°C
SOIC PackageJA, Thermal Impedance
Narrow Body . . . . . . . . . . . . . . . . . . . . . . . . . . . .77°C/W
Wide Body . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
PLCC PackageJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . .90°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
ADG508F/ADG509F PIN CONFIGURATIONS
DIP/SOIC DIP/SOIC
GND
VDD
DS8
VSS
GND
S2A
S3A
S4A
S2B
S3B
S4B
VSS
S1A
VDD
S1BDB
ADG528F PIN CONFIGURATIONS
DIP PLCC
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although these devices feature proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
TERMINOLOGYVSS
GND
RON
RON Drift
IS (OFF)
ID (OFF)
ID, IS (ON)
VD (VS)
CD, CS (ON)
CIN
tON (EN)
tOFF (EN)
tTRANSITION
tOPEN
VINL
VINH
IINL (IINH)
Off Isolation
Charge Injection
IDD
Typical Performance GraphsFigure 3.On Resistance as a Function of VD (VS)
100m
10m
10n
100n
10p
100p
VIN – INPUT VOLTAGE – Volts
– INPUT LEAKAGE – AFigure 4.Input Leakage Current as a Function of VS
(Power Supplies OFF) During Overvoltage Conditions
Figure 5.Output Leakage Current as a Function of VS
(Power Supplies ON) During Overvoltage Conditions
ADG508F/ADG509F/ADG528F
VD (VS) – Volts
– Figure 6.On Resistance as a Function of VD (VS) for
Different Temperatures
100m
10m
10n
100n
10p
100p
VIN – INPUT VOLTAGE – Volts
– INPUT LEAKAGE – AFigure 7.Input Leakage Current as a Function of VS
(Power Supplies ON) During Overvoltage Conditions
VS, VD – Volts
LEAKAGE CURRENTS – nAFigure 8.Leakage Currents as a Function of VD (VS)
TEMPERATURE – 8C
LEAKAGE CURRENTS – nA95105Figure 9.Leakage Currents as a Function of Temperature
– ns
VSUPPLY – VoltsFigure 10.Switching Time vs. Power Supply
– ns
TEMPERATURE – 8C
260Figure 11.Switching Time vs. Temperature
