ADG465BRM Fast Delivery |IC PHOENIX CO.,LIMITED

ADG465BRM ,Single Channel Protector in an SOT-23 PackageSpecifications subject to change without notice.REV. A REV. A–2– –2–ADG4651ABSOLUTE MAXIMUM RATINGS ..
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AF4A1950S60DCC , Array BPF (AF Type)
AF82801IBM , Mobile Intel® GM45, GS45, and GL40 Express Chipsets for Embedded Computing
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AF9410N , N-Channel 30-V (D-S) MOSFET
AF9435P , P-Channel 30-V (D-S) MOSFET
AF9435P , P-Channel 30-V (D-S) MOSFET

ADG465BRM
Single Channel Protector in an SOT-23 Package
REV.A
Single Channel Protector
in an SOT-23 Package
FUNCTIONAL BLOCK DIAGRAM
VDDVSSVIN
VDDVDD
VIN
VOUT
OUTPUT CLAMPED
@ VDD – 1.5V
GENERAL DESCRIPTION
The ADG465 is a single channel protector in an SOT-23 pack-
age. The channel protector is placed in series with the signal
path, and will protect sensitive components from voltage tran-
sience in the signal path whether or not the power supplies are
present. Because the channel protection works regardless of the
presence of the supplies, the channel protectors are ideal for use
in applications where correct power sequencing cannot always
be guaranteed to protect analog inputs (e.g., hot-insertion rack
systems). This is discussed further, and some example circuits
are given, in the Applications section of this data sheet.
A channel protector consists of an n-channel MOSFET, a
p-channel MOSFET and an n-channel MOSFET, connected in
series. The channel protector behaves like a series resistor dur-
ing normal operation, i.e., (VSS + 2V) < VIN < (VDD – 1.5V).
When a channel’s analog input exceeds the power supplies
(including VDD and VSS = 0V), one of the MOSFETs will
switch off, clamping the output to either VSS + 2V or VDD – 1.5V.
Circuitry and signal source protection is provided in the event of
an overvoltage or power loss. The channel protectors can with-
stand overvoltage inputs from –40V to +40V. See the Circuit
Information section of this data sheet.
The ADG465 can operate from both bipolar and unipolar
supplies. The channels are normally on when power is con-
nected, and open circuit when power is disconnected. With
power supplies of –15V, the on-resistance of the ADG465 isW typ, with a leakage current of –1nA max. When power
is disconnected, the input leakage current is approximately5nA typ.
The ADG465 is available in a 6-lead plastic surface mount
SOT-23 package, and an 8-lead mSOIC package.
PRODUCT HIGHLIGHTSFault Protection.
The ADG465 can withstand continuous voltage inputs from
–40V to +40V. When a fault occurs due to the power sup-
plies being turned off, or due to an overvoltage being applied
to the ADG465, the output is clamped. When power is turned
off, current is limited to the nanoampere level.Low Power Dissipation.Low RON 80W typ.Trench Isolation Latchup-Proof Construction.
A dielectric trench separates the p- and n-channel MOSFETs
thereby preventing latchup.
FEATURES
Fault and Overvoltage Protection up to 640␣V
Signal Paths Open Circuit with Power Off
Signal Path Resistance of RON with Power On
44 V Supply Maximum Ratings
Low On Resistance 80 V Typ
1 nA Max Path Current Leakage @ +258C
Low Power Dissipation 0.8␣mW Typ
Latchup-Proof Construction
APPLICATIONS
ATE Equipment
Sensitive Measurement Equipment
Hot-Insertion Rack Systems
ADC Input Channel Protection
ADG465–SPECIFICATIONS
Dual Supply1
FAULT PROTECTED CHANNEL
LEAKAGE CURRENTS
NOTES
1Temperature range is as follows: B Version: –40°C to +85°C.
2Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
(VDD = +15V, VSS = –15V, GND = 0V, unless otherwise noted)
ABSOLUTE MAXIMUM RATINGS1
(TA = +25°C unless otherwise noted)
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+44V
VS, VD, Analog Input Overvoltage with Power ON2
. . . . . . . . . . . . . . . . . . . . . . . . .VSS – 20V to VDD + 20V
VS, VD, Analog Input Overvoltage with Power OFF2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–35V to +35V
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . .20mA
Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . .40mA
(Pulsed at 1ms, 10% Duty Cycle Max)
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . .–40°C to +85°C
Storage Temperature Range . . . . . . . . . . . .–65°C to +125°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
SOT-23 PackageJA, Thermal Impedance . . . . . . . . . . . . . . . . . . .230°C/WSOIC PackageJA, Thermal Impedance . . . . . . . . . . . . . . . . . . .205°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.Overvoltages at S or D will be clamped by the channel protector, see Circuit
Information section of the data sheet.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADG465 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE
PIN CONFIGURATIONS
PIN FUNCTION DESCRIPTIONS
(RT-6)
NC = NO CONNECT
VD1
VS1
VDD
VSS
(RM-8)
NC = NO CONNECTVDD
VSS
VD1
VS1NCNC
ADG465
—Typical Performance Characteristics
VD, VS – Volts
–
110
Figure 1.On Resistance as a Function of VDD and VD
(Input Voltage)
VD, VS – Volts
–
105
Figure 2.On Resistance as a Function of Temperature
and VD (Input Voltage)500mV5.00VCh25.00VM50.0nsCh1
Volts
Figure 3.Positive Overvoltage Transience Response
Ch1500mV5.00V5.00VM50.0nsCh1
Volts
Figure 4.Negative Overvoltage Transience Response500mV5.00VCh25.00VM100nsCh1
Figure 5.Overvoltage Ramp
CIRCUIT INFORMATION
Figure 6 below shows a simplified schematic of a channel pro-
tector circuit. The circuit is comprised of four MOS transis-
tors—two NMOS and two PMOS. One of the PMOS devices
does not lie directly in the signal path, but is used to connect the
source of the second PMOS device to its backgate. This has the
effect of lowering the threshold voltage and increasing the
input signal range of the channel for normal operation. The
source and backgate of the NMOS devices are connected for the
same reason. During normal operation the channel protectors
have a resistance of 80␣W typ. The channel protectors are very
low power devices; even under fault conditions the supply cur-
rent is limited to sub-microampere levels. All transistors are
dielectrically isolated from each other using a trench isolation
method. This makes it impossible to latch up the channel pro-
tectors. For an explanation, see Trench Isolation section.
VSS
NMOSNMOS
VSSVDDVDD
Figure 6.The Channel Protector Circuit
Overvoltage Protection
When a fault condition occurs on the input of a channel pro-
tector, the voltage on the input has exceeded some threshold
voltage set by the supply rail voltages. The threshold voltages
are related to the supply rails as follows: for a positive overvolt-
age, the threshold voltage is given by VDD – VT where VTN is the
threshold voltage of the NMOS transistor (1.5␣V typ). In the
case of a negative overvoltage the threshold voltage is given by
VSS – VTP where VTP is the threshold voltage of the PMOS
device (2␣V typ). If the input voltage exceeds these threshold
voltages, the output of the channel protector (no load) is
clamped at these threshold voltages. However, the channel
protector output will clamp at a voltage inside these thresholds
if the output is loaded. For example, with an output load ofkW, VDD = 15␣V and a positive overvoltage. The output will
clamp at VDD – VTN – DV = 15␣V – 1.5␣V – 0.6␣V = 12.9␣V
where DV is due to I. R voltage drops across the channels of the
MOS devices (see Figure 8). As can be seen from Figure 8, the
current during fault condition is determined by the load on the
output (i.e., VCLAMP/RL). However, if the supplies are off, the
fault current is limited to the nanoampere level.
Figures 7, 9 and 10 show the operating conditions of the signal
path transistors during various fault conditions. Figure 7 shows
how the channel protectors operate when a positive overvoltage
is applied to the channel protector.NMOS
VSS (–15V)VDD (+15V)VDD (+15V)
VDD – VTN*
(+13.5V)POSITIVE
OVERVOLTAGE
(+20V)
*VTN = NMOS THRESHOLD VOLTAGE (+1.5V)
Figure 7.Positive Overvoltage on the Channel Protector
The first NMOS transistor goes into a saturated mode of opera-
tion as the voltage on its Drain exceeds the Gate voltage (VDD) –
the threshold voltage (VTN). This situation is shown in Figure 8.
The potential at the source of the NMOS device is equal to VDD
–VTN. The other MOS devices are in a nonsaturated mode of
operation.VGVS(+20V)
PMOSNMOS
NONSATURATED
OPERATION
IOUTVCLAMP
OVERVOLTAGE
OPERATION
(SATURATED)
Figure 8.Positive Overvoltage Operation on the Channel Protector
ADG465
When a negative overvoltage is applied to the channel protector
circuit, the PMOS transistor enters a saturated mode of operation
as the drain voltage exceeds VSS – VTP. See Figure 9 below. As in
the case of the positive overvoltage, the other MOS devices are
nonsaturated.
NEGATIVE
OVERVOLTAGE
(–20V)NMOS
VSS (–15V)VDD (+15V)VDD (+15V)NEGATIVE
OVERVOLTAGE
(–20V)
*VTP = PMOS THRESHOLD VOLTAGE (+2V)
Figure 9.Negative Overvoltage on the Channel Protector
The channel protector is also functional when the supply rails
are down (e.g., power failure) or momentarily unconnected
(e.g., rack system). This is where the channel protector has an
advantage over more conventional protection methods such as
diode clamping (see Applications Information). When VDD and
VSS equal 0␣V, all transistors are off and the current is limited to
microampere levels (see Figure 10).
VSS (0V)VDD (0V)VDD (0V)
(0V)
POSITIVE OR
NEGATIVE
OVERVOLTAGENMOS
Figure 10.Channel Protector Supplies Equal to Zero Volts
TRENCH ISOLATION
The MOS devices that make up the channel protector are
isolated from each other by an oxide layer (trench) (see Figure
11). When the NMOS and PMOS devices are not electrically
isolated from each other, there exists the possibility of “latchup”
caused by parasitic junctions between CMOS transistors. Latchup
is caused when P-N junctions that are normally reverse biased,
become forward biased, causing large currents to flow. This can
be destructive.
CMOS devices are normally isolated from each other by
Junction Isolation. In Junction Isolation, the N and P wells of the
CMOS transistors form a diode that is reverse biased under
normal operation. However, during overvoltage conditions, this
diode becomes forward biased. A Silicon-Controlled Rectifier
(SCR) type circuit is formed by the two transistors, causing a
significant amplification of the current that, in turn, leads to
latchup. With Trench Isolation, this diode is removed; the result
is a latchup-proof circuit.VS
Figure 11.Trench Isolation

Partno	Mfg	Dc	Qty	Available	Descript
ADG465BRM	AD	N/a	1	avai	Single Channel Protector in an SOT-23 Package