ADG431BN ,LC2MOS Precision Quad SPST SwitchesGENERAL DESCRIPTIONSWITCHES SHOWN FOR A LOGIC "1" INPUTThe ADG431, ADG432 and ADG433 are monolithic ..
ADG431BN ,LC2MOS Precision Quad SPST SwitchesSPECIFICATIONS(V = +15 V 6 10%, V = –15 V 6 10%, V = +5 V 6 10%, GND = O V, unless otherwise noted) ..
ADG431BR ,LC2MOS Precision Quad SPST SwitchesSPECIFICATIONS(V = +15 V 6 10%, V = –15 V 6 10%, V = +5 V 6 10%, GND = O V, unless otherwise noted) ..
ADG432ABR ,LC2MOS Precision Quad SPST Switchesapplications where the analog signal is unipolar, theare turned on with a logic low on the appropri ..
ADG432BN ,LC2MOS Precision Quad SPST SwitchesFEATURES44 V Supply Maximum RatingsS1 S1615 V Analog Signal RangeIN1 IN1Low On Resistance (<24 V)D1 ..
ADG432BR ,LC2MOS Precision Quad SPST SwitchesCHARACTERISTICS V = +15 V, V = –15 VDD SSt 90 90 ns typ R = 300 W , C = 35 pF;ON L L165 175 ns max ..
AF4362NSLA , N-Channel Enhancement Mode Power MOSFET
AF4362NSLA , N-Channel Enhancement Mode Power MOSFET
AF4407PS , P-Channel 30-V (D-S) MOSFET
AF4410N , N-Channel Enhancement Mode Power MOSFET
AF4410N , N-Channel Enhancement Mode Power MOSFET
AF4502C , P & N-Channel 30-V (D-S) MOSFET
ADG431ABR-ADG431BN-ADG431BR-ADG432ABR-ADG432BN-ADG432BR-ADG433ABR-ADG433BN-ADG433BR
LC2MOS Precision Quad SPST Switches
FUNCTIONAL BLOCK DIAGRAMSREV.B
LC2MOS
Precision Quad SPST Switches
FEATURES
44 V Supply Maximum Ratings615 V Analog Signal Range
Low On Resistance (<24 V)
Ultralow Power Dissipation (3.9 mW)
Low Leakage (<0.25 nA)
Fast Switching Times
tON <165 ns
tOFF <130 ns
Break-Before-Make Switching Action
TTL/CMOS Compatible
Plug-in Replacement for DG411/DG412/DG413
APPLICATIONS
Audio and Video Switching
Automatic Test Equipment
Precision Data Acquisition
Battery Powered Systems
Sample Hold Systems
Communication Systems
GENERAL DESCRIPTIONThe ADG431, ADG432 and ADG433 are monolithic CMOS
devices comprising four independently selectable switches. They
are designed on an enhanced LC2MOS process which provides
low power dissipation yet gives high switching speed and low on
resistance.
The on resistance profile is very flat over the full analog input
range ensuring excellent linearity and low distortion when
switching audio signals. Fast switching speed coupled with high
signal bandwidth also make the parts suitable for video signal
switching. CMOS construction ensures ultralow power dissipa-
tion making the parts ideally suited for portable and battery
powered instruments.
The ADG431, ADG432 and ADG433 contain four indepen-
dent SPST switches. The ADG431 and ADG432 differ only in
that the digital control logic is inverted. The ADG431 switches
are turned on with a logic low on the appropriate control input,
while a logic high is required for the ADG432. The ADG433
has two switches with digital control logic similar to that of the
ADG431 while the logic is inverted on the other two switches.
Each switch conducts equally well in both directions when ON
and has an input signal range which extends to the supplies. In
the OFF condition, signal levels up to the supplies are blocked.
All switches exhibit break before make switching action for use
in multiplexer applications. Inherent in the design is low charge
injection for minimum transients when switching the digital inputs.
PRODUCT HIGHLIGHTSExtended Signal Range
The ADG431, ADG432 and ADG433 are fabricated on an
enhanced LC2MOS process giving an increased signal range
which extends fully to the supply rails.Ultralow Power DissipationLow RONBreak-Before-Make Switching
This prevents channel shorting when the switches are config-
ured as a multiplexer.Single Supply Operation
For applications where the analog signal is unipolar, the
ADG431, ADG432 and ADG433 can be operated from a
single rail power supply. The parts are fully specified with a
single +12 V power supply and will remain functional with
single supplies as low as +5 V.
ADG431/ADG432/ADG433–SPECIFICATIONS1
Dual SupplyLEAKAGE CURRENTS
DYNAMIC CHARACTERISTICS
POWER REQUIREMENTS
NOTESTemperature ranges are as follows: B Versions: –40°C to +85°C; T Versions: –55°C to +125°C.Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
(VDD = +15 V 6 10%, VSS = –15 V 6 10%, VL = +5 V 6 10%, GND = O V, unless otherwise noted)
Truth Table (ADG431/ADG432)
Truth Table (ADG433)
Single SupplyLEAKAGE CURRENTS
DYNAMIC CHARACTERISTICS
POWER REQUIREMENTS
NOTES
1Temperature ranges are as follows: B Versions: –40°C to +85°C; T Versions: –55°C to +125°C.
2Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
(VDD = +12 V 6 10%, VSS = O V, VL = +5 V 6 10%, GND = O V, unless otherwise noted)
ADG431/ADG432/ADG433
ADG431/ADG432/ADG433
ABSOLUTE MAXIMUM RATINGS(TA = +25°C unless otherwise noted)
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+44 V
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +25 V
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . .+0.3 V to –25 V
VL to GND . . . . . . . . . . . . . . . . . . . . . .–0.3 V to VDD + 0.3 V
Analog, Digital Inputs2 . . . . . . . . . .VSS – 2 V to VDD + 2 V or
30 mA, Whichever Occurs First
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . .30 mA
Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . .100 mA
(Pulsed at 1 ms, 10% Duty Cycle max)
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . .–40°C to +85°C
Extended (T Version) . . . . . . . . . . . . . . . .–55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Cerdip Package, Power Dissipation . . . . . . . . . . . . . . .900 mWJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . .76°C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . .+300°C
Plastic Package, Power Dissipation . . . . . . . . . . . . . . .470 mWJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . .117°C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . .+260°C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . .600 mWJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . .77°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.Overvoltages at IN, S or D will be clamped by internal diodes. Current should be
limited to the maximum ratings given.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADG431/ADG432/ADG433 features proprietary ESD protection circuitry, perma-
nent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
PIN CONFIGURATION
(DIP/SOIC)
ORDERING GUIDENOTESTo order MIL-STD-883, Class B processed parts, add /883B to T grade part numbers.
2N = Plastic DIP; R = 0.15" Small Outline IC (SOIC); Q = Cerdip.Trench isolated, latch-up proof parts. See Trench Isolation section.
TERMINOLOGYVDDMost positive power supply potential.
VSSMost negative power supply potential in dual
supplies. In single supply applications, it may be
connected to GND.Logic power supply (+5 V).
GNDGround (0 V) reference.Source terminal. May be an input or output.Drain terminal. May be an input or output.Logic control input.
RONOhmic resistance between D and S.
RON vs. VD (VS)The variation in RON due to a change in the ana-
log input voltage with a constant load current.
RON DriftChange in RON vs. temperature.
RON MatchDifference between the RON of any two switches.
CS (OFF)“OFF” switch source capacitance.
CD (OFF)“OFF” switch drain capacitance.
CD, CS (ON)“ON” switch capacitance.
CINInput Capacitance to ground of a digital input.
tONDelay between applying the digital control input
and the output switching on.
tOFFDelay between applying the digital control input
and the output switching off.“OFF” time or “ON” time measured between the
90% points of both switches, when switching
from one address state to another.
CrosstalkA measure of unwanted signal which is coupled
through from one channel to another as a result
of parasitic capacitance.
Typical Performance GraphsFigure 1.On Resistance as a Function of VD (VS) Dual
Supplies
Figure 2.On Resistance as a Function of
VD (VS) for Different Temperatures
Figure 4.On Resistance as a Function of VD (VS) Single
Supply
Figure 5.Supply Current vs. Input Switching Frequency
ADG431/ADG432/ADG433Figure 7.Off Isolation vs. Frequency
Figure 8.Crosstalk vs. Frequency
TRENCH ISOLATIONIn the ADG431A, ADG432A and ADG433A, an insulating
oxide layer (trench) is placed between the NMOS and PMOS
transistors of each CMOS switch. Parasitic junctions, which
occur between the transistors in junction isolated switches, are
eliminated, the result being a completely latch-up proof switch.
In junction isolation, the N and P wells of the PMOS and
NMOS transistors from a diode that is reverse-biased under
normal operation. However, during overvoltage conditions, this
diode becomes forward biased. A silicon-controlled rectifier
(SCR) type circuit is formed by the two transistors causing a
significant amplification of the current which, in turn, leads to
latch up. With trench isolation, this diode is removed, the result
being a latch-up proof switch.
Figure 9.Trench Isolation
APPLICATIONFigure 10 illustrates a precise, fast sample-and-hold circuit. An
AD845 is used as the input buffer while the output operational
amplifier is an AD711. During the track mode, SW1 is closed
and the output VOUT follows the input signal VIN. In the hold
mode, SW1 is opened and the signal is held by the hold capaci-
tor CH.
Due to switch and capacitor leakage, the voltage on the hold
capacitor will decrease with time. The ADG431/ADG432/
ADG433 minimizes this droop due to its low leakage specifica-
tions. The droop rate is further minimized by the use of a poly-
styrene hold capacitor. The droop rate for the circuit shown is
typically 30 mV/ms.
A second switch SW2, which operates in parallel with SW1, is
included in this circuit to reduce pedestal error. Since both
switches will be at the same potential, they will have a differen-
tial effect on the op amp AD711 which will minimize charge
injection effects. Pedestal error is also reduced by the compensa-
tion network RC and CC. This compensation network also
reduces the hold time glitch while optimizing the acquisition
time. Using the illustrated op amps and component values, the
pedestal error has a maximum value of 5 mV over the –10 V
input range. Both the acquisition and settling times are 850 ns.
Figure 10.Fast, Accurate Sample-and-Hold
