ADG412BN ,LC2MOS Precision Quad SPST SwitchesSpecifications subject to change without notice.–2– REV. AADG411/ADG412/ADG413(V = +12 V 6 10%, V = ..
ADG412BR ,LC2MOS Precision Quad SPST SwitchesSPECIFICATIONS(V = +15 V 6 10%, V = –15 V 6 10%, V = +5 V 6 10%, GND = 0 V, unless otherwise noted) ..
ADG412BR-REEL , LC2MOS Precision Quad SPST Switches
ADG412TQ ,LC2MOS Precision Quad SPST Switchesapplications where the analog signal is unipolar, thehas two switches with digital control logic si ..
ADG413BN ,LC2MOS Precision Quad SPST SwitchesGENERAL DESCRIPTIONS4The ADG411, ADG412 and ADG413 are monolithic CMOSIN4devices comprising four in ..
ADG413BNZ , LC2MOS Precision Quad SPST Switches
AF4362NSLA , N-Channel Enhancement Mode Power MOSFET
AF4362NSLA , N-Channel Enhancement Mode Power MOSFET
AF4407PS , P-Channel 30-V (D-S) MOSFET
AF4410N , N-Channel Enhancement Mode Power MOSFET
AF4410N , N-Channel Enhancement Mode Power MOSFET
AF4502C , P & N-Channel 30-V (D-S) MOSFET
ADG411BN-ADG411BR-ADG411BRU-ADG411TQ-ADG412BN-ADG412BR-ADG412TQ-ADG413BN-ADG413BR
LC2MOS Precision Quad SPST Switches
FUNCTIONAL BLOCK DIAGRAMSREV.A
LC2MOS
Precision Quad SPST Switches
FEATURES
44 V Supply Maximum Ratings615 V Analog Signal Range
Low On Resistance (<35 V)
Ultralow Power Dissipation (35 mW)
Fast Switching Times
tON <175 ns
tOFF <145 ns
TTL/CMOS Compatible
Plug-In Replacement for DG411/DG412/DG413
APPLICATIONS
Audio and Video Switching
Automatic Test Equipment
Precision Data Acquisition
Battery Powered Systems
Sample Hold Systems
Communication Systems
PRODUCT HIGHLIGHTSExtended Signal Range
The ADG411, ADG412 and ADG413 are fabricated on an
enhanced LC2MOS, giving an increased signal range which
extends fully to the supply rails.Ultralow Power DissipationLow RONBreak-Before-Make Switching
This prevents channel shorting when the switches are
configured as a multiplexer.Single Supply Operation
For applications where the analog signal is unipolar, the
ADG411, ADG412 and ADG413 can be operated from a
single rail power supply. The parts are fully specified with a
single +12 V power supply and will remain functional with
single supplies as low as +5 V.
GENERAL DESCRIPTIONThe ADG411, ADG412 and ADG413 are monolithic CMOS
devices comprising four independently selectable switches. They
are designed on an enhanced LC2MOS process which provides
low power dissipation yet gives high switching speed and low on
resistance.
The on resistance profile is very flat over the full analog input
range ensuring excellent linearity and low distortion when
switching audio signals. Fast switching speed coupled with high
signal bandwidth also make the parts suitable for video signal
switching. CMOS construction ensures ultralow power dissipa-
tion making the parts ideally suited for portable and battery
powered instruments.
The ADG411, ADG412 and ADG413 contain four indepen-
dent SPST switches. The ADG411 and ADG412 differ only in
that the digital control logic is inverted. The ADG411 switches
are turned on with a logic low on the appropriate control input,
while a logic high is required for the ADG412. The ADG413
has two switches with digital control logic similar to that of the
ADG411 while the logic is inverted on the other two switches.
Each switch conducts equally well in both directions when ON
and each has an input signal range that extends to the supplies.
In the OFF condition, signal levels up to the supplies are
blocked. All switches exhibit break-before-make switching ac-
tion for use in multiplexer applications. Inherent in the design is
low charge injection for minimum transients when switching the
digital inputs.
ADG411/ADG412/ADG413–SPECIFICATIONS1
Dual SupplyDYNAMIC CHARACTERISTICS
NOTESTemperature ranges are as follows: B Versions: –40°C to +85°C; T Versions: –55°C to +125°C.Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
(VDD = +15 V 6 10%, VSS = –15 V 6 10%, VL = +5 V 6 10%, GND = 0 V, unless otherwise noted)
Truth Table (ADG411/ADG412)
ADG411/ADG412/ADG413
Single SupplyDYNAMIC CHARACTERISTICS
NOTESTemperature ranges are as follows: B Versions: –40°C to +85°C; T Versions: –55°C to +125°C.Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
(VDD = +12 V 6 10%, VSS = 0 V, VL = +5 V 6 10%, GND = 0 V, unless otherwise noted)
Truth Table (ADG413)
ADG411/ADG412/ADG413
ORDERING GUIDEADG411BR
ADG411TQ
ADG411BRU
ADG412BN
ADG412BR
ADG412TQ
ADG413BN
NOTESTo order MIL-STD-883, Class B processed parts, add /883B to T grade part
numbers.N = Plastic DIP; R = 0.15" Small Outline IC (SOIC); RU= Thin Shrink Small
Outline (TSSOP); Q = Cerdip.
ABSOLUTE MAXIMUM RATINGS1(TA = +25°C unless otherwise noted)
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+44 V
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +25 V
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . .+0.3 V to –25 V
VL to GND . . . . . . . . . . . . . . . . . . . . . .–0.3 V to VDD + 0.3 V
Analog, Digital Inputs2 . . . . . . . . . . .VSS –2 V to VDD +2 V or
30 mA, Whichever Occurs First
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . .30 mA
Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . .100 mA
(Pulsed at 1 ms, 10% Duty Cycle max)
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . .–40°C to +85°C
Extended (T Version) . . . . . . . . . . . . . . . .–55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Cerdip Package, Power Dissipation . . . . . . . . . . . . . . .900 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . .76°C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . .+300°C
Plastic Package, Power Dissipation . . . . . . . . . . . . . . .470 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . .117°C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . .+260°C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . .600 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . .77°C/W
TSSOP Package, Power Dissipation . . . . . . . . . . . . . .450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . .115°C/W
θJC Thermal Impedance . . . . . . . . . . . . . . . . . . . . . .35°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.Overvoltages at IN, S or D will be clamped by internal diodes. Current should be
limited to the maximum ratings given.
TERMINOLOGYVSS
GND
RON
IS (OFF)
ID (OFF)
CD, CS (ON)
tON
tOFF
Crosstalk
Off Isolation
Charge
Injection
PIN CONFIGURATION
(DIP/SOIC)
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
Typical Performance Graphs Figure 1.On Resistance as a Function of VD (VS) Dual
Supplies
Figure 2.On Resistance as a Function of VD (VS) for
Different Temperatures
Figure 4.On Resistance as a Function of VD (VS) Single
Supply
Figure 5.Supply Current vs. Input Switching Frequency
ADG411/ADG412/ADG413Figure 7.Off Isolation vs. Frequency
Figure 8.Crosstalk vs. Frequency
APPLICATIONFigure 9 illustrates a precise, fast, sample-and-hold circuit. An
AD845 is used as the input buffer while the output operational
amplifier is an AD711. During the track mode, SW1 is closed
and the output VOUT follows the input signal VIN. In the hold
mode, SW1 is opened and the signal is held by the hold capaci-
tor CH.
Due to switch and capacitor leakage, the voltage on the hold
capacitor will decrease with time. The ADG411/ADG412/
ADG413 minimizes this droop due to its low leakage specifica-
tions. The droop rate is further minimized by the use of a poly-
styrene hold capacitor. The droop rate for the circuit shown is
typically 30 μV/μs.
A second switch, SW2, which operates in parallel with SW1, is
included in this circuit to reduce pedestal error. Since both
switches will be at the same potential, they will have a differen-
tial effect on the op amp AD711, which will minimize charge
injection effects. Pedestal error is also reduced by the compensa-
tion network RC and CC. This compensation network also re-
duces the hold time glitch while optimizing the acquisition time.
Using the illustrated op amps and component values, the pedes-
tal error has a maximum value of 5 mV over the ±10 V input
range. Both the acquisition and settling times are 850 ns.
Figure 9.Fast, Accurate Sample-and-Hold
