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ADG406BN-ADG406BP-ADG407BN-ADG407BP-ADG426BN-ADG426BRS-ADG426-BRS
LC2MOS 8-/16-Channel High Performance Analog Multiplexers
REV.0
FEATURES
44 V Supply Maximum Ratings
VSS to VDD Analog Signal Range
Low On Resistance (80 Ω max)
Low Power
Fast Switching
tON < 160ns
tOFF < 150ns
Break Before Make Switching Action
Plug-In Upgrade for
DG506A/ADG506A, DG507A/ADG507A,
DG526/ADG526A
ADG406/ADG407 are Plug-In Replacements for
DG406/DG407
APPLICATIONS
Audio and Video Routing
Automatic Test Equipment
Data Acquisition Systems
Battery Powered Systems
Sample Hold Systems
Communication Systems
Avionics2MOS 8-/16-Channel
High Performance Analog Multiplexers
GENERAL DESCRIPTIONThe ADG406, ADG407 and ADG426 are monolithic CMOS
analog multiplexers. The ADG406 and ADG426 switch one of
sixteen inputs to a common output as determined by the 4-bit
binary address lines A0, A1, A2 and A3. The ADG426 has on-
chip address and control latches that facilitate microprocessor
interfacing. The ADG407 switches one of eight differential
inputs to a common differential output as determined by the 3-
bit binary address lines A0, A1 and A2. An EN input on all
devices is used to enable or disable the device. When disabled,
all channels are switched OFF.
The ADG406/ADG407/ADG426 are designed on an enhanced2MOS process that provides low power dissipation yet gives
high switching speed and low on resistance. These features
make the parts suitable for high speed data acquisition systems
and audio signal switching. Low power dissipation makes the
parts suitable for battery powered systems. Each channel
conducts equally well in both directions when ON and has an
input signal range which extends to the supplies. In the OFF
condition, signal levels up to the supplies are blocked. All
channels exhibit break before make switching action preventing
momentary shorting when switching channels. Inherent in the
design is low charge injection for minimum transients when
switching the digital inputs.
NOTESTemperature ranges are as follows: B Versions: –40°C to +85°C; T Versions: –55°C to +125°C.
ADG406/ADG407/ADG426–SPECIFICATIONS1
DUAL SUPPLY
(VDD = +15 V ± 10%, VSS = –15 V ± 10%, GND = 0 V, unless otherwise noted)
ADG406/ADG407/ADG426
SINGLE SUPPLY(VDD = +12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted)NOTESTemperature ranges are as follows: B Versions: –40°C to +85°C; T Versions: –55°C to +125°C.Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
ADG406/ADG407/ADG426
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although these devices feature proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ORDERING GUIDE*N = Plastic DIP, P = Plastic Leaded Chip Carrier (PLCC), RS = Shrink Small
Outline Package (SSOP).
ABSOLUTE MAXIMUM RATINGS1(TA = +25°C unless otherwise noted)
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+44 V
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +25 V
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . .+0.3 V to –25 V
Analog, Digital Inputs2. . . . . . . . . . . . .VSS – 2 V to VDD + 2 V
or 20 mA, Whichever Occurs First
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . .20 mA
Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . .40 mA
(Pulsed at 1 ms, 10% Duty Cycle Max)
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . .–40°C to +85°C
Extended (T Version) . . . . . . . . . . . . . . . . .–55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Plastic Package
θJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . .75°C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . .+260°C
PLCC Package
θJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . .80°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
SSOP Package
θJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . .122°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
NOTESStresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability. Only
one absolute maximum rating may be applied at any one time.Overvoltages at A, S, D, WR or RS will be clamped by internal diodes. Current
should be limited to the maximum ratings given.
Table III.Truth Table (ADG426)
Table I.Truth Table (ADG406)
Table II.Truth Table (ADG407)
ADG406/ADG407/ADG426
TIMING DIAGRAMS (ADG426)Figure 1.
Figure 1 shows the timing sequence for latching the switch
address and enable inputs. The latches are level sensitive;
therefore, while WR is held low, the latches are transparent and
the switches respond to the address and enable inputs. This
input data is latched on the rising edge of WR.
Figure 2.
Figure 2 shows the Reset Pulse Width, tRS, and the Reset Turn
Off Time, tOFF (RS).
Note: All digital input signals rise and fall times are measured
from 10% to 90% of 3 V. tR = tF = 20 ns.
TERMINOLOGYVDDMost positive power supply potential.
VSSMost negative power supply potential in dual
supplies. In single supply applications, it may
be connected to ground.
GNDGround (0 V) reference.
RONOhmic resistance between D and S.
RON MatchDifference between the RON of any two
channels.
IS (OFF)Source leakage current when the switch is off.
ID (OFF)Drain leakage current when the switch is off.
ID, IS (ON)Channel leakage current when the switch
is on.
VD (VS)Analog voltage on terminals D, S.
CS (OFF)Channel input capacitance for “OFF”
condition.
CD (OFF)Channel output capacitance for “OFF”
condition.
CD, CS (ON)“ON” switch capacitance.
CINDigital input capacitance.
tON (EN)Delay time between the 50% and 90%
points of the digital input and switch “ON”
condition.
tOFF (EN)Delay time between the 50% and 90%
points of the digital input and switch “OFF”
condition.
tTRANSITIONDelay time between the 50% and 90%
points of the digital inputs and the switch
“ON” condition when switching from one
address state to another.
tOPEN“OFF” time measured between 80% points of
both switches when switching from one
address state to another.
VINLMaximum input voltage for logic “0.”
VINHMinimum input voltage for logic “1.”
IINL (IINH)Input current of the digital input.
CrosstalkA measure of unwanted signal which is
coupled through from one channel to another
as a result of parasitic capacitance.
Off IsolationA measure of unwanted signal coupling
through an “OFF” channel.
ChargeA measure of the glitch impulse
Injectiontransferred from the digital input to the analog
output during switching.
IDDPositive supply current.
ISSNegative supply current.
