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ADG3257BRQ
High Speed, 3.3 V/5 V Quad 2:1 Mux/Demux (4-Bit, 1 of 2) Bus Switch
REV.C
High Speed, 3.3 V/5 V Quad 2:1 Mux/Demux
(4-Bit, 1 of 2) Bus Switch
FUNCTIONAL BLOCK DIAGRAM
FEATURES
100 ps Propagation Delay through the Switch
2 � Switches Connect Inputs to Outputs
Data Rates up to 933 Mbps
Single 3.3 V/5 V Supply Operation
Level Translation Operation
Ultralow Quiescent Supply Current (1 nA Typical)
3.5 ns Switching
Standard ‘3257 Type Pinout
APPLICATIONS
Bus Switching
Bus Isolation
Level Translation
Memory Switching/Interleaving
PRODUCT HIGHLIGHTS0.1 ns propagation delay through switch2 Ω switches connect inputs to outputsBidirectional operationUltralow power dissipation16-lead QSOP package
Table I. Truth Table
GENERAL DESCRIPTIONThe ADG3257 is a CMOS bus switch comprised of four 2:1
multiplexers/demultiplexers with high impedance outputs. The
device is manufactured on a CMOS process. This provides low
power dissipation yet high switching speed and very low ON
resistance, allowing the inputs to be connected to the outputs
without adding propagation delay or generating additional ground
bounce noise.
The ADG3257 operates from a single 3.3V/5V supply. The
control logic for each switch is shown in Table I. These switches
are bidirectional when ON. In the OFF condition, signal levels are
blocked up to the supplies.
This bus switch is suited to both switching and level translation
applications. It may be used in applications requiring level
translation from 3.3 V to 2.5 V when powered from 3.3 V.
Additionally, with a diode connected in series with 5 V VDD,
the ADG3257 may also be used in applications requiring 5 V
to 3.3 V level translation.
ADG3257–SPECIFICATIONS1
(VCC = 5.0 V � 10%, GND = 0 V. All specifications TMIN to TMAX, unless otherwise noted.)CAPACITANCE
POWER REQUIREMENTS
NOTESTemperature range is as follows: B Version: –40°C to +85°C.See Test Circuits and Waveforms.All typical values are at TA = 25°C, unless otherwise noted.Guaranteed by design, not subject to production test.The digital switch contributes no propagation delay other than the RC delay of the typical RON of the switch and the load capacitance when driven by an ideal voltage
source. Since the time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to the system. Propagation delay
of the digital switch when used in a system is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side.Propagation delay matching between channels is calculated from ON resistance matching of worst-case channel combinations and load capacitance.This current applies to the control pins only and represents the current required to switch internal capacitance at the specified frequency. The A and B ports
contribute no significant ac or dc currents as they transition. This parameter is guaranteed by design, not subject to production test.
Specifications subject to change without notice.
ADG3257
SPECIFICATIONS1(VCC = 3.3 V � 10%, GND = 0 V. All specifications TMIN to TMAX, unless otherwise noted.)DC ELECTRICAL CHARACTERISTICS
CAPACITANCE
DIGITAL SWITCH
POWER REQUIREMENTS
NOTESTemperature range is as follows: B Version: –40°C to +85°C.See Test Circuits and Waveforms.All typical values are at TA = 25°C, unless otherwise noted.Guaranteed by design, not subject to production test.The digital switch contributes no propagation delay other than the RC delay of the typical RON of the switch and the load capacitance when driven by an ideal voltage
source. Since the time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to the system. Propagation delay
of the digital switch when used in a system is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side.Propagation delay matching between channels is calculated from ON resistance matching of worst-case channel combinations and load capacitance.This current applies to the control pins only and represents the current required to switch internal capacitance at the specified frequency. The A and B ports
contribute no significant ac or dc currents as they transition. This parameter is guaranteed by design, not subject to production test.
Specifications subject to change without notice.
ADG3257
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADG3257 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS*(TA = 25°C, unless otherwise noted.)
VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
Digital Inputs to GND . . . . . . . . . . . . . . . . . . .–0.3 V to +6 V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +6 V
DC Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . .–40°C to +85°C
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
QSOP Package
θJA Thermal Impedance . . . . . . . . . . . . . . . . . .149.97°C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . 300°C
IR Reflow, Peak Temperature (<20 sec) . . . . . . . . . . . 235°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
PIN CONFIGURATION
ORDERING GUIDE
PIN FUNCTION DESCRIPTIONS
TPC 1.ON Resistance vs. Input
Voltage
TPC 4. ON Resistance vs. Input
Voltage for Different Temperatures
INPUT VOLTAGE – V
OUTPUT VOLTAGE – V
0.51.01.52.53.53.02.0TPC 7.Max Pass Voltage
TPC 2.ON Resistance vs. Input
Voltage
TPC 5.ICC vs. Enable Frequency
TPC 8.622 Mbps Eye Diagram
VA/VB – V
– 012345TPC 3.ON Resistance vs. Input
Voltage for Different Temperatures
INPUT VOLTAGE – V
OUTPUT VOLTAGE – V12345TPC 6.Max Pass Voltage
TPC 9.933 Mbps Eye Diagram
ADG3257Figure 1. Load Circuit
Figure 2.Propagation Delay
CONTROL INPUTS
VIH
VOH
VOH – �V
VOL
VOL + �V
VCCOUTPUTtPZH
S1 @ 2 VCC
LOW
S1 @ 2 VCC
OUTPUT
ENABLEDISABLEFigure 3.Select, Enable, and Disable Times
Table II.Switch S1 Condition
Table III.Test Conditions
APPLICATIONS
Mixed Voltage Operation, Level TranslationBus switches can be used to provide a solution for mixed voltage
systems where interfacing bidirectionally between 5 V and 3 V
devices is required. To interface between 5 V and 3.3 V buses,
an external diode is placed in series with the 5 V power supply
as shown in Figure 4.
Figure 4.Level Translation Between 5 V and 3.3 V Devices
The diode drops the internal gate voltage down to 4.3 V.
The bus switch limits the voltage present on the output to
VCC – external diode drop = VTH.
Therefore, assuming a diode drop of 0.7 V and a VTH of 1 V,
the output voltage would be limited to 3.3 V with a logic high.
VIN
3.3V
VOUT
5V SUPPLY5VSWITCH INPUT
WITCH OUTPUTFigure 5.Input Voltage to Output Voltage
Similarly, the device could be used to translate bidirectionally
between 3.3 V to 2.5 V systems. In this case, there is no need
for an external diode. The internal VTH drop is 1 V, so with a
VCC = 3.3 V the bus switch will limit the output voltage to
VCC– 1 V = 2.3 V.
