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ADG1211YRUZ
2 pF Off Cap, 1 pC Qinj ± 15/12 V Quad SPST Switches
1 pF Off Capacitance, 1 pC Charge Injection,
±15 V/12 V iCMOS™ Quad SPST Switches
Rev. PrE
FEATURES
2 pF off capacitance
1 pC charge injection
33 V supply range
150 Ω on resistance
Fully specified at +12 V, ±15 V
No VL supply required
3 V logic-compatible inputs
Rail-to-rail operation
16-lead TSSOP and 16-lead LFCSP packages
Typical power consumption: <0.03 µW
APPLICATIONS
Automatic test equipment
Data aquisition systems
Battery-powered systems
Sample-and-hold systems
Audio signal routing
Video signal routing
Communication systems
GENERAL DESCRIPTION The ADG1211/ADG1212/ADG1213 are monolithic CMOS
devices containing four independently selectable switches
designed on an iCMOS process. iCMOS (industrial-CMOS) is a
modular manufacturing process combining high voltage CMOS
(complementary metal-oxide semiconductor) and bipolar
technologies. It enables the development of a wide range of high
performance analog ICs capable of 30 V operation in a footprint
that no previous generation of high voltage parts has been able
to achieve. Unlike analog ICs using conventional CMOS proc-
esses, iCMOS components can tolerate high supply voltages,
while providing increased performance, dramatically lower
power consumption, and reduced package size.
The ultralow capacitance and charge injection of these switches
make them ideal solutions for data acquisition and sample-and-
hold applications, where low glitch and fast settling are required.
Fast switching speed coupled with high signal bandwidth make
the parts suitable for video signal switching.
FUNCTIONAL BLOCK DIAGRAM
IN1
IN2
IN3
IN4
SWITCHES SHOWN FOR A LOGIC 1 INPUT
IN1
IN2
IN3
IN4
IN1
IN2
IN3
IN4Figure 1.
iCMOS construction ensures ultralow power dissipation,
making the parts ideally suited for portable and battery-
powered instruments.
The ADG1211/ADG1212/ADG1213 contain four independent
single-pole/single-throw (SPST) switches. The ADG1211 and
ADG1212 differ only in that the digital control logic is inverted.
The ADG1211 switches are turned on with Logic 0 on the
appropriate control input, while Logic 1 is required for the
ADG1212. The ADG1213 has two switches with digital control
logic similar to that of the ADG1211; the logic is inverted on the
other two switches. Each switch conducts equally well in both
directions when on, and has an input signal range that extends
to the supplies. In the off condition, signal levels up to the
supplies are blocked.
The ADG1213 exhibits break-before-make switching action for
use in multiplexer applications. Inherent in the design is low
charge injection for minimum transients when switching the
digital inputs.
PRODUCT HIGHLIGHTS 1. 2 pF off capacitance (±15 V supply).
2. 1 pC charge injection.
3. 3 V logic-compatible digital inputs: VIH = 2.0 V, VIL = 0.8 V.
4. No VL logic power supply required.
5. Ultralow power dissipation: <0.03 µW.
6. 16-lead TSSOP and 4 mm × 4 mm LFCSP packages.
TABLE OF CONTENTS Specifications.....................................................................................3
Single Supply.................................................................................3
Absolute Maximum Ratings............................................................6
ESD Caution..................................................................................6
Pin Configurations and Function Descriptions...........................7
Terminology.......................................................................................8
Typical Performance Characteristics..............................................9
Test Circuits.....................................................................................12
Outline Dimensions.......................................................................14
Ordering Guide..........................................................................14
REVISION HISTORY
11/04—Revision PrE: Preliminary Version
SPECIFICATIONS
SINGLE SUPPLY VDD = 15 V ± 10%, VSS = −15 V, GND = 0 V, unless otherwise noted.
Table 1.
1 Temperature range for Y Version is −40°C to +125°C. Guaranteed by design, not subject to production test.
VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 2. 1 Temperature range for Y Version is −40°C to +125°C. Guaranteed by design, not subject to production test.
ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted.
Table 3. 1 Overvoltages at IN, S, or D are clamped by internal diodes. Current should be
limited to the maximum ratings given.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability. Only one absolute maximum rating may be
applied at any one time.
Table 4. ADG1211/ADG1212 Truth Table
Table 5. ADG1213 Truth Table
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
TOP VIEW
ADG1211/
ADG1212/
ADG1213
NC = NO CONNECT
VSS
GND
IN1
VDD
IN4IN3
IN204788-0-002
Figure 2. TSSOP Pin Configuration
PIN 1
INDICATOR
NC = NO CONNECTS1VSSGNDS4VDDS2NC
9S3
TOP VIEWFigure 3. LFCSP Pin Configuration
Table 6. Pin Function Descriptions TERMINOLOGY
IDD The positive supply current.
ISS The negative supply current.
VD (VS) The analog voltage on Terminals D and S.
RON The ohmic resistance between D and S.
RFLAT(ON) Flatness is defined as the difference between the maximum and
minimum value of on resistance, as measured over the specified
analog signal range.
IS (Off) The source leakage current with the switch off.
ID (Off) The drain leakage current with the switch off.
ID, IS (On) The channel leakage current with the switch on.
VINL The maximum input voltage for Logic 0.
VINH The minimum input voltage for Logic 1.
IINL (IINH) The input current of the digital input.
CS (Off) The off switch source capacitance, measured with reference to
ground.
CD (Off) The off switch drain capacitance, measured with reference to
ground.
CD, CS (On) The on switch capacitance, measured with reference to ground.
CIN The digital input capacitance.
tON The delay between applying the digital control input and the
output switching on. See Figure 23.
tOFF The delay between applying the digital control input and the
output switching off.
Charge Injection A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
Off Isolation A measure of unwanted signal coupling through an off switch.
Crosstalk A measure of unwanted signal that is coupled through from one
channel to another as a result of parasitic capacitance.
Bandwidth The frequency at which the output is attenuated by 3 dB.
On Response The frequency response of the on switch.
Insertion Loss The loss due to the on resistance of the switch.
