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ADF7020BCP
High Performance ISM Band FSK/ASK Transceiver IC
High Performance ISM Band
FSK/ASK Transceiver IC
Rev. PrH
FEATURES
Low power, low IF transceiver
Frequency bands:
433 MHz to 464 MHz
862 MHz to 928 MHz
Data rates supported:
0.3 kbps to 200 kbps, FSK
0.3 kbps to 64 kbps, ASK
2.3 V to 3.6 V power supply
Programmable output power:
−16 dBm to +13 dBm in 0.3 dBm steps
Receiver sensitivity:
−117.5 dBm at 1 kbps, FSK
−110.5 dBm at 9.6 kbps, FSK
−106.5 dBm at 9.6 kbps, ASK
Low power consumption:
19 mA in receive mode
22 mA in transmit mode (10 dBm output)
On-chip VCO and fractional-N PLL
On-chip 7-bit ADC and temperature sensor
±1 ppm RF output frequency accuracy possible from
low cost 100 ppm crystal
Digital RSSI
Leakage current <1 µA in power-down mode
48-lead ultrasmall MLF package (chip scale)
APPLICATIONS
Low cost wireless data transfer
Remote control/security systems
Wireless metering
Keyless entry
Home automation
Process and building control
Wireless voice
FUNCTIONAL BLOCK DIAGRAM OUT
OSC
CLKOUT
VCOINCPOUT
MUXOUTADCINRSETVREG(1:4)
RLNA
RFIN
RFINB
SLE
SDATAIN
RxCLK
CLKOUT
SDATAOUT
SCLK
INT/LOCK
Tx/RxDATA01975-P
rG-001
Figure 1.
TABLE OF CONTENTS General Description.........................................................................3
Specifications.....................................................................................4
Timing Characteristics.....................................................................7
Absolute Maximum Ratings............................................................8
ESD Caution..................................................................................8
Pin Configuration and Function Descriptions.............................9
Frequency Synthesizer...................................................................11
Reference Input Section.............................................................11
Choosing Channels for Best System Performance.................13
Transmitter......................................................................................14
Modulation Schemes..................................................................14
Receiver Section..............................................................................16
RF Front End...............................................................................16
RSSI/AGC Section......................................................................17
FSK Demodulators on the ADF7020.......................................17
FSK Correlator/Demodulator...................................................17
Linear FSK Demodulator..........................................................19
AFC Section................................................................................19
Automatic Sync Word Recognition..........................................20
Applications Section.......................................................................21
LNA/PA Matching......................................................................21
Transmit Protocol and Coding Considerations.....................22
Image Rejection Calibration.....................................................22
Device Programming after Initial Power-Up.........................22
Serial Interface................................................................................24
Readback Format........................................................................24
Register 0—N Register...............................................................25
Register 1—Oscillator/Filter Register......................................26
Register 2—Transmit Modulation Register (ASK/OOK
Mode)...........................................................................................27
Register 2—Transmit Modulation Register (FSK Mode).....28
Register 2—Transmit Modulation Register (GFSK/GOOK
Mode)...........................................................................................29
Register 3—Receiver Clock Register.......................................30
Register 4—Demodulator Setup Register...............................31
Register 5—Sync Byte Register.................................................32
Register 6—Correlator/Demodulator Register......................33
Register 7—Readback Setup Register......................................34
Register 8—Power-Down Test Register..................................35
Register 9—AGC Register.........................................................36
Register 10—AGC 2 Register....................................................37
Register 11—AFC Register.......................................................37
Register 12—Test Register.........................................................38
Register 13—Offset Removal and Signal Gain Register.......39
Outline Dimensions.......................................................................40
Ordering Guide..........................................................................40
REVISION HISTORY Revision PrH: Preliminary Version
GENERAL DESCRIPTION The ADF7020 is a low power, highly integrated FSK/GFSK/
ASK/OOK/GASK transceiver designed for operation in the
license-free ISM bands at 433 MHz, 868 MHz, and 915 MHz. It
is suitable for circuit applications that meet either the European
ETSI-300-220 or the North American FCC (Part 15) regulatory
standards. A complete transceiver can be built using a small
number of external discrete components, making the ADF7020
very suitable for price-sensitive and area-sensitive applications.
The transmit section contains a VCO and low noise
fractional-N PLL with output resolution of <1 ppm. The VCO
operates at twice the fundamental frequency to reduce spurious
emissions and frequency pulling problems.
The transmitter output power is programmable in 0.3 dB steps
from −16 dBm to +13 dBm. The transceiver RF frequency,
channel spacing, and modulation are programmable using a
simple 3-wire interface. The device operates with a power
supply range of 2.3 V to 3.6 V and can be powered down when
not in use.
A low IF architecture is used in the receiver (200 kHz),
minimizing power consumption and the external component
count and avoiding interference problems at low frequencies.
The ADF7020 supports a wide variety of programmable
features including Rx linearity, sensitivity, and IF bandwidth,
allowing the user to trade off receiver sensitivity and selectivity
against current consumption, depending on the application. The
receiver also features a patent-pending automatic frequency
control (AFC) loop, allowing the PLL to track out the frequency
error in the incoming signal.
An on-chip ADC provides readback of an integrated tempera-
ture sensor, an external analog input, the battery voltage, or the
RSSI signal, which provides savings on an ADC in some
applications. The temperature sensor is accurate to ±5°C over
the full operating temperature range of −40°C to +85°C.
SPECIFICATIONS VDD = 2.3 V to 3.6 V, GND = 0 V, TA = TMIN to TMAX, unless otherwise noted.
Typical specifications are at VDD = 3 V, TA = 25°C.
All measurements are performed using the test circuit in Figure TBD using PN9 data sequence, unless otherwise noted.
Table 1.
Higher data rates are achievable depending on local regulations. For definition of frequency deviation, see the R section. egister 2—Transmit Modulation Register (FSK Mode)
3 For definition of GFSK frequency deviation, see the R section. egister 2—Transmit Modulation Register (GFSK/GOOK Mode) Measured as maximum unmodulated power. Output power varies with both supply and temperature.
5 For matching details, see the LN section. A/PA Matching See Table 5 for description of different receiver modes.
7 See Table 5 for description of different receiver modes. Follow the matching and layout guidelines to achieve the relevant FCC/ETSI specifications.
9 See the section. Image Rejection Calibration
TIMING CHARACTERISTICS VDD = 3 V ± 10%; VGND = 0 V, TA = 25°C, unless otherwise noted.
Guaranteed by design, but not production tested.
Table 2.
SCLK
SLESDATA01975-P
rG-002
Figure 2. Serial Interface Timing Diagram
t201975-P
rG-003
SCLK
SDATA
SLE
SREADFigure 3. Readback Timing Diagram
ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted.
Table 3. 1 GND = CPGND = RFGND = DGND = AGND = 0 V.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
This device is a high-performance RF integrated circuit with an
ESD rating of <2 kV and it is ESD sensitive. Proper precautions
should be taken for handling and assembly.
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VCOIN
VREG1
VDD1
RFOUT
RFGND
RFIN
RFINB
RLNA
VDD4
RSET
VREG4
GND4
FILT_IFILT_I
GND4
FILT_QFILT_Q
GND4
TEST_A
CLKOUT
DATA CLK
DATA I/O
INT/LOCK
VDD2
VREG2
ADCIN
GND2
SCLK
SREAD
SDATA
SLE
GND1GNDVCO GNDGNDVD
OUT
EG3
DD3
OSC1OSC2MUX01975-P
rG-004
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
FREQUENCY SYNTHESIZER
REFERENCE INPUT SECTION The on-board crystal oscillator circuitry (Figure 5) can use an
inexpensive quartz crystal as the PLL reference. The oscillator
circuit is enabled by setting R1_DB12 high. It is enabled by
default on power-up and is disabled by bringing CE low. Errors
in the crystal can be corrected using the automatic frequency
control (see the AFC Section) feature or by adjusting the
fractional-N value (see the N Counter section). A single-ended
reference (TCXO, CXO) can also be used. The CMOS levels
should be applied to OSC2 with R1_DB12 set low.
OSC101975-P
rG-005
Figure 5. Oscillator Circuit on the ADF7020
Two parallel resonant capacitors are required for oscillation at
the correct frequency; their values are dependent on the crystal
specification. They should be chosen so that the series value of
capacitance added to the PCB track capacitance adds up to the
load capacitance of the crystal, usually 20 pF. Track capacitance
values vary from 2 pF to 5 pF, depending on board layout.
Where possible, choose capacitors that have a very low
temperature coefficient to ensure stable frequency operation
over all conditions.
CLKOUT Divider and Buffer The CLKOUT circuit takes the reference clock signal from the
oscillator section, shown in Figure 5, and supplies a divided-
down 50:50 mark-space signal to the CLKOUT pin. An even
divide from 2 to 30 is available. This divide number is set in
R1_DB(8:11). On power-up, the CLKOUT defaults to
divide-by-8.
DVDD
CLKOUT
ENABLE BIT
CLKOUTOSC101975-P
rG-006÷2
Figure 6. CLKOUT Stage
To disable CLKOUT, set the divide number to 0. The output
buffer can drive up to a 20 pF load with a 10% rise time at
4.8 MHz. Faster edges can result in some spurious feedthrough
to the output. A small series resistor (50 Ω) can be used to slow
the clock edges to reduce these spurs at FCLK.
R Counter The 3-bit R counter divides the reference input frequency by an
integer from 1 to 7. The divided-down signal is presented as the
reference clock to the phase frequency detector (PFD). The
divide ratio is set in Register 1. Maximizing the PFD frequency
reduces the N value. This reduces the noise multiplied at a rate
of 20 log(N) to the output, as well as reducing occurrences of
spurious components. The R Register defaults to R = 1 on
power-up:
PFD [Hz] = XTAL/R
MUXOUT and Lock Detect The MUXOUT pin allows the user to access various digital
points in the ADF7020. The state of MUXOUT is controlled by
Bits R0_DB(29:31).
Regulator Ready REGULATOR READY is the default setting on MUXOUT after
the transceiver has been powered up. The power-up time of the
regulator is typically 50 µs. Because the serial interface is
powered from the regulator, the regulator must be at its nominal
voltage before the ADF7020 can be programmed. The status of
the regulator can be monitored at MUXOUT. When the
REGULATOR READY signal on MUXOUT is high,
programming of the ADF7020 can begin.
REGULATOR READY
DIGITAL LOCK DETECT
R COUNTER OUTPUT
N COUNTER OUTPUT
PLL TEST MODESΣ-∆ TEST MODES
DGND
DVDD
MUXOUT01975-P
rG-007
Figure 7. MUXOUT Circuit
Digital Lock Detect Digital lock detect is active high. The lock detect circuit is
located at the PFD. When the phase error on five consecutive
cycles is less than 15 ns, lock detect is set high. Lock detect
remains high until 25 ns phase error is detected at the PFD.
Because no external components are needed for digital lock
detect, it is more widely used than analog lock detect.
Analog Lock Detect This N-channel open-drain lock detect should be operated with
an external pull-up resistor of 10 kΩ nominal. When a lock has
been detected, this output is high with narrow low-going pulses.
Voltage Regulators The ADF7020 contains four regulators to supply stable voltages
to the part. The nominal regulator voltage is 2.3 V. Each
regulator should have a 100 nF capacitor connected between
VREG and GND. When CE is high, the regulators and other
associated circuitry are powered on, drawing a total supply
current of 2 mA. Bringing the chip-enable pin low disables the
regulators, reduces the supply current to less than 1 µA, and
erases all values held in the registers. The serial interface
operates off a regulator supply; therefore, to write to the part,
the user must have CE high and the regulator voltage must be
stabilized. Regulator status (VREG4) can be monitored using
the regulator ready signal from MUXOUT.
Loop Filter The loop filter integrates the current pulses from the charge
pump to form a voltage that tunes the output of the VCO to the
desired frequency. It also attenuates spurious levels generated by
the PLL. A typical loop filter design is shown in Figure 8.
01975-P
rG-008
CHARGE
PUMP OUTVCOFigure 8. Typical Loop Filter Configuration
In FSK, the loop should be designed so that the loop bandwidth
(LBW) is approximately five times the data rate. Widening the
LBW excessively reduces the time spent jumping between
frequencies, but can cause insufficient spurious attenuation.
For ASK systems, a wider LBW is recommended. The sudden
large transition between two power levels might result in VCO
pulling and can cause a wider output spectrum than is desired.
By widening the LBW to more than 10 times the data rate, the
amount of VCO pulling is reduced, because the loop settles
quickly back to the correct frequency. The wider LBW might
restrict the output power and data rate of ASK-based systems
compared with FSK-based systems.
Narrow-loop bandwidths can result in the loop taking long
periods of time to attain lock. Careful design of the loop filter is
critical to obtaining accurate FSK/GFSK modulation.
For GFSK, it is recommended that an LBW of 2.0 to 2.5 times
the data rate be used to ensure that sufficient samples are taken
of the input data while filtering system noise. The free design
tool ADIsimPLL can be used to design loop filters for the
ADF7020.
N Counter The feedback divider in the ADF7020 PLL consists of an 8-bit
integer counter and a 14-bit Σ-∆ fractional-N divider. The
integer counter is the standard pulse-swallow type common in
PLLs. This sets the minimum integer divide value to 31. The
fractional divide value gives very fine resolution at the output,
where the output frequency of the PLL is calculated as
FOUT = R
XTAL × (Integer-N + 142Fractional)
01975-P
rG-009
INTEGER-NFRACTIONAL-N
REFERENCE INFigure 9. Fractional-N PLL
The combination of the integer-N (maximum = 255) and the
fractional-N (maximum = 16383/16384) give a maximum N
divider of 255 + 1. Therefore, the minimum usable PFD is
PDFMIN [Hz] = Maximum Required Output Frequency/(255 + 1)
For example, when operating in the European 868 MHz to
870 MHz band, PFDMIN equals 3.4 MHz.
Voltage Controlled Oscillator (VCO) To minimize spurious emissions, the on-chip VCO operates
from 1732 MHz to 1856 MHz. The VCO signal is then divided
by 2 to give the required frequency for the transmitter and the
required LO frequency for the receiver.
The VCO should be recentered, depending on the required
frequency of operation, by programming the VCO adjust bits
R1_DB(20:21).
The VCO is enabled as part of the PLL by the PLL-enable bit,
R0_DB28.
A further frequency divide-by-2 is included to allow operation
in the lower 433 MHz and 460 MHz bands. To enable operation
in the these bands, R1_DB13 should be set to 1. The VCO needs
VCO Bias Current VCO bias current can be adjusted using Bits R1_DB19 to
R1_DB16. To ensure VCO oscillation, the minimum bias
current setting under typical conditions is 2.5 mA.
VCOLOOP FILTER
VCO SELECT BIT
TO PA AND
N DIVIDER
VCO BIAS
R1_DB (16:19)
220µF01975-P
rG-010
CVCO PINFigure 10. Voltage Controlled Oscillator (VCO)
CHOOSING CHANNELS FOR BEST SYSTEM
PERFORMANCE The fractional-N PLL allows the selection of any channel within
868 MHz to 928 MHz (and 433MHz using divide-by-2) to a
resolution of <100 Hz. This also facilitates frequency hopping
systems.
Careful selection of the RF transmit channels must be made to
achieve best spurious performance. The architecture of
fractional-N results in some level of the nearest integer channel
moving through the loop to the RF output. These “beat-note”
spurs are not attenuated by the loop, if the desired RF channel
and the nearest integer channel are separated by a frequency of
less than the LBW.
The occurrence of beat-note spurs is rare, because the integer
frequencies are at multiples of the reference, which is typically
>10 MHz.
Beat-note spurs can be significantly reduced in amplitude by
avoiding very small or very large values in the fractional
register, using the frequency doubler. By having a channel
1 MHz away from an integer frequency, a 100 kHz loop filter
can reduce the level to <−45 dBc. When using an external VCO,
the fast lock (bleed) function reduces the spurs to <−60 dBc for
the same conditions.
TRANSMITTER
RF OUTPUT STAGE The PA of the ADF7020 is based on a single-ended, controlled
current, open-drain amplifier that has been designed to deliver
up to 13 dBm into a 50 Ω load at a maximum frequency of
928 MHz.
The PA output current and, consequently, the output power are
programmable over a wide range. The PA configurations in
FSK/GFSK and ASK/OOK modulation modes are shown in
Figure 11 and Figure 12, respectively. In FSK/GFSK modulation
mode, the output power is independent of the state of the
DATA_IO pin. In ASK/OOK modulation mode, it is dependent
on the state of the DATA_IO pin and Bit R2_DB29, which
selects the polarity of the TxData input. For each transmission
mode, the output power can be adjusted as follows: FSK/GFSK: The output power is set using bits
R2_DB(9:14). ASK: The output power for the inactive state of the TxData
input is set by Bits R2_DB(15:20). The output power for the
active state of the TxData input is set by Bits R2_DB(9:14). OOK: The output power for the active state of the TxData
input is set by Bits R2_DB(9:14). The PA is muted when the
TxData input is inactive.
R2_DB(9:14)
R2_DB4
R2_DB5
DIGITALLOCK DETECT
R2_DB(30:31)
RFGND
RFOUT
FROM VCO01975-P
rG-011
Figure 11. PA Configuration in FSK/GFSK Mode
R2_DB(9:14)
R2_DB(15:23)
R2_DB4
R2_DB5
DIGITAL
LOCK DETECT
R2_DB(30:31)
R2_DB29
RFGND
RFOUTrG-012
ASK/OOK MODEThe PA is equipped with overvoltage protection, which makes it
robust in severe mismatch conditions. Depending on the
application, one can design a matching network for the PA to
exhibit optimum efficiency at the desired radiated output power
level for a wide range of different antennas, such as loop or
monopole antennas. See the LNA/PA Matching section for
details.
PA Bias Currents and Mute PA until Lock Bit Control Bits R2_DB(30:31) facilitate an adjustment of the PA
bias current to further extend the output power control range, if
necessary. If this feature is not required, the default value of
7 µA is recommended. The output stage is powered down by
resetting Bit R2_DB4. To reduce the level of undesired spurious
emissions, the PA can be muted during the PLL lock phase by
setting Bit R2_DB5 (mute PA until lock bit).
MODULATION SCHEMES
Frequency Shift Keying (FSK) Frequency shift keying is implemented by setting the N value
for the center frequency and then toggling this with the TxData
line. The deviation from the center frequency is set using Bits
R2_DB(15:23). The deviation from the center frequency in Hz
is 142Hz][NumberPFDFSKDEVIATION×=
where Modulation Number is a number from 1 to 511
(R2_DB(15:23)) .
Select FSK using Bits R2_DB(6:8).
01975-P
rG-013
INTEGER-N
PA STAGEFigure 13. FSK Implementation
Gaussian Frequency Shift Keying (GFSK) Gaussian frequency shift keying reduces the bandwidth
occupied by the transmitted spectrum by digitally prefiltering
the TxData. A TxCLK output line is provided from the
ADF7020 for synchronization of TxData from the micro-
controller. The TxCLK line can be connected to the clock input
of a shift register that clocks data to the transmitter at the exact
data rate.
Setting Up the ADF7020 for GFSK To set up the frequency deviation, set the PFD and the mod
control bits: 2]Hz[
DEVIATIONPFDGFSK×=
where m is GFSK_MOD_CONTROL set using R2_DB(24:26).
To set up the GFSK data rate:
COUNTERINDEXFACTORDIVIDER
PFDDR__]bps[×=
For further information, see the application note, Using GFSK
on the ADF7010, in the EVAL-ADF7010EB1 Technical Note.
Amplitude Shift Keying (ASK) Amplitude shift keying is implemented by switching the output
stage between two discrete power levels. This is accomplished
by toggling the DAC, which controls the output level between
two 6-bit values set up in Register 2. A zero TxData bit sends
Bits R2_DB(15:20) to the DAC. A high TxData bit sends Bits
R2_DB(9:14) to the DAC. A maximum modulation depth of
30 dB is possible.
On-Off Keying (OOK) On-off keying is implemented by switching the output stage to a
certain power level for a high TxData bit and switching the
output stage off for a zero. For OOK, the transmitted power for
a high input is programmed using Bits R2_DB(9:14).
Gaussian On-Off Keying (G-OOK) Gaussian on-off keying represents a prefiltered form of OOK
modulation. The usually sharp symbol transitions are replaced
with smooth Gaussian filtered transitions, the result being a
reduction in frequency pulling of the VCO. Frequency pulling
of the VCO in OOK mode can lead to a wider than desired BW,
especially if it is not possible to increase the loop filter BW >
300 kHz. The G-OOK sampling clock samples data at the data
rate. (See the Setting Up the ADF7020 for GFSK section.)
RECEIVER SECTION
RF FRONT END The ADF7020 is based on a fully integrated, low IF receiver
architecture. The low IF architecture facilitates a very low
external component count and does not suffer from power-line-
induced interference problems.
Figure 14 shows the structure of the receiver front end. The
many programming options allow users to trade off sensitivity,
linearity, and current consumption against each other in the
way best suitable for their applications. To achieve a high level
of resilience against spurious reception, the LNA features a
differential input. Switch SW2 shorts the LNA input when
transmit mode is selected (R0_DB27 = 0). This feature
facilitates the design of a combined LNA/PA matching network,
avoiding the need for an external Rx/Tx switch. See the LNA/PA
Matching section for details on the design of the matching
network.
01975-P
rG-014
RFIN
RFINB
Tx/Rx SELECT
[R0_DB27]
LNA MODE
[R6_DB15]
LNA CURRENT
[R6_DB(16:17)]
MIXER LINEARITY
[R6_DB18]
I (TO FILTER)
Q (TO FILTER)
LNA GAIN
[R9_DB(20:21)]
LNA/MIXER ENABLE
[R8_DB6] Figure 14. ADF7020 RF Front End
The LNA is followed by a quadrature downconversion mixer,
which converts the RF signal to the IF frequency of 200 kHz. It
is important to consider that the output frequency of the
synthesizer must be programmed to a value 200 kHz below the
center frequency of the received channel.
The LNA has two basic operating modes: high gain/low noise
mode and low gain/low power mode. To switch between these
two modes, use the LNA_mode bit, R6_DB15. The mixer is also
configurable between a low current and an enhanced linearity
mode using the mixer_linearity bit, R6_DB18.
Based on the specific sensitivity and linearity requirements of
the application, it is recommended to adjust control bits
LNA_mode (R6_DB15) and mixer_linearity (R6_DB18) as
outlined in Table 5.
The gain of the LNA is configured by the LNA_gain field,
R9_DB(20:21), and can be set by either the user or the AGC
logic.
IF Filter Settings/Calibration Out-of-band interference is rejected by means of a fourth-order
Butterworth polyphase IF filter centered around a frequency of
200 kHz. The bandwidth of the IF filter can be programmed
between 100 kHz and 200 kHz by means of Control Bits
R1_DB(22:23), and should be chosen as a compromise between
interference rejection, attenuation of the desired signal, and the
AFC pull-in range.
To compensate for manufacturing tolerances, the IF filter
should be calibrated once after power-up. The IF filter
calibration logic requires that the IF filter divider in Bits
R6_DB(20:28) be set dependent on the crystal frequency. Once
initiated by setting Bit R6_DB19, the calibration is performed
automatically without any user intervention. The calibration
time is 200 µs, during which the ADF7020 should not be
accessed. It is important not to initiate the calibration cycle
before the crystal oscillator has fully settled. If the AGC loop is
disabled, the gain of IF filter can be set to three levels using the
filter_gain field, R9_DB(20:21). The filter gain is adjusted
automatically, if the AGC loop is enabled.
The signal in the image channel of the low IF mixer, located at a
frequency of 400 kHz below the desired channel, is rejected due
to the image rejection of the polyphase filter. The image
rejection performance of the IF filter is subject to manufactur-
ing tolerances, and, to some extent, temperature drift. To
improve the image rejection, a calibration procedure can be
performed as outlined in the Image Rejection Calibration
section.
Table 5. LNA/Mixer Modes
RSSI/AGC SECTION The RSSI is implemented as a successive compression log amp
following the base-band channel filtering. The log amp achieves
±3 dB log linearity. It also doubles as a limiter to convert the
signal-to-digital levels for the FSK demodulator. The RSSI itself
is used for amplitude shift keying (ASK) demodulation. In ASK
mode, extra digital filtering is performed on the RSSI value.
Offset correction is achieved using a switched capacitor integra-
tor in feedback around the log amp. This uses the BB offset
clock divide. The RSSI level is converted for user readback and
digitally controlled AGC by an 80-level (7-bit) flash ADC. This
level can be converted to input power in dBm.
CLK
RSSI
FSK
DEMOD01975-P
rG-015
Figure 15. RSSI Block Diagram
RSSI Thresholds When the RSSI is above AGC_HIGH_THRESHOLD, the gain is
reduced. When the RSSI is below AGC_LOW_THRESHOLD,
the gain is increased. A delay (AGC_DELAY) is programmed to
allow for settling of the loop. The user programs the two
threshold values (recommended defaults, 27 and 76) and the
delay (default, 10). The default AGC setup values should be
adequate for most applications. The threshold values must be
chosen to be more than 30 apart for the AGC to operate
correctly.
Offset Correction Clock In Register 3, the user should set the BB offset clock divide bits
R3_DB(4:5) to give an offset clock between 1 MHz and 2 MHz,
where:
BBOS _CLK [Hz] = XTAL/(BBOS_CLK_DIVIDE)
BBOS_CLK_DIVIDE can be set to 4, 8, or 16.
AGC Information In Register 9, the user should select automatic gain control by
selecting auto in R9_DB18 and auto in R9_DB19. The user
should then program AGC low threshold R9_DB(4:10) and
AGC high threshold R9_DB(11:17). The recommended/default
values for the low and high thresholds are 30 and 70, respec-
tively. In the AGC2 register the user should program the AGC
delay to be long enough to allow the loop to settle. The
recommended value is 10.
RSSI Formula (Converting to dBm) Input_Power [dBm] = −110 dBm + (Readback_Code +
Gain_Mode_Correction ) × 0.5
where:
Readback_Code is given by Bits RV7 to RV1 in the readback
register (see Readback Format section).
Gain_Mode_Correction is given by the values in Table 6.
LNA gain and filter gain (LG2/LG1, FG2/FG1) are also obtained
from the readback register.
Table 6. Gain Mode Correction Table An additional factor should be introduced to account for losses
in the front-end matching network/antenna.
FSK DEMODULATORS ON THE ADF7020 The two FSK demodulators on the ADF7020 are FSK correlator/demodulator Linear demodulator
Select these using the demod select bits, R4_DB(4:5).
FSK CORRELATOR/DEMODULATOR The quadrature outputs of the IF filter are first limited and then
fed to a pair of digital frequency correlators that perform band-
pass filtering of the binary FSK frequencies at (IF + FDEV) and
(IF − FDEV). Data is recovered by comparing the output levels
from each of the two correlators. The performance of this
frequency discriminator approximates that of a matched filter
detector, which is known to provide optimum detection in the
presence of AWGN.
LIMITERS
DB(4:13)DB(8:15)DB(14)
Rx DATA
Rx CLK
SLICERFREQUENCY CORRELATOR01975-P
rG-016
Figure 16. FSK Correlator/Demodulator Block Diagram
Postdemodulator Filter A second-order, digital low-pass filter removes excess noise
from the demodulated bit stream at the output of the
discriminator. The bandwidth of this postdemodulator filter is
programmable and must be optimized for the user’s data rate. If
the bandwidth is set too narrow, performance is degraded due
to intersymbol interference (ISI). If the bandwidth is set too
wide, excess noise degrades the receiver’s performance.
Typically, the 3 dB bandwidth of this filter is set at
approximately 0.75 times the user’s data rate, using Bits
R4_DB(6:15).
Bit Slicer The received data is recovered by threshold detecting the output
of the postdemodulator low-pass filter. In the correlator/
demodulator, the binary output signal levels of the frequency
discriminator are always centered on zero. Therefore, the slicer
threshold level can be fixed at zero and the demodulator
performance is independent of the run-length constraints of the
transmit data bit stream. This results in robust data recovery,
which does not suffer from the classic baseline wander
problems that exist in the more traditional FSK demodulators.
Frequency errors are removed by an internal AFC loop that
measures the average IF frequency at the limiter output and
applies a frequency correction value to the fractional-N
synthesizer. This loop should be activated when the frequency
errors are greater than approximately 40% of the transmit
frequency deviation (see the AFC Section).
Data Synchronizer An oversampled digital PLL is used to resynchronize the
received bit stream to a local clock. The oversampled clock rate
of the PLL (CDR_CLK) must be set at 32 times the data rate.
See the notes for the Register 3—Receiver Clock Register
section for a definition of how to program. The clock recovery
PLL can accommodate frequency errors of up to ±2%.
FSK Correlator Register Settings To enable the FSK correlator/demodulator, Bits R4_DB(5:4)
should be set to [01]. To achieve best performance, the
bandwidth of the FSK correlator must be optimized for the
specific deviation frequency that is used by the FSK transmitter.
The discriminator BW is controlled in Register 6 by
R6_DB(4:13) and is defined as 10800/()_(_3××=KCLKDEMODBWtorDiscrimina
where:
DEMOD_CLK is as defined in the Register 3—Receiver Clock
Register section, Note 2.
K = Round(200e3/FSK Deviation)
To optimize the coefficients of the FSK correlator, two
additional bits, R6_DB14 and R6_DB29, must be assigned. The
value of these bits depends on whether K (as defined above) is
odd or even. These bits are assigned according to Table 7 and
Table 8.
Table 7. When K Is Even
Table 8. When K Is Odd
Postdemodulator Bandwidth Register Settings The 3 dB bandwidth of the postdemodulator filter is controlled
by Bits R4_ DB(6:15) and is given by
CLKDEMODBWSettingDemodPostCUTOFF2__×π×=
where FCUTOFF is the target 3 dB bandwidth in Hz of the
postdemodulator filter. This should typically be set to 0.75 times
the data rate (DR).
Some sample settings for the FSK correlator/demodulator are
DEMOD_CLK = 5 MHz
DR = 9.6 kbps
FDEV = 20 kHz
Therefore,
FCUTOFF = 0.75 × 9.6 × 103 Hz
Post_Demod_BW = 211 π 7.2 × 103 Hz/(5 MHz)
Post_Demod_BW = Round(9.26) = 9
and
K = Round(200 kHz)/20 kHz) = 10
Discriminator_BW = (5 MHz × 10)/(800 × 103) = 62.5 =
63 (rounded to nearest integer)
Table 9. LINEAR FSK DEMODULATOR A block diagram of the linear FSK demodulator is shown in
Figure 17.
SLICER
LIMITER
MUX 1
LINEAR DISCRIMINATOR
DB(6:15)
FREQUENCY
READBACK
AND
AFC LOOP
Rx DATA01975-P
rG-017
Figure 17. Block Diagram of Frequency Measurement System and
ASK.OOK/Linear FSK Demodulator
This method of frequency demodulation is useful when very
short preamble length is required and the system protocol
cannot support the overhead of the settling time of the internal
feedback AFC loop settling.
A digital frequency discriminator provides an output signal that
is linearly proportional to the frequency of the limiter outputs.
The discriminator output is then filtered and averaged using a
combined averaging filter and envelope detector. The demodu-
lated FSK data is recovered by threshold-detecting the output of
the averaging filter, as shown in Figure 17. In this mode, the
slicer output shown in Figure 17 is routed to the data synchro-
nizer PLL for clock synchronization. To enable the linear FSK
demodulator, set Bits R4_DB(4:5) to [00].
The 3 dB bandwidth of the postdemodulation filter is set in the
same way as the FSK correlator/demodulator, which is set in
R4_DB(6:15) and is defined as
CLKDEMODSettingBWDemodPostCUTOFF2___×π×=
where:
FCUTOFF is the target 3 dB bandwidth in Hz of the
postdemodulator filter.
DEMOD_CLK is as defined in the Register 3—Receiver Clock
Register section, Note 2.
ASK/OOK Operation ASK/OOK demodulation is activated by setting Bits
R4_DB(4:5) to [10].
Digital filtering and envelope detecting the digitized RSSI input
via MUX 1, as shown in Figure 17, perform ASK/OOK
demodulation. The bandwidth of the digital filter must be
optimized to remove any excess noise without causing ISI in the
The 3 dB bandwidth of this filter is typically set at approxi-
mately 0.75 times the user data rate and is assigned by R4
_DB(6:15) as
Post_Demod_BW_Setting = DEMOD_CLKCUTOFF×π×2210
where FCUTOFF is the target 3 dB bandwidth in Hz of the
postdemodulator filter.
AFC SECTION The ADF7020 supports a real-time AFC loop, which is used to
remove frequency errors that can arise due to mismatches
between the transmit and receive crystals. This uses the
frequency discriminator block, as described in the Linear FSK
Demodulator section (see Figure 17). The discriminator output
is filtered and averaged to remove the FSK frequency
modulation using a combined averaging filter and envelope
detector. In FSK mode, the output of the envelope detector
provides an estimate of the average IF frequency.
Two methods of AFC, external and internal, are supported on
the ADF7020 (in FSK mode only).
External AFC The user reads back the frequency information through the
ADF7020 serial port and applies a frequency correction value to
the fractional-N synthesizer’s N divider.
The frequency information is obtained by reading the 16-bit
signed AFC_readback, as described in the Readback Format
section, and applying the following formula:
FREQ_RB [Hz] = (AFC_READBACK × DEMOD_CLK)/215
Note that while the AFC_READBACK value is a signed number,
under normal operating conditions it is positive. In the absence
of frequency errors, the FREQ_RB value is equal to the IF
frequency of 200 kHz.
Internal AFC The ADF7020 supports a real-time internal automatic
frequency control loop. In this mode, an internal control loop
automatically monitors the frequency error and adjusts the
synthesizer N divider using an internal PI control loop.
The internal AFC control loop parameters are controlled in
Register 11. The internal AFC loop is activated by setting
R11_DB20 to 1. A scaling coefficient must also be entered,
based on the crystal frequency in use. This is set up in
R11_DB(4:19) and should be calculated using
AFC_Scaling_Coefficient = (500 × 224)/XTAL
Therefore, using a 10 MHz XTAL yields an AFC scaling
Maximum AFC Range The maximum AFC frequency range is ±100 kHz. This is set by
the maximum IF filter bandwidth of 200 kHz. Using the
minimum IF filter bandwidth of 100 kHz, the AFC range is
±50 kHz.
When AFC errors have been removed using either the internal
or external AFC, further improvement in the receiver’s sensi-
tivity can be obtained by reducing the IF filter bandwidth using
Bits R1_DB(22:23).
AUTOMATIC SYNC WORD RECOGNITION The ADF7020 also supports automatic detection of the sync or
ID fields. To activate this mode, the sync (or ID) word must be
preprogrammed into the ADF7020. In receive mode, this
preprogrammed word is compared to the received bit stream
and, when a valid match is identified, the external pin
INT/LOCK is asserted by the ADF7020.
This feature can be used to alert the microprocessor that a valid
channel has been detected. It relaxes the computational
requirements of the microprocessor and reduces the overall
power consumption. The INT/LOCK is automatically de-
asserted again after nine data clock cycles.
The automatic sync/ID word detection feature is enabled by
selecting demod mode 2 or 3 in the demodulator setup register.
Do this by setting R4_DB(25:23) = [010] or [011]. Bits
R5_DB(4:5) are used to set the length of the sync/ID word,
which can be either 12, 16, 20, or 24 bits long. The transmitter
must transmit the MSB of the sync byte first and the LSB last to
ensure proper alignment in the receiver sync byte detection
hardware.
For systems using FEC, an error tolerance parameter can also be
programmed that accepts a valid match when up to three bits of
the word are incorrect. The error tolerance value is assigned in
R5_DB(6:7).
