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ADF7010BRU
High Performance ISM Band ASK/FSK/GFSK Transmitter IC
REV.0
High Performance ISM Band
ASK/FSK/GFSK Transmitter IC
FEATURES
Single Chip Low Power UHF Transmitter
902 MHz–928 MHz Frequency Band
On-Chip VCO and Fractional-N PLL
2.3 V–3.6 V Supply Voltage
Programmable Output Power
–16 dBm to +12 dBm, 0.3 dB Steps
Data Rates up to 76.8 kbps
Low Current Consumption
28 mA at 8 dBm Output
Power-Down Mode (<1 �A)
24-Lead TSSOP Package
APPLICATIONS
Low Cost Wireless Data Transfer
Wireless Metering
Remote Control/Security Systems
Keyless Entry
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTIONThe ADF7010 is a low power OOK/ASK/FSK/GFSK UHF
transmitter designed for use in ISM band systems. It contains
an integrated VCO and sigma-delta fractional-N PLL. The
output power, channel spacing, and output frequency are pro-
grammable with four 24-bit registers. The fractional-N PLL
enables the user to select any channel frequency within the U.S.
902 MHz–928 MHz band, allowing the use of the ADF7010 in
frequency hopping systems.
It is possible to choose from the four different modulation
schemes: Binary or Gaussian Frequency Shift Keying (FSK/
GFSK), Amplitude Shift Keying (ASK), or On/Off Keying
(OOK). The device also features a crystal compensation register
that can provide �1 ppm resolution in the output frequency.
Indirect temperature compensation of the crystal can be accom-
plished inexpensively using this register.
Control of the four on-chip registers is via a simple 3-wire inter-
face. The devices operate with a power supply ranging from
2.3 V to 3.6 V and can be powered down when not in use.
ADF7010–SPECIFICATIONS1(VDD = 2.3 V to 3.6 V, GND = 0 V, TA = TMIN to TMAX, unless otherwise noted. Typical
specifications are at VDD = 3 V, TA = 25�C.)
ADF7010REFERENCE INPUT
FREQUENCY COMPENSATION
TIMING INFORMATION
NOTESOperating temperature range is as follows: –40∞C to +85∞C.Frequency Deviation = (PFD Frequency � Mod Deviation )/212.GFSK Frequency Deviation = (PFD Frequency � 2m)/212 where m = Mod Control.VDD = 3 V, PFD = 19.2 MHz, PA = 8 dBmVDD = 3 V, Loop Filter BW = 100 kHzMeasured >1 MHz away from integer channel. See Successful Design with ADF7010 Transmitter application note.Not production tested. Based on characterization.
Specifications subject to change without notice.
ADF7010
TIMING CHARACTERISTICSGuaranteed by design but not production tested.
Figure 1. Timing Diagram
(VDD = 3 V �10%, VGND = 0 V, TA = 25�C, unless otherwise noted.)
ABSOLUTE MAXIMUM RATINGS1, 2(TA = 25∞C, unless otherwise noted.)
VDD to GND3 . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +4.0 V
VCOVDD, RFVDD, CPVDD to GND . . . . . –0.3 V to +7 V
Digital I/O Voltage to GND . . . . . . –0.3 V to DVDD + 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . –40∞C to +85∞C
Storage Temperature Range . . . . . . . . . . . . –65∞C to +125∞C
Maximum Junction Temperature . . . . . . . . . . . . . . . . . 125∞C
TSSOP �JA Thermal Impedance . . . . . . . . . . . . . . 150.4∞C/W
CSP �JA (Paddle Soldered) . . . . . . . . . . . . . . . . . . . . 122∞C/W
CSP �JA (Paddle Not Soldered) . . . . . . . . . . . . . . . . . 216∞C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 235∞C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240∞C
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.This device is a high performance RF integrated circuit with an ESD rating of
<1 kV and it is ESD sensitive. Proper precautions should be taken for handling and
assembly.GND = CPGND = RFGND = DGND = AGND = 0 V.
ORDERING GUIDE
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
PIN FUNCTION DESCRIPTIONS4CPOUT
5CEChip Enable. A logic low applied to this pin powers down the part. This must be high for the part to
8LELoad Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one
PIN CONFIGURATION
ADF7010
PIN FUNCTION DESCRIPTIONS (continued)TPC 1.FSK Modulated Signal, FDEVIATION = 58 kHz,
Data Rate = 19.2 kbps/s, 10 dBm
TPC 2.OOK Modulated Signal, Data Rate = 4.8 kbps/s, 4 dBm
TPC 3.Harmonic Levels at 10 dBm Output Power.
See Figure 15.
TPC 4.PLL Settling Time, 902 MHz to 928 MHz,
23 �s (±400 kHz)
TPC 5.PFD Spurious/Fractional Spurious
TPC 6.In-Band Phase Noise
ADF7010TPC 7.1.6 MHz CLOCKOUT Waveform
TPC 8.Spurious Signal Generated by CLOCKOUT
TPC 9.N-Divider Input Sensitivity
TPC 10.Typical VCO Gain
TPC 11.PA Output Programmability, TA = 25∞C
TPC 12.IDD vs. VDD @ 10 dBm
REGISTER MAPS
ADF7010
RF R REGISTER
