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ADF4360-8BCP
Integrated Synthesizer and VCO
Integrated Synthesizer and VCORev. 0
FEATURES
Output frequency range: 65 MHz to 400 MHz
3.0 V to 3.6 V power supply
1.8 V logic compatibility
Integer-N synthesizer
Programmable output power level
3-wire serial interface
Digital lock detect
Hardware and software power-down mode
APPLICATIONS
System clock generation
Test equipment
Wireless LANs
CATV equipment
GENERAL DESCRIPTION The ADF4360-8 is an integrated integer-N synthesizer and
voltage controlled oscillator (VCO). The ADF4360-8 center
frequency is set by external inductors. This allows a frequency
range of between 65 MHz to 400 MHz.
Control of all the on-chip registers is through a simple 3-wire
interface. The device operates with a power supply ranging from
3.0 V to 3.6 V and can be powered down when not in use.
FUNCTIONAL BLOCK DIAGRAM
MUXOUT
VVCO
REFIN
CLK
DATA
AVDDDVDDCE
AGNDDGNDCPGND
RSET
VTUNE
RFOUTA
RFOUTBFigure 1.
TABLE OF CONTENTS Specifications.....................................................................................3
Timing Characteristics.....................................................................5
Absolute Maximum Ratings............................................................6
Transistor Count...........................................................................6
ESD Caution..................................................................................6
Pin Configuration and Function Descriptions.............................7
Typical Performance Characteristics.............................................8
Circuit Description.........................................................................10
Reference Input Section.............................................................10
N Counter....................................................................................10
R Counter....................................................................................10
PFD and Charge Pump..............................................................10
MUXOUT and Lock Detect......................................................10
Input Shift Register.....................................................................11
VCO.............................................................................................11
Output Stage................................................................................12
Latch Structure...........................................................................13
Control Latch..............................................................................17
N Counter Latch.........................................................................18
R Counter Latch.........................................................................18
Choosing the Correct Inductance Value.................................19
Fixed Frequency LO...................................................................19
Power-Up.....................................................................................20
Interfacing...................................................................................20
PCB Design Guidelines for Chip Scale Package...........................20
Output Matching........................................................................21
Outline Dimensions.......................................................................22
Ordering Guide..........................................................................22
REVISION HISTORY
10/04—Revision 0: Initial Version SPECIFICATIONS1 AVDD = DVDD = VVCO = 3.3 V ± 10%; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted.
Table 1. Specifications continued on next page.
Footnotes on next page.
1 Operating temperature range is –40°C to +85°C. Guaranteed by design. Sample tested to ensure compliance.
3 ICP is internally modified to maintain constant loop gain over the frequency range. TA = 25°C; AVDD = DVDD = VVCO = 3.3 V.
5 Unless otherwise stated, these characteristics are guaranteed for VCO core power = 5 mA. L1, L2 = 270 nH, 470 Ω resistors to GND in parallel with L1, L2. Jumping from 88 MHz to 108 MHz. PFD frequency = 200 kHz; loop bandwidth = 10 kHz.
7 For more detail on using tuned loads, see Output Matching section. Using 50 Ω resistors to VVCO, into a 50 Ω load.
9 The noise of the VCO is measured in open-loop conditions. The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider value). The
phase noise figure of merit subtracts 10 log (PFD frequency). The phase noise is measured with the EVAL-ADF4360-xEB1 Evaluation Board and the HP 8562E Spectrum Analyzer. The Spectrum Analyzer provides the REFIN for the
synthesizer; offset frequency = 1 kHz. fREFIN = 10 MHz; fPFD = 200 kHz; N = 1000; Loop B/W = 10 kHz.
13 fREFIN = 10 MHz; fPFD = 1 MHz; N = 120; Loop B/W = 100 kHz. The spurious signals are measured with the EVAL-ADF4360-xEB1 Evaluation Board and the HP 8562E Spectrum Analyzer. The Spectrum Analyzer provides the REFIN
for the synthesizer; fREFOUT = 10 MHz @ 0 dBm.
TIMING CHARACTERISTICS AVDD = DVDD = VVCO = 3.3 V ± 10%; AGND = DGND = 0 V; 1.8 V and 3 V logic levels used; TA = TMIN to TMAX, unless otherwise noted.
Table 2.
CLOCK
DATAt3t5 Figure 2. Timing Diagram
ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted.
Table 3. 1 GND = AGND = DGND = 0 V.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may affect device
reliability.
This device is a high performance RF integrated circuit with an
ESD rating of <1 kV, and it is ESD sensitive. Proper precautions
should be taken for handling and assembly.
TRANSISTOR COUNT 12543 (CMOS) and 700 (Bipolar)
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features proprie-
tary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic
discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of
functionality.
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADF4360-8
TOP VIEW
(Not to Scale)
CPGND
AVDD
AGND
RFOUTA
RFOUTB
VVCO
DATA
CLK
REFIN
DGND
RSET
TUNE
AGND
AGND
AGNDPIN 1
IDENTIFIER
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
TYPICAL PERFORMANCE CHARACTERISTICS
1001k10k100k1M10M
FREQUENCY OFFSET (Hz)
OUTP
UT P
R (dB)Figure 4. Open-Loop VCO Phase Noise, L1, L2 = 560 nH
1001k10k100k1M10M
FREQUENCY OFFSET (Hz)
OUTP
UT P
R (dB)Figure 5. VCO Phase Noise, 65 MHz, 1 MHz PFD, 100 kHz Loop Bandwidth
OUTP
UT P
R (dB)
–2kHz–1kHz65MHz1kHz2kHz
Figure 6. Close-In Phase Noise at 65 MHz (1 MHz Channel Spacing)
OUTP
UT P
R (dB)
–1.1MHz–0.55MHz65MHz0.55MHz1.1MHz
Figure 7. Reference Spurs at 65 MHz
(1 MHz Channel Spacing, 100 kHz Loop Bandwidth)
1001k10k100k1M10M
FREQUENCY OFFSET (Hz)
OUTP
UT P
R (dB)Figure 8. Open-Loop VCO Phase Noise, L1, L2 = 110 nH
1001k10k100k1M10M
FREQUENCY OFFSET (Hz)
OUTP
UT P
R (dB)Figure 9. VCO Phase Noise, 160 MHz, 1 MHz PFD, 100 kHz Loop Bandwidth
OUTP
UT P
R (dB)
–2kHz–1kHz160MHz1kHz2kHz
Figure 10. Close-In Phase Noise at 160 MHz (1 MHz Channel Spacing)
OUTP
UT P
R (dB)
–1.1MHz–0.55MHz160MHz0.55MHz1.1MHz
Figure 11. Reference Spurs at 160 MHz
(1 MHz Channel Spacing, 100 kHz Loop Bandwidth)
1001k10k100k1M10M
FREQUENCY OFFSET (Hz)
OUTP
UT P
R (dB)Figure 12. Open-Loop VCO Phase Noise, L1, L2 = 18 nH
1001k10k100k1M10M
FREQUENCY OFFSET (Hz)
OUTP
UT P
R (dB)Figure 13. VCO Phase Noise, 400 MHz, 1 MHz PFD, 100 kHz Loop Bandwidth
OUTP
UT P
R (dB)
–2kHz–1kHz400MHz1kHz2kHz
Figure 14. Close-In Phase Noise at 400 MHz (1 MHz Channel Spacing)
OUTP
UT P
R (dB)
–1.1MHz–0.55MHz400MHz0.55MHz1.1MHz
Figure 15. Reference Spurs at 400 MHz
(1 MHz Channel Spacing, 100 kHz Loop Bandwidth)
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION The reference input stage is shown in Figure 16. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed, and SW1 and SW2 are
opened. This ensures that there is no loading of the REFIN pin
on power-down.
TO R COUNTERREFIN
100kΩ
SW1
POWER-DOWN
CONTROL
Figure 16. Reference Input Stage
N COUNTER The CMOS N counter allows a wide division ratio in the PLL
feedback counter. The counters are specified to work when
the VCO output is 400 MHz or less. To avoid confusion, this is
referred to as the B counter. It makes it possible to generate
output frequencies that are spaced only by the reference
frequency divided by R. The VCO frequency equation is fBfREFINVCO/×=
where:
fVCO is the output frequency of the VCO. B is the preset divide
ratio of the binary 13-bit counter (3 to 8191).
fREFIN is the external reference frequency oscillator.
R COUNTER The 14-bit R counter allows the input reference frequency to
be divided down to produce the reference clock to the phase
frequency detector (PFD). Division ratios from 1 to 16,383 are
allowed.
PFD AND CHARGE PUMP The PFD takes inputs from the R counter and N counter (N =
BP + A) and produces an output proportional to the phase and
frequency difference between them. Figure 17 is a simplified
schematic. The PFD includes a programmable delay element
that controls the width of the antibacklash pulse. This pulse
ensures that there is no dead zone in the PFD transfer function
and minimizes phase noise and reference spurs. Two bits in the
R counter latch, ABP2 and ABP1, control the width of the pulse
(see Table 9).
U3
CHARGE
DOWNHIABP2
R DIVIDER
N DIVIDER
CP OUTPUT
CPGNDFigure 17. PFD Simplified Schematic and Timing (In Lock)
MUXOUT AND LOCK DETECT The output multiplexer on the ADF4360 family allows the user
to access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2, and M1 in the function
latch. The full truth table is shown in Table 7. Figure 18 shows
the MUXOUT section in block diagram form.
R COUNTER OUTPUT
N COUNTER OUTPUT
DIGITAL LOCK DETECT
DGNDMUXOUT
DVDD04763-018
Figure 18. MUXOUT Circuit
Lock Detect The correct band is chosen automatically by the band select
logic at power-up or whenever the N counter latch is updated. It
is important that the correct write sequence be followed at
power-up. This sequence is
MUXOUT can be programmed for one type of lock detect.
Digital lock detect is active high. When LDP in the R counter
latch is set to 0, digital lock detect is set high when the phase error
on three consecutive phase detector cycles is less than 15 ns. 1. R counter latch
With LDP set to 1, five consecutive cycles of less than 15 ns
phase error are required to set the lock detect. It stays set high
until a phase error of greater than 25 ns is detected on any
subsequent PD cycle.
2. Control latch
3. N counter latch
During band select, which takes five PFD cycles, the VCO VTUNE
is disconnected from the output of the loop filter and connected
to an internal reference voltage.
INPUT SHIFT REGISTER The ADF4360 family’s digital section includes a 24-bit input
shift register, a 14-bit R counter, and an 18-bit N counter
comprised of a 5-bit A counter and a 13-bit B counter. Data is
clocked into the 24-bit shift register on each rising edge of CLK.
The data is clocked in MSB first. Data is transferred from the
shift register to one of four latches on the rising edge of LE. The
destination latch is determined by the state of the two control
bits (C2, C1) in the shift register. These are the two LSBs, DB1
and DB0, shown in Figure 2.
FREQUENCY (MHz)
TUNE
(VThe truth table for these bits is shown in Table 5. Table 6 shows
a summary of how the latches are programmed. Note that the
test modes latch is used for factory testing and should not be
programmed by the user.
Table 5. C2 and C1 Truth Table Figure 19. Frequency vs. VTUNE, ADF4360-8, L1 and L2 = 270 nH
The R counter output is used as the clock for the band select
logic and should not exceed 1 MHz. A programmable divider is
provided at the R counter input to allow division by 1, 2, 4, or 8
and is controlled by Bits BSC1 and BSC2 in the R counter latch.
Where the required PFD frequency exceeds 1 MHz, the divide
ratio should be set to allow enough time for correct band
selection.
VCO The VCO core in the ADF4360 family uses eight overlapping
bands, as shown in Figure 19, to allow a wide frequency range to
be covered without a large VCO sensitivity (KV) and resultant
poor phase noise and spurious performance.
After band selection, normal PLL action resumes. The value of
KV is determined by the value of inductors used (see the
Choosing the Correct Inductance Value section). The ADF4360
family contains linearization circuitry to minimize any variation
of the product of ICP and KV.
The operating current in the VCO core is programmable in four
steps: 2.5 mA, 5 mA, 7.5 mA, and 10 mA. This is controlled by
Bits PC1 and PC2 in the control latch.
OUTPUT STAGE The RFOUTA and RFOUTB pins of the ADF4360 family are
connected to the collectors of an NPN differential pair driven
by buffered outputs of the VCO, as shown in Figure 20. To allow
the user to optimize the power dissipation versus the output
power requirements, the tail current of the differential pair is
programmable via Bits PL1 and PL2 in the control latch. Four
current levels may be set: 3.5 mA, 5 mA, 7.5 mA, and 11 mA.
These levels give output power levels of −9 dBm, −6 dBm,
−3 dBm, and 0 dBm, respectively, using the correct shunt
inductor to VDD and ac coupling into a 50 Ω load. Alternatively,
both outputs can be combined in a 1 + 1:1 transformer or a 180°
microstrip coupler (see the Output Matching section).
If the outputs are used individually, the optimum output stage
consists of a shunt inductor to VDD.
Another feature of the ADF4360 family is that the supply current
to the RF output stage is shut down until the part achieves lock as
measured by the digital lock detect circuitry. This is enabled by the
Mute-Till-Lock Detect (MTLD) bit in the control latch.
RFOUTARFOUTB04763-020
Figure 20. Output Stage ADF4360-8
