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ADF4360-7BCP
Integrated Synthesizer and VCO
PRELIMINARY TECHNICAL DATA
Integrated Synthesizer and VCO
ADF4360-2 FUNCTIONAL BLOCK DIAGRAM
FEATURES
Output Frequency Range: 1800 MHz to 2150 MHz
Divide-by-2 output
+3.0 V to +3.6V Power Supply
1.8 V Logic Compatibility
Integer-N Synthesizer
Programmable Dual Modulus Prescaler
8/9, 16/17, 32/33
Programmable Output Power Level
3-Wire Serial Interface
Analog and Digital Lock Detect
Hardware and Software Power Down Mode
APPLICATIONS
Wireless Handsets (DECT, GSM, PCS, DCS, WCDMA)
Test Equipment
Wireless LANS
CATV Equipment
GENERAL DESCRIPTIONThe ADF4360-2 is a fully integrated integer-N
synthesizer and voltage controlled oscillator (VCO). The
ADF4360-2 is designed for a center frequency of
2000MHz. In addition, there is a divide-by-2 option
available, whereby the user gets an RF output of between
900MHz and 1075MHz.
Control of all the on-chip registers is via a simple 3-wire
interface. The device operates with a power supply rang-
ing from 3.0V to 3.6V and can be powered down when not
in use.
REFIN
CLK
DATA
AVDDDVDDCE
AGNDDGNDCPGND
RSET
VTUNE
RFOUT AMUXOUT
RFOUT B
VVCO
PRELIMINARY TECHNICAL DATANOTESOperating temperature range is as follows: B Version: –40°C to +85°C.Guaranteed by design. Sample tested to ensure compliance.ICP is internally modified to maintain constant loop gain over the frequency range.
ADF4360 -2 SPECIFICATIONS1(AVDD = DVDD = VVCO = +3.3V ± 10%; AGND = DGND = 0 V;
TA = TMIN to TMAX unless otherwise noted)
PRELIMINARY TECHNICAL DATA
ADF4360 -2 SPECIFICATIONS1(AVDD = DVDD = VVCO = +3.3V ± 10%; AGND = DGND = 0 V;
TA = TMIN to TMAX unless otherwise noted)Spurious Signals due to PFD Frequency
NOTESOperating temperature range is as follows: –40°C to +85°C. All measurements on this page for Core Power = 15mA.The noise of the VCO is meaured in open-loop conditions.The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider
value).The phase noise is measured with the EVAL-ADF4360-xEB1 Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the
REFIN for the synthesizer, f REFIN = 10MHz; Offset frequency = 1 kHz.f REFIN = 10 MHz; fPFD = 200 kHz; N = 10000; Loop B/W = 10kHz.f REFIN = 10 MHz; fPFD = 1 MHz; N = 2000; Loop B/W = 25kHz.The spurious signals are measured with the EVAL-ADF4360-xEB1 Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the
REFIN for the synthesizer (fREFOUT = 10MHz @ 0dBm).
ORDERING GUIDE
PIN CONFIGURATION
TOP VIEW
PRELIMINARY TECHNICAL DATAADF4360-2
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V
readily accumulate on the human body and test equipment and can discharge without
detection. Although the ADF4360 family features proprietary ESD protection circuitry,
permanent damage may occur on devices subjected to high-energy electrostatic
discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
TIMING CHARACTERISTICS
(AVDD = DVDD = VVCO = +3.3V ± 10%; AGND = DGND = 0 V; 1.8V and 3V Logic Levels Used; TA =
TMIN to TMAX unless otherwise noted)Figure 1.Timing Diagram
ABSOLUTE MAXIMUM RATINGS1, 2(TA = +25°C unless otherwise noted)
AVDD to GND3...................................–0.3 V to +3.9 V
AVDD to DVDD ...................................–0.3 V to +0.3 V
VVCO to GND......................................–0.3 V to +3.9 V
VVCO to AVDD ......................................–0.3 V to +0.3 V
Digital I/O Voltage to GND..........–0.3 V to VDD + 0.3 V
Analog I/O Voltage to GND..........–0.3 V to VDD + 0.3 V
REFIN, to GND............................–0.3 V to VDD + 0.3 V
OperatingTemperature Range
Maximum Junction Temperature........................+150°C
CSP θJA Thermal Impedance
(Paddle Soldered).......................................50°C/W
(Paddle Not Soldered).................................88°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec)......................................+215°C
Infrared (15 sec)............................................+220°CStresses above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above
those listed in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.This device is a high-performance RF integrated circuit with an ESD
rating of < 1kV and it is ESD sensitive. Proper precautions should be
taken for handling and assembly.GND = AGND = DGND = 0V
TRANSISTOR COUNT12543 (CMOS) and 700 (Bipolar)
PRELIMINARY TECHNICAL DATA
PIN DESCRIPTION
PRELIMINARY TECHNICAL DATAADF4360-2
TPC 1.Open Loop VCO Phase Noise
TPC 2. VCO Phase Noise, 2000MHz, 200kHz PFD, 10kHz
loop bandwidth.
TPC 4.Close-In Phase Noise at 2000MHz (200kHz Channel
Spacing)ypical Performance Characteristics:
TPC 5.Reference Spurs at 2000MHz (200kHz Channel
Spacing, 10kHz loop bandwidth)
PRELIMINARY TECHNICAL DATA
ADF4360-2Figure 2. Reference Input Stage
A AND B COUNTERSThe A and B CMOS counters combine with the dual modulus
prescaler to allow a wide ranging division ratio in the PLL
feedback counter. The counters are specified to work when
the prescaler output is 300MHz or less. Thus, with an VCO
frequency of 2.5GHz, a prescaler value of 16/17 is valid but a
value of 8/9 is not valid.
Pulse Swallow FunctionThe A and B counters, in conjunction with the dual modulus
prescaler make it possible to generate output frequencies
which are spaced only by the Reference Frequency divided
by R . The equation for the VCO frequency is as follows:
fVCO = [(P x B) + A] x fREFIN/R
fVCOOuput Frequency of voltage controlled oscillator
(VCO).Preset modulus of dual modulus prescaler (8/9, 16/17,
etc.,).Preset Divide Ratio of binary 13-bit counter (3 to
8191).Preset Divide Ratio of binary 5-bit swallow
counter (0 to 31).
fREFINExternal reference frequency oscillator.
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTIONThe Reference Input stage is shown below in Figure 2. SW1
and SW2 are normally-closed switches. SW3 is normally-
open. When Powerdown is initiated, SW3 is closed and SW1
and SW2 are opened. This ensures that there is no loading of
the REFIN pin on powerdown.
PRESCALER (P/P+1)The dual modulus prescaler (P/P+1), along with the A and B
counters, enables the large division ratio, N, to be realised (N
= BP + A). The dual-modulus prescaler, operating at CML
levels, takes the clock from the VCO and divides it down to a
manageable frequency for the CMOS A and B counters. The
prescaler is programmable. It can be set in software to 8/9,
16/17 or 32/33. It is based on a synchronous 4/5 core. There
is a minimum divide ratio possible for fully contiguous output
frequencies. This minimum is determined by P, the prescaler
value and is given by: (P2-P).
Figure 3. A and B Counters
PRELIMINARY TECHNICAL DATA0000–0–01/00 (rev. 0) 00000
PRINTED IN U.S.A.
ADF4360-2
R COUNTERThe 14-bit R counter allows the input reference frequency
to be divided down to produce the reference clock to the
phase frequency detector (PFD). Division ratios from 1 to
16,383 are allowed.
PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMPThe PFD takes inputs from the R counter and N counter
(N=BP+A) and produces an output proportional to the
phase and frequency difference between them. Figure 4 is a
simplified schematic. The PFD includes a programmable
delay element which controls the width of the anti-backlash
pulse. This pulse ensures that there is no deadzone in the
PFD transfer function and minimizes phase noise and
reference spurs. Two bits in the R Counter Latch, ABP2
and ABP1 control the width of the pulse. See Page 14.
Figure 4. PFD Simplified Schematic and Timing (In Lock)
Figure 5. MUXOUT Circuit
INPUT SHIFT REGISTERThe ADF4360 family’s digital section includes a 24-bit
input shift register, a 14-bit R counter and a 18-bit N
counter, comprising a 5-bit A counter and a 13-bit B
counter. Data is clocked into the 24-bit shift register on
each rising edge of CLK. The data is clocked in MSB
first. Data is transferred from the shift register to one of
four latches on the rising edge of LE. The destination
latch is determined by the state of the two control bits
(C2, C1) in the shift register. These are the two lsb's
DB1, DB0 as shown in the timing diagram of Figure 1.
The truth table for these bits is shown in Table 1. Table 2
shows a summary of how the latches are programmed.
Please note that the Test Modes Latch is used for Factory
Testing snd should not be programmed by the user.
Analog Lock Detect
MUXOUT
Digital Lock Detect
R Counter Output
N Counter Output
SDOUT
DVDD
DGND
Table I. C2, C1 Truth Table
MUXOUT AND LOCK DETECTThe output multiplexer on the ADF4360 family allows
the user to access various internal points on the chip. The
state of MUXOUT is controlled by M3, M2 and M1 in
the Function Latch. The full truth table is shown on page
13. Figure 5 shows the MUXOUT section in block
diagram form.
Lock DetectMUXOUT can be programmed for two types of lock
detect: digital lock detect and analog lock detect.
Digital lock detect is active high. When LDP in the R
Counter latch is set to 0, digital lock detect is set high
when the phase error on three consecutive Phase Detector
cycles is less than 15ns.
With LDP set to "1", five consecutive cycles of less than
15ns phase error are required to set the lock detect. It will
stay set high until a phase error of greater than 25ns is
detected on any subsequent PD cycle.
The N-channel open-drain analog lock detect should be
operated with an external pull-up resistor of 10kΩ
nominal. When lock has been detected this output will be
high with narrow low-going pulses.
PRELIMINARY TECHNICAL DATA
ADF4360-2
VCOThe VCO core in the ADF4360 family uses eight overlapping
bands as shown in figure 6 to allow a wide frequency range to
be covered without a large VCO sensitivity (Kv) and resultant
poor phase noise and spurious performance.
The correct band is chosen automatically by the band select
logic at power-up or whenever the N Counter latch is updated.
It is important that the correct write sequence be followed at
power-up. This sequence is:
1) R Counter latch
2) Control latch
3) N Counter latch
During band select, which takes five PFD cycles, The VCO
Vtune is disconnected from the output of the loop filter and
connected to an internal reference voltage.
The operating current in the VCO core is programmable
in four steps, 5mA, 10mA, 15mA & 20mA. This is
controlled by bits PC1 & PC2 in the Control latch.
OUTPUT STAGEThe RFoutA and RFoutB pins of the ADF4360 family are
connected to the collectors of an NPN differential pair
driven by buffered outputs of the VCO as shown in figure
7. To allow the user to optimise his/her power dissipation
vs output power requirements, The tail current of the
differential pair is programmable via bits PL1 & PL2 in
the Control latch. Four current levels may be set; 3.5mA,
5mA, 7.5mA and 11mA giving output power levels of -
13dBm, -10.5dBm, -8dBm & -6dBm using a 50Ohm
resistor to Vdd and ac-coupling into a 50Ohm load.
Alternatively, both outputs can be combined in a 1+1:1
transformer or a 180� microstrip coupler. See Page 19.
If the outputs are to be used individually, then the
optimum output stage consists of a shunt inductor to Vdd.
Another feature of the ADF4360 family is provided
whereby the supply current to the RF output stage is shut
down until the part achieves lock as measured by the
Digital Lock Detect circuitry. This is enabled by the
MTLD (Mute Till Lock Detect) bit in the Control latch.
Figure 6 Frequency vs Vtune, ADF4360-2
After band select, normal PLL action resumes. The
nominal value of Kv is 57MHz/Volt or 28MHZ/Volt if
divide by two operation has been selected (by
programming DIVSEL (DB22), high in the N Counter
latch). The ADF4360 family contains linearisation
circuitry to minimise any variation of the product of Icp
and Kv.
The R Counter output is used as the clock for the band select
logic and should not exceed 1MHz. A programmable divider
is provided at the R Counter input to allow division by 1,2,4
or 8, and is controlled by bits BSC1 and BSC2 in the R
Counter Latch. Where the required PFD frequency exceeds 1
MHz the divide ratio should be set to allow enough time for
correct band selection.
Figure 7 RF Output Stage ADF4360-2
PRELIMINARY TECHNICAL DATA0000–0–01/00 (rev. 0) 00000
PRINTED IN U.S.A.
ADF4360-2
TABLE II: LATCH STRUCTUREThe diagram below shows the three on-chip latches for the ADF4360 family. The two LSB’s decide which latch is
programmed.
