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ADF4360-6-ADF4360-6BCP-ADF4360-6BCPZ
Integrated Integer-N Synthesizer and VCO
Integrated Synthesizer and VCORev. 0
FEATURES
Output frequency range: 1050 MHz to 1250 MHz
Divide-by-2 output
3.0 V to 3.6 V power supply
1.8 V logic compatibility
Integer-N synthesizer
Programmable dual-modulus prescaler 8/9, 16/17, 32/33
Programmable output power level
3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode
APPLICATIONS
Wireless handsets (DECT, GSM, PCS, DCS, WCDMA)
Test equipment
Wireless LANs
CATV equipment
GENERAL DESCRIPTION The ADF4360-6 is a fully integrated integer-N synthesizer and
voltage controlled oscillator (VCO). The ADF4360-6 is designed
for a center frequency of 1150 MHz. In addition, a divide-by-2
option is available, whereby the user receives an RF output of
between 525 MHz and 625 MHz.
Control of all the on-chip registers is through a simple 3-wire
interface. The device operates with a power supply ranging from
3.0 V to 3.6 V and can be powered down when not in use.
FUNCTIONAL BLOCK DIAGRAM
MUXOUT
VVCO
REFIN
CLK
DATA
AVDDDVDDCE
AGNDDGNDCPGND
RSET
VTUNE
RFOUTA
RFOUTBFigure 1.
TABLE OF CONTENTS Specifications.....................................................................................3
Timing Characteristics.....................................................................5
Absolute Maximum Ratings............................................................6
Transistor Count...........................................................................6
ESD Caution..................................................................................6
Pin Configuration and Functional Descriptions..........................7
Typical Performance Characteristics.............................................8
Circuit Description...........................................................................9
Reference Input Section...............................................................9
Prescaler (P/P + 1)........................................................................9
A and B Counters.........................................................................9
R Counter......................................................................................9
PFD and Charge Pump................................................................9
MUXOUT and Lock Detect......................................................10
Input Shift Register.....................................................................10
VCO.............................................................................................10
Output Stage................................................................................11
Latch Structure...........................................................................12
Control Latch..............................................................................16
N Counter Latch.........................................................................17
R Counter Latch.........................................................................17
Applications.....................................................................................18
Direct Conversion Modulator..................................................18
Fixed Frequency LO...................................................................19
Power-Up.....................................................................................19
Interfacing...................................................................................19
PCB Design Guidelines for Chip Scale Package...........................20
Output Matching........................................................................20
Outline Dimensions.......................................................................21
Ordering Guide..........................................................................21
REVISION HISTORY Revision 0: Initial Version
SPECIFICATIONS1
Table 1. AVDD = DVDD = VVCO = 3.3 V ± 10%; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted Operating temperature range is –40°C to +85°C.
2 Guaranteed by design. Sample tested to ensure compliance. ICP is internally modified to maintain constant loop gain over the frequency range.
4 TA = 25°C; AVDD = DVDD = VVCO = 3.3 V; P = 32. These characteristics are guaranteed for VCO core power = 10 mA.
6 Jumping from 1.0 GHz to 1.25 GHz. PFD frequency = 200 kHz; loop bandwidth = 10 kHz. Using 50 Ω resistors to VVCO, into a 50 Ω load. For tuned loads, see section. Output Matching
8 The noise of the VCO is measured in open-loop conditions. The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider value).
10 The phase noise is measured with the EVAL-ADF4360-xEB1 Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for the
synthesizer; offset frequency = 1 kHz.
11 fREFIN = 10 MHz; fPFD = 200 kHz; N = 5000; Loop B/W = 10 kHz. fREFIN = 10 MHz; fPFD = 1 MHz; N = 1000; Loop B/W = 25 kHz.
13 The spurious signals are measured with the EVAL-ADF4360-xEB1 Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for
the synthesizer; fREFOUT = 10 MHz @ 0 dBm.
TIMING CHARACTERISTICS
Table 2. AVDD = DVDD = VVCO = 3.3 V ± 10%; AGND = DGND = 0 V; 1.8 V and 3 V logic levels used; TA = TMIN to TMAX, unless
otherwise noted
CLOCK
DATAt3t5Figure 2. Timing Diagram
ABSOLUTE MAXIMUM RATINGS
Table 3. TA = 25°C, unless otherwise noted *GND = AGND = DGND = 0 V.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rat-
ing only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may affect device
reliability.
This device is a high performance RF integrated circuit with an
ESD rating of <1 kV and it is ESD sensitive. Proper precautions
should be taken for handling and assembly.
TRANSISTOR COUNT 12543 (CMOS) and 700 (Bipolar)
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS
ADF4360-6
TOP VIEW
(Not to Scale)
CPGND
AVDD
AGND
RFOUTA
RFOUTB
VVCO
DATA
CLK
REFIN
DGND
RSET
TUNE
AGND
AGND
AGND
AGND
AGNDPIN 1
IDENTIFIER
Figure 3. Pin Configuration
Table 4. Pin Functional Descriptions TYPICAL PERFORMANCE CHARACTERISTICS
–1010M1M100k10k
FREQUENCY OFFSET (Hz)
OUTPUT POWER (dB)Figure 4. Open-Loop VCO Phase Noise
–150
–7010010M1M100k10k
FREQUENCY OFFSET (Hz)
OUTP
UT P
R (dB)Figure 5. VCO Phase Noise, 1150 MHz, 200 kHz PFD, 10 kHz Loop Bandwidth
–150
–7010010M1M100k10k
FREQUENCY OFFSET (Hz)
OUTP
UT P
R (dB)Figure 6. VCO Phase Noise, 575 MHz,
Divide-by-2 Enabled 200 kHz PFD, 10 kHz Loop Bandwidth
OUTP
UT P
R (dB)
–2kHz–1kHz1150MHz1kHz2kHz
Figure 7. Close-In Phase Noise at 1150 MHz (200 kHz Channel Spacing)
OUTP
UT P
R (dB)
–200kHz–100kHz1150MHz100kHz200kHz
Figure 8. Reference Spurs at 1150 MHz
(200 kHz Channel Spacing, 10 kHz Loop Bandwidth)
OUTP
UT P
R (dB)
–1MHz–0.5MHz1150MHz0.5MHz1MHz
Figure 9. Reference Spurs at 1150 MHz
(1 MHz Channel Spacing, 25 kHz Loop Bandwidth)
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION The reference input stage is shown in Figure 10. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed, and SW1 and SW2 are
opened. This ensures that there is no loading of the REFIN pin
on power-down.
TO R COUNTERREFIN
100kΩ
SW1
POWER-DOWN
CONTROL
Figure 10. Reference Input Stage
PRESCALER (P/P + 1) The dual-modulus prescaler (P/P + 1), along with the A and B
counters, enables the large division ratio, N, to be realized (N =
BP + A). The dual-modulus prescaler, operating at CML levels,
takes the clock from the VCO and divides it down to a manage-
able frequency for the CMOS A and B counters. The prescaler is
programmable. It can be set in software to 8/9, 16/17, or 32/33
and is based on a synchronous 4/5 core. There is a minimum
divide ratio possible for fully contiguous output frequencies;
this minimum is determined by P, the prescaler value, and is
given by (P2 − P).
A AND B COUNTERS The A and B CMOS counters combine with the dual-modulus
prescaler to allow a wide range division ratio in the PLL feed-
back counter. The counters are specified to work when the pre-
scaler output is 300 MHz or less. Thus, with a VCO frequency of
2.5 GHz, a prescaler value of 16/17 is valid, but a value of 8/9 is
not valid.
Pulse Swallow Function The A and B counters, in conjunction with the dual-modulus
prescaler, make it possible to generate output frequencies that
are spaced only by the reference frequency divided by R. The
VCO frequency equation is RfABPfREFINVCO/×]+×[=
where:
fVCO is the output frequency of the VCO.
P is the preset modulus of the dual-modulus prescaler (8/9,
16/17, and so on).
B is the preset divide ratio of the binary 13-bit counter (3 to 8191).
A is the preset divide ratio of the binary 5-bit swallow counter (0 to 31).
TO PFD
FROM VCO Figure 11. A and B Counters
R COUNTER The 14-bit R counter allows the input reference frequency to
be divided down to produce the reference clock to the phase
frequency detector (PFD). Division ratios from 1 to 16,383 are
allowed.
PFD AND CHARGE PUMP The PFD takes inputs from the R counter and N counter (N =
BP + A) and produces an output proportional to the phase and
frequency difference between them. Figure 12 is a simplified
schematic. The PFD includes a programmable delay element
that controls the width of the antibacklash pulse. This pulse
ensures that there is no dead zone in the PFD transfer function
and minimizes phase noise and reference spurs. Two bits in the
R counter latch, ABP2 and ABP1, control the width of the pulse
(see Table 9).
U3
CHARGE
DOWNHIABP2
R DIVIDER
N DIVIDER
CPGNDMUXOUT AND LOCK DETECT The output multiplexer on the ADF4360 family allows the user
to access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2, and M1 in the function
latch. The full truth table is shown in Table 7. Figure 13 shows
the MUXOUT section in block diagram form.
Lock Detect MUXOUT can be programmed for two types of lock detect:
digital and analog. Digital lock detect is active high. When LDP
in the R counter latch is set to 0, digital lock detect is set high
when the phase error on three consecutive phase detector cycles
is less than 15 ns.
With LDP set to 1, five consecutive cycles of less than 15 ns
phase error are required to set the lock detect. It stays set high
until a phase error of greater than 25 ns is detected on any sub-
sequent PD cycle.
The N-channel open-drain analog lock detect should be oper-
ated with an external pull-up resistor of 10 kΩ nominal. When a
lock has been detected, this output is high with narrow low-
going pulses.
R COUNTER OUTPUT
N COUNTER OUTPUT
DIGITAL LOCK DETECT
DGNDMUXOUT
DVDD
ANALOG LOCK DETECT
SDOUT04414-0-013
Figure 13. MUXOUT Circuit
INPUT SHIFT REGISTER The ADF4360 family’s digital section includes a 24-bit input
shift register, a 14-bit R counter, and an 18-bit N counter
comprised of a 5-bit A counter and a 13-bit B counter. Data is
clocked into the 24-bit shift register on each rising edge of CLK.
The data is clocked in MSB first. Data is transferred from the
shift register to one of four latches on the rising edge of LE. The
destination latch is determined by the state of the two control
bits (C2, C1) in the shift register. These are the two LSBs—DB1,
DB0—as shown in Figure 2.
The truth table for these bits is shown in Table 5. Table 6 shows
a summary of how the latches are programmed. Note that the
test modes latch is used for factory testing and should not be
programmed by the user.
Table 5. C2 and C1 Truth Table
VCO The VCO core in the ADF4360 family uses eight overlapping
bands, as shown in Figure 14, to allow a wide frequency range to
be covered without a large VCO sensitivity (KV) and resultant
poor phase noise and spurious performance.
The correct band is chosen automatically by the band select
logic at power-up or whenever the N counter latch is updated. It
is important that the correct write sequence be followed at
power-up. This sequence is
1. R counter latch
2. Control latch
3. N counter latch
During band select, which takes five PFD cycles, the VCO VTUNE
is disconnected from the output of the loop filter and connected
to an internal reference voltage.
FREQUENCY (MHz)
VOLTAGE (V)Figure 14. Frequency vs. VTUNE, ADF4360-6
The R counter output is used as the clock for the band select logic
and should not exceed 1 MHz. A programmable divider is provided
at the R counter input to allow division by 1, 2, 4, or 8 and is con-
trolled by Bits BSC1 and BSC2 in the R counter latch. Where the
required PFD frequency exceeds 1 MHz, the divide ratio should be
set to allow enough time for correct band selection.
After band selection, normal PLL action resumes. The nominal
value of KV is 32 MHz/V, or 16 MHz/V if divide-by-2 operation has
been selected (by programming DIV2 (DB22) high in the N
counter latch). The ADF4360 family contains linearization circuitry
to minimize any variation of the product of ICP and KV.
If the outputs are used individually, the optimum output stage
consists of a shunt inductor to VDD.
Another feature of the ADF4360 family is that the supply current
to the RF output stage is shut down until the part achieves lock as
measured by the digital lock detect circuitry. This is enabled by the
Mute-Till-Lock Detect (MTLD) bit in the control latch. The operating current in the VCO core is programmable in four
steps: 5 mA, 10 mA, 15 mA, and 20 mA. This is controlled by
Bits PC1 and PC2 in the control latch.
RFOUTARFOUTB04414-0-015
OUTPUT STAGE The RFOUTA and RFOUTB pins of the ADF4360 family are con-
nected to the collectors of an NPN differential pair driven by
buffered outputs of the VCO, as shown in Figure 15. To allow
the user to optimize the power dissipation versus the output
power requirements, the tail current of the differential pair is
programmable via Bits PL1 and PL2 in the control latch. Four
current levels may be set: 3.5 mA, 5 mA, 7.5 mA, and 11 mA.
These levels give output power levels of −13.5 dBm, −10.5 dBm,
−7.5 dBm, and −4.5 dBm, respectively, using a 50 Ω resistor to
VDD and ac coupling into a 50 Ω load. Alternatively, both out-
puts can be combined in a 1 + 1:1 transformer or a 180° micro-
strip coupler (see the Output Matching section).
Figure 15. Output Stage ADF4360-6
LATCH STRUCTURE Table 6 shows the three on-chip latches for the ADF4360 family. The two LSBs decide which latch is programmed.
Table 6. Latch Structure
CONTROL LATCH
N COUNTER LATCH
R COUNTER LATCH
