ADF4252BCP Fast Delivery |IC PHOENIX CO.,LIMITED

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ADF4252BCP
Lowest Phase Noise PLL Synthesizer using Fractional-N Technology
REV.B
Dual Fractional-N/Integer-N
Frequency Synthesizer
FEATURES
3.0 GHz Fractional-N/1.2GHz Integer-N
2.7 Vto 3.3V Power Supply
Separate VP Allows Extended Tuning Voltage to 5V
Programmable Dual Modulus Prescaler
RF: 4/5, 8/9
IF: 8/9, 16/17, 32/33, 64/65
Programmable Charge Pump Currents
3-Wire Serial Interface
Digital Lock Detect
Power-Down Mode
Programmable Modulus on Fractional-N Synthesizer
Trade-Off Noise versus Spurious Performance
APPLICATIONS
Base Stations for Mobile Radio (GSM, PCS, DCS,
CDMA, WCDMA)
Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA)
Wireless LANs
Communications Test Equipment
CATV Equipment
FUNCTIONAL BLOCK DIAGRAM
REFIN
REFOUT
VDD1VDD2VDD3DVDDVP1VP2RSET
CLK
DATA
RFINA
RFINB
CPRF
CPIF
MUXOUT
AGND1AGND2DGNDCPGND1CPGND2
IFINB
IFINA
GENERAL DESCRIPTION
The ADF4252 is a dual fractional-N/integer-N frequency
synthesizer that can be used to implement local oscillators
(LO) inthe upconversion and downconversion sections of
wireless receivers and transmitters. Both the RF and IF syn-
thesizers consist of a low noise digital PFD (phase frequency
detector), a precision charge pump, and a programmable refer-
ence divider. The RF synthesizer has a �-�-based fractional
interpolator that allows programmable fractional-N division.
The IF synthesizer has programmable integer-N counters. A
complete PLL (phase-locked loop) can be implemented if the
synthesizer is used with an external loop filter and VCO (volt-
age controlled oscillator).
Control of all the on-chip registers is via a simple 3-wire inter-
face. The devices operate with a power supply ranging from
2.7Vto 3.3V and can be powered down when not in use.
ADF4252–SPECIFICATIONS1(VDD1 = VDD2 = VDD3 = DVDD = 3V� 10%, DVDD < VP1, VP2 < 5.5 V, GND= 0V,
RSET = 2.7k�, dBm referred to 50�, TA = TMIN to TMAX, unless otherwise noted.)
CHARGE PUMP
LOGIC INPUTS
RF NOISE AND SPURIOUS CHARACTERISTICS
NOTES
ADF4252
TIMING CHARACTERISTICS*
*Guaranteed by design, but not production tested.
(VDD1 = VDD2 = VDD3 = DVDD =3 V � 10%, DVDD < VP1, VP2 < 5.5 V, GND = 0 V,
unless otherwise noted.)
Figure 1.Timing Diagram
ADF4252
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADF4252 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
ORDERING GUIDE
*CP = Chip Scale Package
PIN CONFIGURATION
PIN 1
INDICATOR
TOP VIEW(Not to Scale)
18 CPGND2
17 DVDD
16 IFINA
15 IFINB
CPRF 1
CPGND1 2
RFINA 3
24
14 AGND2
13 RSET
REF
7
REF
OUT
8
GND
9
CLK 10
11
LE 1
RFINB 4
AGND1 5
MUXOUT 6
23
22
21
20
19 CP
ADF4252
ABSOLUTE MAXIMUM RATINGS1, 2
(TA = 25°C, unless otherwise noted.)
VDD1, VDD2, VDD3, DVDD to GND3 . . . . . . . . –0.3 V to +4 V
REFIN, RFINA, RFINB to GND . . . . . . –0.3 V to VDD + 0.3 V
VP1, VP2 to GND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.8 V
VP1, VP2 to VDD1 . . . . . . . . . . . . . . . . . . . . . –3.3 V to +3.5 V
Digital I/O Voltage to GND . . . . . . . . –0.3 V to VDD + 0.3 V
Analog I/O Voltage to GND . . . . . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150°C
CSP �JA Thermal Impedance . . . . . . . . . . . . . . . . . . . 122°C/W
Soldering Reflow Temperature
Vapor Phase (60 sec max) . . . . . . . . . . . . . . . . . . . . . 240°C
IR Reflow (20 sec max) . . . . . . . . . . . . . . . . . . . . . . . 240°C
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2This device is a high performance RF integrated circuit with an ESD rating
of <2kΩ, and it is ESD sensitive. Proper precautions should be taken for handling
and assembly.
3GND = CPGND1, AGND1, DGND, AGND2, and CPGND2.
PIN FUNCTION DESCRIPTIONS
CPGND1
RFINA
RFINBComplementary Input to the RF Prescaler.
REFOUT
DGND
CLK
DATA
RSET
AGND2Ground for the IF Synthesizer.
IFINA
DVDD
CPGND2IF Charge Pump Ground.
CPIF
VP2IF Charge Pump Power Supply. Decoupling capacitors to the ground plane should be placed as close as possible
VDD3
VDD1
VP1
ADF4252
REFIN
REFOUT
VDD1VDD2VDD3DVDDVP1VP2RSET
CLK
DATA
RFINA
RFINB
CPRF
CPIF
MUXOUT
AGND1AGND2DGNDCPGND1CPGND2
IFINB
IFINA
Figure 2.Detailed Functional Block Diagram
TPC plots 1 to 12 attained using EVAL-ADF4252EB1;
measurements from HP8562E spectrum analyzer.
TPC 1.Phase Noise Plot, Lowest Noise Mode,
1.7518 GHz RFOUT, 10 MHz PFD Frequency,
200kHz Channel Step Resolution
TPC 2.Phase Noise Plot, Low Noise and Spur
Mode, 1.7518 GHz RFOUT, 10 MHz PFD Frequency,
200kHz Channel Step Resolution
TPC 4.Spurious Plot, Lowest Noise Mode,
1.7518GHz RFOUT, 10 MHz PFD Frequency,
200kHz Channel Step Resolution
TPC 5.Spurious Plot, Low Noise and Spur Mode,
1.7518GHz RFOUT, 10 MHz PFD Frequency,
200kHz Channel Step Resolution
ADF4252
TPC 7.Phase Noise Plot, Lowest Noise Mode,
1.7518 GHz RFOUT, 20 MHz PFD Frequency,
200kHz Channel Step Resolution
TPC 8.Phase Noise Plot, Low Noise and Spur
Mode, 1.7518 GHz RFOUT, 20 MHz PFD Frequency,
200kHz Channel Step Resolution
TPC 9.Phase Noise Plot, Lowest Spur Mode,
TPC 10.Spurious Plot, Lowest Noise Mode,
1.7518GHz RFOUT, 20 MHz PFD Frequency,
200kHz Channel Step Resolution
TPC 11.Spurious Plot, Low Noise and Spur Mode,
1.7518GHz RFOUT, 20 MHz PFD Frequency, 200kHz
Channel Step Resolution
TPC 12.Spurious Plot, Lowest Spur Mode,
TPC 13. In-Band Phase Noise vs. Frequency*
TPC 14. 100 kHz Spur vs. Frequency*
TPC 15. 200 kHz Spur vs. Frequency*
TPC 16. 400 kHz Spur vs. Frequency*
TPC 17. 600 kHz Spur vs. Frequency*
TPC 18. 3 MHz Spur vs. Frequency*
ADF4252
TPC 19.RF Input Sensitivity
TPC 20.IF Input Sensitivity
TPC 21.Phase Noise (Referred to CP Output) vs.
PFD Frequency, RF Side
TPC 22.Phase Noise (Referred to CP Output) vs.
PFD Frequency, IF Side
TPC 23.RF Charge Pump Output Characteristics
TPC 24.IF Charge Pump Output Characteristics
CIRCUIT DESCRIPTION
Reference Input Section
The reference input stage is shown in Figure 3. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REFIN pin
on power-down.
Figure 3.Reference Input Stage
RF and IF Input Stage
The RF input stage is shown in Figure 4. The IF input stage is
the same. It is followed by a two-stage limiting amplifier to
generate the CML clock levels needed for the N counter.
Figure 4.RF Input Stage
RF INT Divider
The RF INT CMOS counter allows a division ratio in the PLL
feedback counter. Division ratios from 31 to 255 are allowed.
INT, FRAC, MOD, and R Relationship
The INT, FRAC, and MOD values, in conjunction with the
RF R counter, make it possible to generate output frequencies
that are spaced by fractions of the RF phase frequency detector
(PFD). The equation for the RF VCO frequency (RFOUT) is(1)
where RFOUT is the output frequency of external voltage controlled
oscillator (VCO).(2)
REFIN = the reference input frequency, D= RF REFIN doubler
bit, R= the preset divide ratio of the binary 4-bit program-
mable reference counter (1 to 15), INT= the preset divide ratio of
the binary 8-bit counter (31 to 255), MOD= the preset modulus
ratio of binary 12-bit programmable FRAC counter (2 to 4095),
and FRAC= the preset fractional ratio of the binary 12-bit
programmable FRAC counter (0 to MOD).
Figure 5.N Counter
RF R Counter
The 4-bit RF R counter allows the input reference frequency
(REFIN) to be divided down to produce the reference clock to
the RF PFD. Division ratios from 1 to 15 are allowed.
IF R Counter
The 15-bit IF R counter allows the input reference frequency
(REFIN) to be divided down to produce the reference clock to
the IF PFD. Division ratios from 1 to 32767 are allowed.
IF Prescaler (P/P+ 1)
The dual modulus IF prescaler (P/P+ 1), along with the IF A
and B counters, enables the large division ratio, N, to be realized= PB+ A). Operating at CML levels, it takes the clock from
the IF input stage and divides it down to a manageable frequency
for the CMOS IF A and B counters.
IF A and B Counters
The IF A and B CMOS counters combine with the dual modulus
IF prescaler to allow a wide ranging division ratio in the PLL
feedback counter. The counters are guaranteed to work when the
prescaler output is 150MHz or less.
Pulse Swallow Function
The IF A and B counters, in conjunction with the dual modulus
IF prescaler, make it possible to generate output frequencies
that are spaced only by the reference frequency divided by R.
See Device Programming after Initial Power-Up section for
examples. The equation for the IF VCO (IFOUT) frequency is(3)
where IFOUT = the output frequency of the external voltage controlled
oscillator (VCO), P = the preset modulus of IF dual modulus
prescaler, B= the preset divide ratio of the binary 12-bit counter
(3 to 4095), and A= the preset divide ratio of the binary 6-bit
ADF4252
Phase Frequency Detector (PFD) and Charge Pump
The PFD takes inputs from the R counter and N counter and
produces an output proportional to the phase and frequency
difference between them. Figure 6 is a simplified schematic. The
antibacklash pulse. This pulse ensures that there is no dead zone
in the PFD transfer function and minimizes phase noise and
reference spurs.
+INDELAY
ELEMENTUPDOWN
CHARGE
PUMP
–IN
Figure 6.PFD Simplified Schematic
MUXOUT and Lock Detect
The output multiplexer on the ADF4252 allows the user to
access various internal points on the chip. The state of MUXOUT
is controlled by M4, M3, M2, and M1 in the master register.
Table I shows the full truth table. Figure 7 shows the MUXOUT
section in block diagram format.
IF/RF ANALOG LOCK DETECT
Figure 7.MUXOUT Circuit
Lock Detect
MUXOUT can be programmed for two types of lock detect: digital
and analog. Digital is active high. The N-channel open-drain
analog lock detect should be operated with an external pull-up
resistor of 10kΩ nominal. When lock has been detected, this
output will be high with narrow low going pulses.
Input Shift Register
Data is clocked in on each rising edge of CLK. The data is
clocked in MSB first. Data is transferred from the input register
to one of seven latches on the rising edge of LE. The destination
latch is determined by the state of the three control bits (C2, C1,
and C0) in the shift register. These are the three LSBs: DB2,
DB1, and DB0, as shown in Figure 1. The truth table for these
bits is shown in Table I. Table II summarizes how the registers
are programmed.
Table I.Control Bit Truth Table
Table II.Register Summary
ADF4252
Table III.RF N Divider Register Map

Partno	Mfg	Dc	Qty	Available	Descript
ADF4252BCP	ADI	N/a	2	avai	Lowest Phase Noise PLL Synthesizer using Fractional-N Technology