ADF4212BRU Fast Delivery |IC PHOENIX CO.,LIMITED

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ADF4212BRU
Dual, Integer-N 0.5 GHz/3.0 GHz PLL
REV.A
Dual RF/IF PLL Frequency Synthesizers
FUNCTIONAL BLOCK DIAGRAM
CLOCK
DATA
MUXOUT
CPRF
CPIF
REFIN
RFIN
VDD1VDD2VP1VP2
AGNDRFDGNDRFDGNDIFAGNDIF
DGNDIF
IFINFLO
RSET
FEATURES
ADF4210: 550 MHz/1.2 GHz
ADF4211: 550 MHz/2.0 GHz
ADF4212: 1.0 GHz/2.7 GHz
ADF4213: 1.0 GHz/3 GHz
2.7 V to 5.5 V Power Supply
Separate Charge Pump Supply (VP) Allows Extended
Tuning Voltage in 3 V Systems
Programmable Dual Modulus Prescaler
RF and IF: 8/9, 16/17, 32/33, 64/65
Programmable Charge Pump Currents
3-Wire Serial Interface
Analog and Digital Lock Detect
Fastlock Mode
Power-Down Mode
APPLICATIONS
Base Stations for Wireless Radio (GSM, PCS, DCS,
CDMA, WCDMA)
Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA)
Wireless LANS
Communications Test Equipment
CATV Equipment
GENERAL DESCRIPTION
The ADF4210/ADF4211/ADF4212/ADF4213 is a dual frequency
synthesizer that can be used to implement local oscillators (LO)
in the upconversion and downconversion sections of wireless
receivers and transmitters. They can provide the LO for both
the RF and IF sections. They consist of a low-noise digital PFD
(Phase Frequency Detector), a precision charge pump, a pro-
grammable reference divider, programmable A and B Counters
and a dual-modulus prescaler (P/P + 1). The A (6-bit) and B
(12-bit) counters, in conjunction with the dual modulus prescaler
(P/P + 1), implement an N divider (N = BP + A). In addition,
the 14-bit reference counter (R Counter), allows selectable
REFIN frequencies at the PFD input. A complete PLL (Phase-
Locked Loop) can be implemented if the synthesizer is used with
an external loop ﬁlter and VCO (Voltage Controlled Oscillators).
Control of all the on-chip registers is via a simple 3-wire interface.
The devices operate with a power supply ranging from 2.7 V to
5 V and can be powered down when not in use.
ADF4210/ADF4211/ADF4212/ADF4213–SPECIFICATIONS1
(VDD1 = VDD2 = 3 V � 10%, 5 V � 10%; VDD1, VDD2 ≤ VP1, VP2 ≤ 6.0 V ; AGNDRF = DGNDRF = AGNDIF = DGNDIF = 0 V; RSET = 2.7 k� dBm to 50 �;
TA = TMIN to TMAX unless otherwise noted.)
ADF4210/ADF4211/ADF4212/ADF4213
NOTES
1Operating temperature range is as follows: B Version: –40°C to +85°C.The B Chip speciﬁcations are given as typical values.
3This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the IF/RF input is divided down to a frequency that is
less than this value.
4VDD1 = VDD2 = 3 V; For VDD1 = VDD2 = 5 V, use CMOS-compatible levels, TA = 25°C.Guaranteed by design. Sample tested to ensure compliance.
6VDD = 3 V; P = 16; RFIN = 900 MHz; IFIN = 540 MHz, TA = 25°C.The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 logN (where N is the N divider value). See
TPC 16.The phase noise is measured with the EVAL-ADF4210/ADF4212/ADF4213EB Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the
REFIN for the synthesizer (fREFOUT = 10 MHz @ 0 dBm).fREFIN = 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; fIF = 540 MHz; N = 2700; Loop B/W = 20 kHz.
10fREFIN = 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; fRF = 900 MHz; N = 4500; Loop B/W = 20 kHz.Same conditions as listed in Note 10.
12fREFIN = 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; fRF = 1750 MHz; N = 8750; Loop B/W = 20 kHz.fREFIN = 10 MHz; fPFD = 10 kHz; Offset frequency = 200 Hz; fRF = 1750 MHz; N = 175000; Loop B/W = 1 kHz.
14fREFIN = 10 MHz; fPFD = 1 MHz; Offset frequency = 1 kHz; fRF = 1960 MHz; N = 9800; Loop B/W = 20 kHz.
Speciﬁcations subject to change without notice.
ADF4210/ADF4211/ADF4212/ADF4213
Figure 1.Timing Diagram
TIMING CHARACTERISTICS
NOTES
Guaranteed by design but not production tested.
Speciﬁcations subject to change without notice.
(VDD1 = VDD2 = 3 V � 10%, 5 V � 10%; VDD1, VDD2 ≤ VP1, VP2 ≤ 6 V � 10%; AGNDRF = DGNDRF
= AGNDIF = DGNDIF = 0 V; TA = TMIN to TMAX unless otherwise noted.)
ABSOLUTE MAXIMUM RATINGS1, 2
(TA = 25°C unless otherwise noted)
VDD1 to GND3 . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
VDD1 to VDD2 . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
VP1, VP2 to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
VP1, VP2 to VDD1 . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.5 V
Digital I/O Voltage to GND . . . . . . –0.3 V to DVDD + 0.3 V
Analog I/O Voltage to GND . . . . . . . . . –0.3 V to VP + 0.3 V
REFIN, RFINA, RFINB,
IFINA, IFINB to GND . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . .–40°C to +85°C
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C
TSSOP θJA Thermal Impedance . . . . . . . . . . . . . 150.4°C/W
CSP θJA (Paddle Soldered) . . . . . . . . . . . . . . . . . . . 122°C/W
CSP θJA (Paddle Not Soldered) . . . . . . . . . . . . . . . . 216°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this speciﬁcation is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.This device is a high-performance RF integrated circuit with an ESD rating of
< 2 kV and it is ESD sensitive. Proper precautions should be taken for handling
and assembly.GND = AGND = DGND = 0 V.
TRANSISTOR COUNT
11749 (CMOS) and 522 (Bipolar).
ORDERING GUIDE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADF4210/ADF4211/ADF4212/ADF4213 features proprietary ESD protection circuitry, per-
manent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore,
proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
PIN FUNCTION DESCRIPTIONS
PIN CONFIGURATIONS
TSSOP
CP-20
AGNDRF
FLO
CPRF
RFIN
DGNDRF
DGNDIF
IFIN
RSET
AGNDIF
TOP VIEW
(Not to Scale)
ADF4210/
ADF4211/
ADF4212/
ADF4213
ADF4210/ADF4211/ADF4212/ADF4213
–Typical Performance Characteristics

TPC 1.S-Parameter Data for the ADF4213 RF Input
(Up to 3.0 GHz)

TPC 2.ADF4213 Phase Noise (900 MHz, 200 kHz, 20 kHz)
10dB/DIVISIONRL = –40dBc/HzRMS NOISE = 0.6522�
100Hz
FREQUENCY OFFSET FROM 900MHz CARRIER
1MHz
PHASE NOISE
dBc/Hz
1kHz10kHz100kHz
TPC 3.ADF4213 Integrated Phase Noise (900 MHz,
200 kHz, 35 kHz, Typical Lock Time: 200 µs)

TPC 4.Input Sensitivity (ADF4213)

10dB/DIVISIONRL = –40dBc/HzRMS NOISE = 0.5421�
100Hz
FREQUENCY OFFSET FROM 900MHz CARRIER
1MHz
PHASE NOISE
dBc/Hz
1kHz10kHz100kHz
TPC 5.ADF4213 Integrated Phase Noise (900 MHz, 200 kHz,
20 kHz, Typical Lock Time: 400 µs)

TPC 6.ADF4213 Reference Spurs (900 MHz, 200 kHz, 20 kHz)

TPC 7.ADF4213 Reference Spurs (900 MHz,
200 kHz, 35 kHz)
10dB/DIVISIONRL = –40dBc/HzRMS NOISE = 1.6�
100HzFREQUENCY OFFSET FROM 1750MHz CARRIER1MHz
PHASE NOISE
dBc/Hz
–140
TPC 8.ADF4213 Integrated Phase Noise (1750 MHz,
30 kHz, 3 kHz)

TPC 9.ADF4213 Phase Noise (2800 MHz, 1 MHz, 100 kHz)

TPC 10.ADF4213 Phase Noise (1750 MHz, 30 kHz, 3 kHz)

TPC 11.ADF4213 Reference Spurs (1750 MHz,
30 kHz, 3 kHz)

10dB/DIVISIONRL = –40dBc/HzRMS NOISE = 1.7�
100HzFREQUENCY OFFSET FROM 3100MHz CARRIER1MHz
PHASE NOISE
dBc/Hz
–140
TPC 12.ADF4213 Integrated Phase Noise (2800 MHz,
1 MHz, 100 kHz)
ADF4210/ADF4211/ADF4212/ADF4213
TPC 13.ADF4213 Reference Spurs (2800 MHz, 1 MHz,
100 kHz)
TEMPERATURE – �C
PHASE NOISE
dBc/Hz
–20
TPC 14.ADF4213 Phase Noise vs. Temperature (900 MHz,
200 kHz, 20 kHz)
TUNING VOLTAGE – Volts0234–105
FIRST REFERENCE SPUR
dBc
–25
TPC 15.ADF4213 Reference Spurs (200 kHz) vs. V TUNE
(900 MHz, 200 kHz, 20 kHz)
TPC 16.ADF4213 Phase Noise (Referred to CP Output)
vs. PFD Frequency
TEMPERATURE – �C
FIRST REFERENCE SPUR
dBc–70
–20
TPC 17.ADF4213 Reference Spurs vs. Temperature
(900 MHz, 200 kHz, 20 kHz)
TEMPERATURE – �C
PHASE NOISE
dBc/Hz
–20
TPC 18.ADF4213 Phase Noise vs. Temperature
(836 MHz, 30 kHz, 3 kHz)
TEMPERATURE – �C
FIRST REFERENCE SPUR
dBc–70
–20
TPC 19.ADF4213 Reference Spurs vs. Temperature
(836 MHz, 30 kHz, 3 kHz)
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
The reference input stage is shown below in Figure 2. SW1 and
SW2 are normally-closed switches. SW3 is normally-open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REFIN pin
on power-down.
Figure 2.Reference Input Stage
RF/IF INPUT STAGE
The RF/IF input stage is shown in Figure 3. It is followed by a
2-stage limiting ampliﬁer to generate the CML (Current Mode
Logic) clock levels needed for the prescaler.
Figure 3.RF/IF Input Stage
PRESCALER (P/P + 1)
The dual modulus prescaler (P/P + 1), along with the A and
B counters, enables the large division ratio, N, to be realized
(N = PB + A). The dual-modulus prescaler, operating at CML
levels, takes the clock from the RF/IF input stage and divides
it down to a manageable frequency for the CMOS A and B
counters in the RF and If sections. The prescaler in both
sections is programmable. It can be set in software to 8/9, 16/17,
32/33, or 64/65. See Tables IV and VI. It is based on a syn-
chronous 4/5 core.
RF/IF A AND B COUNTERS
The A and B CMOS counters combine with the dual modulus
prescaler to allow a wide ranging division ratio in the PLL
feedback counter. The counters are speciﬁed to work when the
prescaler output is 200 MHz or less, when VDD = 5 V. Typically,
they will work with 250 MHz output from the prescaler. Thus,
with an RF input frequency of 2.5 GHz, a prescaler value of
16/17 is valid, but a value of 8/9 is not valid.
Pulse Swallow Function
The A and B counters, in conjunction with the dual modulus
prescaler make it possible to generate output frequencies which
are spaced only by the Reference Frequency divided by R. The
equation for the VCO frequency is as follows:
fVCO = [(P × B) + A] × fREFIN/R
fVCO=Output Frequency of external voltage controlled
oscillator (VCO).=Preset modulus of dual modulus prescaler (8/9,
16/17, etc.).=Preset Divide Ratio of binary 13-bit counter
(3 to 8191).=Preset Divide Ratio of binary 6-bit A counter
(0 to 63).
fREFIN=External reference frequency oscillator.=Preset divide ratio of binary 15-bit programmable refer-
ence counter (1 to 32767).
Figure 4.RF/IF A and B Counters
RF/IF COUNTER
The 15-bit RF/IF R counter allows the input reference fre-
quency to be divided down to product the input clock to the
phase frequency detector (PFD). Division ratios from 1 to
32767 are allowed.
ADF4210/ADF4211/ADF4212/ADF4213
PHASE FREQUENCY DETECTOR (PFD) AND CHARGE
PUMP
The PFD takes inputs from the R counter and N counter and
produces an output proportional to the phase and frequency
difference between them. Figure 5 is a simpliﬁed schematic.
The PFD includes a ﬁxed-delay element that sets the width of
the antibacklash pulse. This is typically 3 ns. This pulse ensures
that there is no deadzone in the PFD transfer function and gives
a consistent reference spur level.
Figure 5.RF/IF PFD Simpliﬁed Schematic and Timing
(In Lock)
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF421x family allows the
user to access various internal points on the chip. The state of
MUXOUT is controlled by P3, P4, P11, and P12. See Tables
III and V. Figure 6 shows the MUXOUT section in block dia-
gram form.
DVDD
MUXOUT
DGND
IF ANALOG LOCK DETECT
IF R COUNTER OUTPUT
IF N COUNTER OUTPUT
IF/RF ANALOG LOCK DETECT
RF R COUNTER OUTPUT
RF N COUNTER OUTPUT
RF ANALOG LOCK DETECT
DIGITAL LOCK DETECT
Figure 6.MUXOUT Circuit
Lock Detect
MUXOUT can be programmed for two types of lock detect:
Digital Lock Detect and Analog Lock Detect. Digital Lock
Detect is active high. It is set high when the phase error on three
consecutive Phase Detector cycles is less than 15 ns. It will stay
set high until a phase error of greater than 25 ns is detected on
any subsequent PD cycle. The N-channel open-drain analog
lock detect should be operated with an external pull-up resistor
of 10 kΩ nominal. When lock has been detected, it is high with
narrow low-going pulses.
RF/IF INPUT SHIFT REGISTER
The ADF421x family digital section includes a 24-bit input shift
register, a 14-bit IF R counter and a 18-bit IF N counter, com-
prising a 6-bit IF A counter and a 12-bit IF B counter. Also
present is a 14-bit RF R counter and an 18-bit RF N counter,
comprising a 6-bit RF A counter and a 12-bit RF B counter.
Data is clocked into the 24-bit shift register on each rising edge
of CLK. The data is clocked in MSB ﬁrst. Data is transferred
from the shift register to one of four latches on the rising edge of
LE. The destination latch is determined by the state of the two
control bits (C2, C1) in the shift register. These are the two LSBs
DB1, DB0 as shown in the timing diagram of Figure 1. The
truth table for these bits is shown in Table VI. Table I shows a
summary of how the latches are programmed.
Table I.C2, C1 Truth Table

Partno	Mfg	Dc	Qty	Available	Descript
ADF4212BRU	ADI	N/a	396	avai	Dual, Integer-N 0.5 GHz/3.0 GHz PLL