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ADF4206BRU
Dual RF PLL Frequency Synthesizers
REV.0
Dual RF PLL Frequency Synthesizers
FUNCTIONAL BLOCK DIAGRAM
CLOCK
DATA
MUXOUT
CPRF1
CPRF2
OSCIN
RF1INA
RF1INBDD1VDD2VP1VP2
AGNDRF1DGNDRF1DGNDRF2AGNDRF2
RF2INA
RF2INB
OSCOUT
FEATURES
ADF4206:550 MHz/550 MHz
ADF4207:1.1 GHz/1.1 GHz
ADF4208:2.0 GHz/1.1 GHz
2.7 V to 5.5 V Power Supply
Selectable Charge Pump Supply (VP) Allows Extended
Tuning Voltage in 3 V Systems
Selectable Charge Pump Currents
On-Chip Oscillator Circuit
Selectable Dual Modulus Prescaler
RF2:32/33 or 64/65
RF1:32/33 or 64/65
3-Wire Serial Interface
Power-Down Mode
APPLICATIONS
Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA)
Base Stations for Wireless Radio (GSM, PCS, DCS,
CDMA, WCDMA)
Wireless LANS
Communications Test Equipment
CATV Equipment
GENERAL DESCRIPTIONThe ADF4206 family of dual frequency synthesizers can be
used to implement local oscillators in the upconversion and
downconversion sections of wireless receivers and transmitters.
Each synthesizer consists of a low-noise digital PFD (Phase
Frequency Detector), a precision charge pump, a programmable
reference divider, programmable A and B counters and a dual-
modulus prescaler (P/P + 1). The A (6-bit) and B (11-bit)
counters, in conjunction with the dual modulus prescaler (P/P + 1),
implement an N divider (N = BP + A). In addition, the 14-bit
reference counter (R Counter), allows selectable REFIN frequen-
cies at the PFD input. The on-chip oscillator circuitry allows
the reference input to be derived from crystal oscillators.
A complete PLL (Phase-Locked Loop) can be implemented if
the synthesizers are used with an external loop filter and VCOs
(Voltage Controlled Oscillators).
Control of all the on-chip registers is via a simple 3-wire interface.
The devices operate with a power supply ranging from 2.7 V
to 5.5 V and can be powered down when not in use.
ADF4206/ADF4207/ADF4208–SPECIFICATIONS1(VDD1 = VDD2 = 3 V � 10%, 5 V � 10%;
VDD1, VDD2 � VP1, VP2 � 6.0 V; AGNDRF1 = DGNDRF1 = AGNDRF2 = DGNDRF2 = 0 V; TA = TMIN to TMAX unless otherwise noted, dBm referred to 50 �.)RF/IF CHARACTERISTICS (3 V)
LOGIC OUTPUTS
POWER SUPPLIES
ADF4206/ADF4207/ADF4208NOISE CHARACTERISTICS
NOTESOperating temperature range is as follows: B Version: –40°C to +85°C.The B Chip specifications are given as typical values.This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that is
less than this value.VDD1 = VDD2 = 3 V; For VDD1 = VDD2 = 5 V, use CMOS-compatible levels.
5Guaranteed by design. Sample tested to ensure compliance.Typical values apply for VDD = 3 V; P = 32; RF1IN1/RF2IN2 for ADF4206 = 540 MHz; RF1IN1/RF2IN2 for ADF4207 = 900 MHz; RF1IN1/RF2IN2 for ADF4208 = 900 MHz.The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 logN (where N is the N divider value).The phase noise is measured at a 1 kHz unless otherwise noted. The phase noise is measured with the EVAL-ADF4206/ADF4207EB or the EVAL-AD4208EB Evaluation
Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for the synthesizer (fREFOUT = 10 MHz @ 0 dBm).fREFIN = 10 MHz; fPFD = 30 kHz; Offset Frequency = 300 Hz; fRF/IF = 836 MHz; N = 27866; Loop B/W = 3 kHz.
10fREFIN = 10 MHz; fPFD = 10 kHz; Offset Frequency = 200 Hz; fRF = 1750 MHz; N = 175000; Loop B/W = 1 kHz.
Specifications subject to change without notice.
ADF4206/ADF4207/ADF4208
TIMING CHARACTERISTICSNOTES
Guaranteed by design but not production tested.
Specification subject to change without notice.
(VDD1 = VDD2 = 3 V � 10%, 5 V � 10%; VDD1, VDD2 ≤ VP1, VP2 ≤ 6.0 V; AGNDRF1 = DGNDRF1 =
AGNDRF2 = DGNDRF2 = 0 V; TA = TMIN to TMAX unless otherwise noted, dBm referred to 50 �.)Figure 1.Timing Diagram
ABSOLUTE MAXIMUM RATINGS1, 2(TA = 25°C unless otherwise noted.)
VDD1 to GND3 . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
VDD1 to VDD2 . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
VP1, VP2 to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
VP1, VP2 to VDD1 . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.5 V
Digital I/O Voltage to GND . . . . . . –0.3 V to DVDD + 0.3 V
Analog I/O Voltage to GND . . . . . . . . . –0.3 V to VP + 0.3 V
OSCIN, OSCOUT, RF1IN (A, B),
RF2IN (A, B) to GND . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
RFINA to RFINB (RF1, RF2) . . . . . . . . . . . . . . . . . . ±320 mV
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . .–40°C to +85°C
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C
TSSOP θJA Thermal Impedance . . . . . . . . . . . . . 150.4°C/W
CSP θJA (Paddle Soldered) . . . . . . . . . . . . . . . . . . . 122°C/W
CSP θJA (Paddle Not Soldered) . . . . . . . . . . . . . . . . 216°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.This device is a high-performance RF integrated circuit with an ESD rating of
< 2 kV and it is ESD sensitive. Proper precautions should be taken for handling
and assembly.GND = AGND = DGND = 0 V.
TRANSISTOR COUNT11749 (CMOS) and 522 (Bipolar).
ORDERING GUIDEADF4207BRU
*Contact the factory for chip availability.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
PIN FUNCTION DESCRIPTIONS
PIN CONFIGURATIONS
TSSOP
TSSOP
ADF4206/ADF4207/ADF4208
–Typical Performance CharacteristicsTPC 1.S-Parameter Data for the AD4208 RF1 Input
(Up to 2.5 GHz)
TPC 2.Input Sensitivity for the ADF4208 (RF1)
TPC 3.ADF4208 RF1 Phase Noise (900 MHz, 200 kHz,
20 kHz)
TPC 4.ADF4208 RF1 Reference Spurs (900 MHz,
200 kHz, 20 kHz)
FREQUENCY OFFSET FROM 900MHz CARRIER
100Hz1MHz
PHASE NOISE
dBc/Hz
1kHz10kHz100kHzTPC 5.ADF4208 RF1 Integrated Phase Noise (900 MHz,
200 kHz, 20 kHz)
FREQUENCY OFFSET FROM 900MHz CARRIER
100Hz1MHz
PHASE NOISE
dBc/Hz
1kHz10kHz100kHzTPC 6.ADF4208 RF1 Integrated Phase Noise (900 MHz,
200 kHz, 35 kHz)
TPC 7.ADF4208 RF1 Reference Spurs (900 MHz,
200 kHz, 35 kHz)
FREQUENCY – Hz
400–400–2001750M200
OUTPUT POWER
dB
–100TPC 8.ADF4208 RF1 Phase Noise (1750 MHz, 30 kHz, 3 kHz)
FREQUENCY OFFSET FROM 1750MHz CARRIER
100Hz1MHz
PHASE NOISE
dBc/Hz
1kHz10kHz100kHzTPC 9.ADF4208 RF1 Integrated Phase Noise (1750 MHz,
30 kHz, 3 kHz)
TPC 10.ADF4208 RF1 Reference Spurs (1750 MHz,
30 kHz, 3 kHz)
TPC 11.ADF4208 RF1 Phase Noise vs. PFD Frequency
TPC 12.ADF4208 RF1 Phase Noise vs. Temperature
(900 MHz, 200 kHz, 20 kHz)
ADF4206/ADF4207/ADF4208
TEMPERATURE – �C
FIRST REFERENCE SPUR
dBc–70
–20TPC 13.ADF4208 RF1 Reference Spurs vs. Temperature
(900 MHz, 200 kHz, 20 kHz)
TUNING VOLTAGE – V0234–105
FIRST REFERENCE SPUR
dBc
–25TPC 14.ADF4208 RF1 Reference Spurs vs. VTUNE
(900 MHz, 200 kHz, 20 kHz)
TPC 15.ADF4208 RF2 Phase Noise vs. PFD Frequency
PRESCALER OUTPUT FREQUENCY – MHz
mA
10050TPC 16DIDD vs. Prescaler Output Frequency (All Models,
RF1 and RF2)
PRESCALER VALUE32/3364/65
mATPC 17.ADF4206/ADF4207/ADF4208 AIDD vs. Prescaler
Value (RFI)
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTIONThe reference input stage is shown in Figure 2. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2
are opened. Typical recommended external components are
shown in Figure 2.
Figure 2.RF Input Stage
RF INPUT STAGEThe RF input stage is shown in Figure 3. It is followed by a
2-stage limiting amplifier to generate the CML clock levels needed
for the prescaler.
Figure 3.RF Input Stage
PRESCALERThe dual modulus prescaler (P/P + 1), along with the A and
B counters, enables the large division ratio, N, to be realized
(N = BP + A). This prescaler, operating at CML levels, takes
the clock from the RF input stage and divides it down to a man-
ageable frequency for the CMOS A and B counters. It is based
on a synchronous 4/5 core.
The prescaler is selectable. Both RF1 and RF2 can be set to
either 32/33 or 64/65. DB20 of the AB counter latch selects
the value. See Tables IV and VI.
A AND B COUNTERSThe A and B CMOS counters combine with the dual modulus
prescaler to allow a wide ranging division ratio in the PLL feed-
back counter. The devices are guaranteed to work when the
prescaler output is 200 MHz or less.
Pulse Swallow FunctionThe A and B counters, in conjunction with the dual modulus
prescaler, make it possible to generate output frequencies that
are spaced only by the Reference Frequency divided by R. The
equation for the VCO frequency is as follows:
fVCO = [(P × B) + A] × fREFIN/R
fVCO=Output frequency of external voltage controlled
oscillator (VCO).=Preset modulus of dual modulus prescaler
(32/33, 64/65).=Preset Divide Ratio of binary 11-bit counter
(1 to 2047).=Preset Divide Ratio of binary 6-bit A counter
(0 to 63).
fREFIN=Output frequency of the external reference frequency
oscillator.=Preset divide ratio of binary 14-bit programmable
reference counter (1 to 16383).
R COUNTERThe 14-bit R counter allows the input reference frequency to
be divided down to produce the reference clock to the phase
frequency detector (PFD). Division ratios from 1 to 16,383
are allowed.
Figure 4.A and B Counters
PHASE FREQUENCY DETECTOR (PFD) AND CHARGE
PUMPThe PFD takes inputs from the R counter and N counter (N =
BP + A) and produces an output proportional to the phase and
frequency difference between them. Figure 5 is a simplified
schematic.
ADF4206/ADF4207/ADF4208U3
CHARGE
PUMP
DOWNHI
R DIVIDER
N DIVIDER
CP OUTPUT
CPGNDFigure 5.PFD Simplified Schematic and Timing (In Lock)
The PFD includes a delay element which sets the width of the
antibacklash phase. The typical value for this is in the ADF4206
family is 3 ns. The pulse ensures that there is no deadzone in
the PFD transfer function and minimizes phase noise and refer-
ence spurs.
MUXOUT AND LOCK DETECTThe output multiplexer on the ADF4206 family allows the
user to access various internal points on the chip. The state
of MUXOUT is controlled by P3, P4, P11, and P12. See
Tables III and V. Figure 6 shows the MUXOUT section in
block diagram form.
DVDD
MUXOUT
DGND
RF2 ANALOG LOCK DETECT
RF2 R COUNTER OUTPUT
RF2 N COUNTER OUTPUT
RF2/RF1 ANALOG LOCK DETECT
RF1 R COUNTER OUTPUT
RF1 N COUNTER OUTPUT
RF1 ANALOG LOCK DETECTFigure 6.MUXOUT Circuit
Lock DetectMUXOUT can be programmed for analog lock detect. The
N-channel open-drain analog lock detect should be operated
with an external pull-up resistor of 10 kΩ nominal. When lock
has been detected it is high with narrow low-going pulses.
INPUT SHIFT REGISTERThe functional block diagram for the ADF4206 family is shown
on Page 1. The main blocks include a 22-bit input shift register,
a 14-bit R counter, and an 17-bit N counter, comprising a 6-bit
A counter and an 11-bit B counter. Data is clocked into the 22-bit
shift register on each rising edge of CLK. The data is clocked
in MSB first. Data is transferred from the shift register to one of
four latches on the rising edge of LE. The destination latch is
determined by the state of the two control bits (C2, C1) in the
shift register. These are the two LSBs DB1, DB0, as shown in
the timing diagram of Figure 1. The truth table for these bits is
shown in Table I.
Table I.C2, C1 Truth Table
