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ADF4154BRU-ADF4154BRUZ-ADF4154BRUZ-RL7
Fractional-N Frequency Synthesizer
Fractional-N Frequency Synthesizer Rev. 0
FEATURES
RF bandwidth 500 MHz to 4 GHz
2.7 V to 3.3 V power supply
Separate VP allows extended tuning voltage
Programmable dual-modulus prescaler 4/5, 8/9
Programmable charge pump currents
3-wire serial interface
Digital lock detect
Power-down mode
Pin compatible with the ADF4110/ADF4111/
ADF4112/ADF4113, ADF4106 and ADF4153
Programmable modulus on fractional-N synthesizer
Trade-off noise versus spurious performance
Fast-lock mode with built-in timer
APPLICATIONS
CATV equipment
Base stations for mobile radio (GSM, PCS, DCS,
CDMA, WCDMA)
Wireless handsets (GSM, PCS, DCS, CDMA, WCDMA)
Wireless LANs
Communications test equipment
GENERAL DESCRIPTION The ADF4154 is a fractional-N frequency synthesizer that
implements local oscillators in the up conversion and down
conversion sections of wireless receivers and transmitters. It
consists of a low noise digital phase frequency detector (PFD),
a precision charge pump, and a programmable reference divider.
There is a Σ-Δ based fractional interpolator to allow program-
mable fractional-N division. The INT, FRAC, and MOD regis-
ters define an overall N divider (N = (INT + (FRAC/MOD))).
In addition, the 4-bit reference counter (R counter) allows
selectable REFIN frequencies at the PFD input. A complete
phase-locked loop (PLL) can be implemented if the synthesizer
is used with an external loop filter and a voltage controlled
oscillator (VCO).
A key feature of the ADF4154 is the fast-lock mode with a built-
in timer. The user can program a predetermined count-down
time value so that the PLL will remain in wide bandwidth mode,
instead of having to control this time externally.
Control of all on-chip registers is via a simple 3-wire interface.
The device operates with a power supply ranging from 2.7 V to
3.3 V, and can be powered down when not in use.
FUNCTIONAL BLOCK DIAGRAM
DATA
CLOCK
REFIN
AVDD
AGND
DGNDCPGND
DVDDVPSDVDDRSET
RFINA
RFINBMUXOUT04833-0-001
Figure 1.
TABLE OF CONTENTS Specifications.....................................................................................3
Timing Characteristics.....................................................................4
Absolute Maximum Ratings............................................................5
ESD Caution..................................................................................5
Pin Configuration and Pin Function Descriptions......................6
Typical Performance Characteristics.............................................7
Circuit Description...........................................................................9
Reference Input Section...............................................................9
RF Input Stage...............................................................................9
RF INT Divider.............................................................................9
INT, FRAC, MOD, and R Relationship......................................9
RF R Counter................................................................................9
Phase Frequency Detector (PFD) and Charge Pump..............9
MUXOUT and Lock Detect......................................................10
Input Shift Registers...................................................................10
Program Modes..........................................................................10
Registers...........................................................................................11
Register Definition.....................................................................15
R-Divider Register, R1...............................................................15
Control Register, R2...................................................................15
Noise and Spur Register, R3......................................................16
Reserved Bits...............................................................................16
RF Synthesizer: A Worked Example........................................16
Modulus.......................................................................................17
Reference Doubler and Reference Divider.............................17
12-Bit Programmable Modulus................................................17
Spurious Optimization and Fast-lock......................................17
Fast-Lock Timer and Register Sequences...............................17
Fast-Lock: A Worked Example.................................................18
Fast-Lock: Loop Filter Topology..............................................18
Spurious Signals..........................................................................18
Filter Design—ADIsimPLL.......................................................18
Interfacing...................................................................................18
PCB Design Guidelines for Chip Scale Package....................19
Outline Dimensions.......................................................................20
Ordering Guide..........................................................................20
SPECIFICATIONS
Table 1. AVDD = DVDD = SDVDD = 2.7 V to 3.3 V; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise
noted; dBm referred to 50 Ω. The operating temperature for the B version is −40°C to +80°C. Use a square wave for frequencies below fMIN.
2 Guaranteed by design. Sample tested to ensure compliance. AC coupling ensures AVDD/2 bias. See for typical circuit. Figure 17
4 This figure can be used to calculate phase noise for any application. Use the formula –213 + 10log(fPFD) + 20logN to calculate in-band phase noise performance, as seen
at the VCO output. The value given is the lowest noise mode.
5 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N-divider value).
TIMING CHARACTERISTICS
Table 2. AVDD = DVDD = SDVDD = 2.7 V to 3.3 V; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise
noted; dBm referred to 50 Ω. Guaranteed by design, but not production tested.
CLOCK
DATA04833-0-026
Figure 2. Timing Diagram
ABSOLUTE MAXIMUM RATINGS
Table 3. Absolute Maximum Ratings.1, 2, 3 TA = 25°C, unless
otherwise noted. Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
This device is a high performance RF integrated circuit with an ESD rating of
< 2 kV, and it is ESD sensitive. Proper precautions should be taken for
handling and assembly.
2 GND = AGND = DGND = 0 V. VDD = AVDD = DVDD = SDVDD.
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS
AGND
RFINB
RFINA
AVDD
REFIN
DATA
CLK
SDVDD
DGND
RSET
CPGND
DVDD
MUXOUT04833-0-002
Figure 3. TSSOP Pin Configuration
04833-0-003
MUXOUTDATA
CLK
SDVDD789
DGNDDGNDRERFINA
RFINB
AGND
AGND
CPGND181716
ADF4154
TOP VIEWR
SET
PIN 1INDICATORFigure 4. LFCSP Pin Configuration
Table 4. Pin Function Descriptions TYPICAL PERFORMANCE CHARACTERISTICS Figure 5 to Figure 10, and Figure 12: RFOUT = 1.722 GHz, PFD Frequency = 26 MHz, INT = 66, Channel Spacing = 200 kHz,
Modulus = 130, Fraction = 30/130, and ICP = 5 mA.
Loop Bandwidth = 20 kHz, Reference = 26 MHz, VCO = Vari-L VCO190-1750T, Evaluation Board = EVAL-ADF4154EB1. Measurements
were taken on the HP8562E spectrum analyzer.
OUTP
UT P
R (dB)
–2kHz–1kHz1kHz2kHz1.722GHz04833-0-004
Figure 5. Phase Noise (Lowest Noise Mode)
OUTP
UT P
R (dB)
–2kHz–1kHz1kHz2kHz1.722GHz04833-0-005
Figure 6. Phase Noise (Low Noise Mode and Spur Mode)
OUTP
UT P
R (dB)
–2kHz–1kHz1kHz2kHz1.722GHz04833-0-006
OUTP
UT P
R (dB)
–400kHz–200kHz200kHz400kHz1.722GHz–10004833-0-007
Figure 8. Spurs (Lowest Noise Mode)
OUTP
UT P
R (dB)
–400kHz–200kHz200kHz400kHz1.722GHz04833-0-008
Figure 9. Spurs (Low Noise and Spur Mode)
OUTP
UT P
R (dB)
–400kHz–200kHz200kHz400kHz1.722GHz04833-0-009
SE N
ISE (
PHASE DETECTOR FREQUENCY (kHz)
–17004833-0-010
Figure 11. PFD Noise Floor vs. PFD Frequency (Lowest Noise Mode)
FREQUENCY (GHz)
AMP
ITUDE
(dBm)
–3500.51.01.54.03.53.02.52.04.504833-0-011
Figure 12. RF Input Sensitivity
VCP(V)
ICP
(mA)04833-0-012
Figure 13. Charge Pump Output Characteristics
RSET VALUE (kΩ)
SE N
ISE (–90
–10004833-0-013
Figure 14. Phase Noise vs. RSET
TEMPERATURE(°C)
SE N
ISE (
–10004833-0-014
Figure 15. Phase Noise vs. Temperature
04833-0-028
TIME (µs)
FRE
NCY
(GHz)
1.640Figure 16. A) Lock Time in Fast-lock Mode. Fast Counter = 150, Low Spur
Mode: a 1649.7 MHz to 1686.8 MHz Frequency Jump.
Final Loop Bandwidth = 60 kHz
B) Lock Time with the PLL in Normal Mode (Non Fast-lock), Low Spur Mode, a
1649.7 MHz to 1686.8 MHz Frequency Jump. Final Loop Bandwidth = 60 kHz
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION The reference input stage is shown in Figure 17. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that the REFIN pin is not loaded on
power-down.
TO R COUNTERREFIN
100kΩ
SW1
POWER-DOWN
CONTROL04833-0-027
Figure 17. Reference Input Stage
RF INPUT STAGE The RF input stage is shown in Figure 18. It is followed by a
2-stage limiting amplifier to generate the current mode logic
(CML) clock levels needed for the prescaler.
AGND
AVDD
RFINB
RFINA04833-0-015
Figure 18. RF Input Stage
RF INT DIVIDER The RF INT CMOS counter allows a division ratio in the PLL
feedback counter. Division ratios from 31 to 511 are allowed.
INT, FRAC, MOD, AND R RELATIONSHIP The INT, FRAC, and MOD values, in conjunction with the
R counter, make it possible to generate output frequencies that
are spaced by fractions of the phase frequency detector (PFD).
See the RF Synthesizer: A Worked Example section for more
information. The RF VCO frequency (RFOUT) equation is MODFRFPFDOUT+×= (1)
where RFOUT is the output frequency of the external voltage DREFFINPFD (2)
where:
REFIN is the reference input frequency.
D is the REFIN doubler bit.
R is the preset divide ratio of binary 4-bit programmable
reference counter (1 to 15).
INT is the preset divide ratio of binary 9-bit counter (31 to 511).
MOD is the preset modulus ratio of binary 12-bit program-
mable FRAC counter (2 to 4095).
FRAC is the preset fractional ratio of binary 12-bit
programmable FRAC counter (0 to MOD).
RF R COUNTER The 4-bit RF R counter allows the input reference frequency
(REFIN) to be divided down to produce the reference clock to
the PFD. Division ratios from 1 to 15 are allowed.
FROM RF
INPUT STAGE04833-0-016
Figure 19. A and B Counters
PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP The PFD takes inputs from the R counter and N counter and
produces an output proportional to the phase and frequency
difference between them. Figure 20 is a simplified schematic.
The PFD includes a fixed delay element that sets the width of
the antibacklash pulse, which is typically 3 ns. This pulse
ensures that there is no dead zone in the PFD transfer function
and gives a consistent reference spur level.
HI
–IN
+IN04833-0-017
MUXOUT AND LOCK DETECT The output multiplexer on the ADF4154 allows the user to
access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2, and M1 (see Table 9).
Figure 21 shows the MUXOUT section in block diagram form.
The N-channel, open-drain, analog lock detect should be
operated with an external pull-up resistor of 10 kΩ nominal.
When lock has been detected, the lock detect is high with
narrow low-going pulses.
R-DIVIDER OUTPUT
N-DIVIDER OUTPUT
ANALOG LOCK DETECT
DGNDMUXOUT
DVDD
LOGIC LOW
FAST-LOCK CONTROL
THREE-STATE OUTPUT
DIGITAL LOCK DETECTLOGIC HIGH
Figure 21. MUXOUT Schematic
INPUT SHIFT REGISTERS The ADF4154 digital section includes a 4-bit RF R counter, a
9-bit RF N counter, a 12-bit FRAC counter, and a 12-bit
modulus counter. Data is clocked into the 24-bit shift register
on each rising edge of CLK. The data is clocked in MSB first.
Data is transferred from the shift register to one of four latches
on the rising edge of LE. The destination latch is determined by
the state of the two control bits (C2 and C1) in the shift register.
These are the 2 LSBs, DB1, and DB0, as shown in Figure 2. The
truth table for these bits is shown in Table 5. Table 6 shows a
summary of how the latches are programmed.
PROGRAM MODES Table 5 through Table 10 show how to set up the program
modes in the ADF4154.
The ADF4154 programmable modulus is double-buffered. This
means that two events have to occur before the part uses a new
modulus value. First, the new modulus value is latched into the
device by writing to the R-divider register. Second, a new write
must be performed on the N-divider register. Therefore, when-
ever the modulus value is updated, the N-divider register must
then be written to so that the modulus value is loaded correctly.
Table 5. C2 and C1 Truth Table
