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ADF4153-ADF4153BCP-ADF4153BRU-ADF4153BRU-REEL7
Fractional-N Frequency Synthesizer
Fractional-N Frequency Synthesizer Rev. A
FEATURES
RF bandwidth 500 MHz to 4 GHz
2.7 V to 3.3 V power supply
Separate VP allows extended tuning voltage
Programmable dual-modulus prescaler 4/5, 8/9
Programmable charge pump currents
3-wire serial interface
Analog and digital lock detect
Power-down mode
Pin compatible with the
ADF4110/ADF4111/ADF4112/ADF4113 and ADF4106
Programmable modulus on fractional-N synthesizer
Trade-off noise versus spurious performance
APPLICATIONS
CATV equipment
Base stations for mobile radio (GSM, PCS, DCS,
CDMA, WCDMA)
Wireless handsets (GSM, PCS, DCS, CDMA, WCDMA)
Wireless LANs
Communications test equipment
GENERAL DESCRIPTION The ADF4153 is a fractional-N frequency synthesizer that
implements local oscillators in the upconversion and
downconversion sections of wireless receivers and transmitters.
It consists of a low noise digital phase frequency detector
(PFD), a precision charge pump, and a programmable reference
divider. There is a Σ-Δ based fractional interpolator to allow
programmable fractional-N division. The INT, FRAC, and
MOD registers define an overall N divider (N = (INT +
(FRAC/MOD))). In addition, the 4-bit reference counter (R
counter) allows selectable REFIN frequencies at the PFD input.
A complete phase-locked loop (PLL) can be implemented if the
synthesizer is used with an external loop filter and a voltage
controlled oscillator (VCO).
Control of all on-chip registers is via a simple 3-wire interface.
The device operate with a power supply ranging from 2.7 V to
3.3 V and can be powered down when not in use.
FUNCTIONAL BLOCK DIAGRAM
DATA
CLOCK
REFIN
AVDD
AGND
DGNDCPGND
DVDDVPSDVDDRSET
RFINA
RFINBMUXOUT03685-A
Figure 1.
TABLE OF CONTENTS Specifications.....................................................................................3
Timing Characteristics.....................................................................5
Absolute Maximum Ratings............................................................6
ESD Caution..................................................................................6
Pin Configuration and Pin Function Descriptions......................7
Typical Performance Characteristics.............................................8
Circuit Description.........................................................................10
Reference Input Section.............................................................10
RF Input Stage.............................................................................10
RF INT Divider...........................................................................10
INT, FRAC, MOD, and R Relationship....................................10
RF R COUNTER........................................................................10
Phase Frequency Detector (PFD) and Charge Pump............11
MUXOUT and LOCK Detect...................................................11
Input Shift Registers...................................................................11
Program Modes..........................................................................11
N Divider Register, R0...............................................................17
R Divider Register, R1................................................................17
Control Register, R2...................................................................17
Noise and Spur Register, R3......................................................18
Reserved Bits...............................................................................18
RF Synthesizer: A Worked Example........................................18
Modulus.......................................................................................19
Reference Doubler and Reference Divider.............................19
12-Bit Programmable Modulus................................................19
Spurious Optimization and Fastlock.......................................19
Phase Resync and Spur Consistency.......................................19
Spurious Signals—Predicting Where They Will Appear.......20
Filter Design—ADIsimPLL.......................................................20
Interfacing...................................................................................20
PCB Design Guidelines for Chip Scale Package....................21
Outline Dimensions.......................................................................22
Ordering Guide..........................................................................22
REVISION HISTORY 1/04—Data Sheet Changed from a REV. 0 to a REV. A
Renumbered Figures and Tables..............................UNIVERSAL
Changes to Specifications...............................................................3
Changes to Pin Function Description..........................................7
Changes to RF Power-Down section..........................................17
Changes to PCB Design Guidelines for Chip Scale
Package section..............................................................................21
Updated Outline Dimensions......................................................22
Updated Ordering Guide..............................................................22
7/03—Revision 0: Initial Version
SPECIFICATIONS1 AVDD = DVDD = SDVDD = 2.7 V to 3.3 V; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted; dBm
referred to 50 Ω.
Table 1. See footnotes on next page.
1 Operating temperature is B version: −40°C to +80°C. Use a square wave for frequencies below fMIN.
3 Guaranteed by design. Sample tested to ensure compliance. AC coupling ensures AVDD/2 bias. See Figure 16 for typical circuit.
5 This figure can be used to calculate phase noise for any application. Use the formula –217 + 10log(fPFD) + 20logN to calculate in-band phase noise performance as seen
at the VCO output. The value given is the lowest noise mode.
6 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value).
The value given is the lowest noise mode. The phase noise is measured with the EVAL-ADF4153EB1 evaluation board and the HP8562E spectrum analyzer. fREFIN = 26 MHz; fPFD = 10 MHz; offset frequency = 1 kHz; RFOUT = 1750 MHz; N = 175; loop B/W = 20 kHz; lowest noise mode.
TIMING CHARACTERISTICS1 AVDD = DVDD = SDVDD = 2.7 V to 3.3 V; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted; dBm
referred to 50 Ω.
Table 2. Guaranteed by design but not production tested.
DATA Figure 2. Timing Diagram
ABSOLUTE MAXIMUM RATINGS1, 2, 3, 4 TA = 25°C, unless otherwise noted.
Table 3. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2 This device is a high performance RF integrated circuit with an ESD rating of < 2 kV, and it is ESD sensitive. Proper precautions should be taken for handling and
assembly.
3 GND = AGND = DGND = 0 V. VDD = AVDD = DVDD = SDVDD.
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS
AGND
RFINB
RFIINA
AVDD
REFIN
DATA
CLK
SDVDD
DGND
RSET
CPGND
DVDD
MUXOUT03685-A
Figure 3. TSSOP Pin Configuration
03685-A
CPGND1
AGND2
AGND3
MUXOUT
DATA
CLK
SDVDD
DGND
DGND
RFINB4
RFINA5
SET18171620191716
PIN 1INDICATOR
ADF4153TOP VIEW
Figure 4. LFCSP Pin Configuration
Table 4. Pin Function Descriptions TYPICAL PERFORMANCE CHARACTERISTICS Figure 5 to Figure 10: RFOUT = 1.722 GHz, PFD Freq = 26 MHz, INT = 66, Channel Spacing = 200 kHz, Modulus = 130, Fraction = 1/130,
and ICP = 5 mA.
Loop Bandwidth = 20 kHz, Reference = Fox 10 MHz TCXO, VCO = Vari-L VCO190-1750T, Eval Board = Eval-ADF4153EB1,
measurements taken on HP8562E spectrum analyzer.
OUTP
UT P
R (dB)
–2kHz–1kHz1kHz2kHz1.722GHz03685-A
Figure 5. Phase Noise (Lowest Noise Mode)
OUTP
UT P
R (dB)
–2kHz–1kHz1kHz2kHz1.722GHz03685-A
Figure 6. Phase Noise (Low Noise Mode and Spur Mode)
OUTP
UT P
R (dB)
–2kHz–1kHz1kHz2kHz1.722GHz03685-A
Figure 7. Phase Noise (Lowest Spur Mode)
OUTP
UT P
R (dB)
–400kHz–200kHz200kHz400kHz1.722GHz–10003685-A
Figure 8. Spurs (Lowest Noise Mode)
OUTP
UT P
R (dB)
–400kHz–200kHz200kHz400kHz1.722GHz03685-A
Figure 9. Spurs (Low Noise and Spur Mode)
OUTP
UT P
R (dB)
–400kHz–200kHz200kHz400kHz1.722GHz03685-A
Figure 10. Spurs (Lowest Spur Mode)
SE N
OISE (
PHASE DETECTOR FREQUENCY (kHz)
–170Figure 11. PFD Noise Floor vs. PFD Frequency (Lowest Noise Mode)
FREQUENCY (GHz)
AMP
LITUDE
(dBm)
–3500.51.01.54.03.53.02.52.04.503685-A
Figure 12. RF Input Sensitivity
VCP(V)
(mA)Figure 13. Charge Pump Output Characteristics
RSET VALUE (kΩ)
SE N
OISE (–90
–100Figure 14. Phase Noise vs. RSET
SE N
OISE (
–100Figure 15. Phase Noise vs. Temperature
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION The reference input stage is shown in Figure 16. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REFIN pin
on power-down.
TO R COUNTERREFIN
100kΩ
SW1
POWER-DOWN
CONTROL
Figure 16. Reference Input Stage
RF INPUT STAGE The RF input stage is shown in Figure 17. It is followed by a
2-stage limiting amplifier to generate the current mode logic
(CML) clock levels needed for the prescaler.
AGND
RFINB
RFINA03685-A
Figure 17. RF Input Stage
RF INT DIVIDER The RF INT CMOS counter allows a division ratio in the PLL
feedback counter. Division ratios from 31 to 511 are allowed.
INT, FRAC, MOD, AND R RELATIONSHIP The INT, FRAC, and MOD values, in conjunction with the
R counter, make it possible to generate output frequencies that
are spaced by fractions of the phase frequency detector (PFD).
See the RF Synthesizer: A Worked Example section for more
information. The RF VCO frequency (RFOUT) equation is MODFRFPFDOUT
where RFOUT is the output frequency of external voltage
controlled oscillator (VCO). RDREFFINPFD (2)
where:
REFIN is the reference input frequency.
D is the REFIN doubler bit.
R is the preset divide ratio of binary 4-bit programmable
reference counter (1 to 15).
INT is the preset divide ratio of binary 9-bit counter (31 to 511).
MOD is the preset modulus ratio of binary 12-bit
programmable FRAC counter (2 to 4095).
FRAC is the preset fractional ratio of binary 12-bit
programmable FRAC counter (0 to MOD).
RF R COUNTER The 4-bit RF R counter allows the input reference frequency
(REFIN) to be divided down to produce the reference clock to
the PFD. Division ratios from 1 to 15 are allowed.
FROM RF
INPUT STAGE03685-A
Figure 18. A and B Counters
PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP The PFD takes inputs from the R counter and N counter and
produces an output proportional to the phase and frequency
difference between them. Figure 19 is a simplified schematic.
The PFD includes a fixed delay element that sets the width of
the antibacklash pulse, which is typically 3 ns. This pulse
ensures that there is no dead zone in the PFD transfer function,
and gives a consistent reference spur level.
HI
–IN03685-A
Figure 19. PFD Simplified Schematic
MUXOUT AND LOCK DETECT The output multiplexer on the ADF4153 allows the user to
access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2, and M1 (see Table 8).
Figure 20 shows the MUXOUT section in block diagram form.
The N-channel open-drain analog lock detect should be
operated with an external pull-up resistor of 10 kΩ nominal.
When lock has been detected, it is high with narrow low-going
pulses.
DIGITAL LOCK DETECT
R COUNTER OUTPUT
LOGIC LOW
DGNDMUXOUT
DVDD
THREE-STATE OUTPUT
N COUNTER OUTPUT
ANALOG LOCK DETECT
LOGIC HIGH03685-A
Figure 20. MUXOUT Schematic
INPUT SHIFT REGISTERS The ADF4153 digital section includes a 4-bit RF R counter, a 9-
bit RF N counter, a 12-bit FRAC counter, and a 12-bit modulus
counter. Data is clocked into the 24-bit shift register on each
rising edge of CLK. The data is clocked in MSB first. Data is
transferred from the shift register to one of four latches on the
rising edge of LE. The destination latch is determined by the
state of the two control bits (C2 and C1) in the shift register.
These are the 2 LSBs, DB1 and DB0, as shown in Figure 2. The
truth table for these bits is shown in Table 5. Table 6 shows a
summary of how the latches are programmed.
PROGRAM MODES Table 5 through Table 10 show how to set up the program
modes in the ADF4153.
The ADF4153 programmable modulus is double buffered. This
means that two events have to occur before the part uses a new
modulus value. First, the new modulus value is latched into the
device by writing to the R divider register. Second, a new write
must be performed on the N divider register. Therefore, any
time that the modulus value has been updated, the N divider
register must be written to after this, to ensure that the modulus
value is loaded correctly.
Table 5. C2 and C1 Truth Table
Control Bits Table 6. Register Summary
CONTROL REGA-019
