ADF4116BRU-ADF4117BRU-ADF4118BRU Fast Delivery |IC PHOENIX CO.,LIMITED

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ADF4116BRU-ADF4117BRU-ADF4118BRU
RF PLL Frequency Synthesizers
REV.0
RF PLL Frequency Synthesizers
FEATURES
ADF4116:550 MHz
ADF4117:1.2 GHz
ADF4118:3.0 GHz
2.7 V to 5.5 V Power Supply
Separate VP Allows Extended Tuning Voltage in 3 V
Systems
Selected Charge Pump Currents
Dual Modulus Prescaler
ADF4116:8/9
ADF4117/ADF4118:32/33
3-Wire Serial Interface
Digital Lock Detect
Power-Down Mode
Fast Lock Mode
APPLICATIONS
Base Stations for Wireless Radio (GSM, PCS, DCS,
CDMA, WCDMA)
Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA)
Wireless LANS
Communications Test Equipment
CATV Equipment
GENERAL DESCRIPTION
The ADF4116 family of frequency synthesizers can be used
to implement local oscillators in the up-conversion and down-
conversion sections of wireless receivers and transmitters. They
consist of a low-noise digital PFD (Phase Frequency Detector),
a precision charge pump, a programmable reference divider,
programmable A and B counters and a dual-modulus prescaler
(P/P+1). The A (5-bit) and B (13-bit) counters, in conjunction
with the dual modulus prescaler (P/P+1), implement an N
divider (N = BP+A). In addition, the 14-bit reference counter
(R Counter), allows selectable REFIN frequencies at the PFD
input. A complete PLL (Phase-Locked Loop) can be imple-
mented if the synthesizer is used with an external loop ﬁlter and
VCO (Voltage Controlled Oscillator).
Control of all the on-chip registers is via a simple 3-wire interface.
The devices operate with a power supply ranging from 2.7 V to
5.5 V and can be powered down when not in use.
FUNCTIONAL BLOCK DIAGRAM
ADF4116/ADF4117/ADF4118–SPECIFICATIONS1
(AVDD = DVDD = 3 V � 10%, 5 V � 10%; AVDD ≤ VP ≤ 6.0 V; AGND = DGND = CPGND = 0 V; TA = TMIN to TMAX unless otherwise noted)
RF CHARACTERISTICS
LOGIC INPUTS
ADF4116/ADF4117/ADF4118
value).The phase noise is measured with the EVAL-ADF411xEB Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for
the synthesizer (fREFOUT = 10 MHz @ 0 dBm).fREFIN = 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; fRF = 540 MHz; N = 2700; Loop B/W = 20 kHz.fREFIN = 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; fRF = 900 MHz; N = 4500; Loop B/W = 20 kHz.fREFIN = 10 MHz; fPFD = 30 kHz; Offset frequency = 300 Hz; fRF = 836 MHz; N = 27867; Loop B/W = 3 kHz.fREFIN = 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; fRF = 1750 MHz; N = 8750; Loop B/W = 20 kHz.fREFIN = 10 MHz; fPFD = 10 kHz; Offset frequency = 200 Hz; fRF = 1750 MHz; N = 175000; Loop B/W = 1 kHz.fREFIN = 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; fRF = 1960 MHz; N = 9800; Loop B/W = 20 kHz.Same conditions as above.
Speciﬁcations subject to change without notice.
TIMING CHARACTERISTICS1
NOTEGuaranteed by design but not production tested.
Speciﬁcations subject to change without notice.
(AVDD = DVDD = 3 V � 10%, 5 V � 10%; AVDD ≤ VP < 6.0 V; AGND = DGND = CPGND = 0 V;
TA = TMIN to TMAX unless otherwise noted)
ADF4116/ADF4117/ADF4118
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily accumu-
late on the human body and test equipment and can discharge without detection. Although the
ADF4116/ADF4117/ADF4118 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS1, 2
(TA = 25°C unless otherwise noted)
AVDD to GND3 . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
VP to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
VP to AVDD . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.5 V
Digital I/O Voltage to GND . . . . . . . . –0.3 V to VDD + 0.3 V
Analog I/O Voltage to GND . . . . . . . . . –0.3 V to VP + 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C
TSSOP θJA Thermal Impedance . . . . . . . . . . . . . 150.4°C/W
CSP θJA Thermal Impedance
(Paddle Soldered) . . . . . . . . . . . . . . . . . . . . . . . . . 122°C/W
(Paddle Not Soldered) . . . . . . . . . . . . . . . . . . . . . . 216°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this speciﬁcation is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.This device is a high-performance RF integrated circuit with an ESD rating of
< 2 kV and it is ESD sensitive. Proper precautions should be taken for handling
and assembly.GND = AGND = DGND = 0 V.
TRANSISTOR COUNT
6425 (CMOS) and 303 (Bipolar).
ORDERING GUIDE
*Contact the factory for chip availability.
Figure 1.Timing Diagram
PIN FUNCTION DESCRIPTIONS
PIN CONFIGURATIONS
TSSOP
Chip Scale Package
CPGND
AGND
AGND
RFINB
RFINA
MUXOUT
DATA
CLKFL
REF
DGNDDGND
ADF4116/ADF4117/ADF4118
–Typical Performance Characteristics
Table I.S-Parameter Data for the ADF4118 RF Input
(Up to 1.8 GHz)
RF INPUT FREQUENCY – GHz4.00.51.52.02.53.03.5
RF INPUT POWER
dBm
–45
Figure 2.Input Sensitivity (ADF4118)
Figure 3.ADF4118 Phase Noise (900 MHz, 200 kHz, 20 kHz)
10dB/DIVISIONRL = –40dBc/HzRMS NOISE = 0.64�
100HzFREQUENCY OFFSET FROM 900 MHz CARRIER1MHz
PHASE NOISE
dBc/Hz
–140
Figure 4.ADF4118 Integrated Phase Noise (900 MHz,
200 kHz, 35 kHz, Typical Lock Time: 200 µs)
10dB/DIVISIONRL = –40dBc/HzRMS NOISE = 0.575�
100HzFREQUENCY OFFSET FROM 900 MHz CARRIER1MHz
PHASE NOISE
dBc/Hz
–140
Figure 5.ADF4118 Integrated Phase Noise (900 MHz,
200 kHz, 20 kHz, Typical Lock Time: 400 µs)
Figure 6.ADF4118 Reference Spurs (900 MHz, 200 kHz,
Figure 7.ADF4118 Reference Spurs (900 MHz, 200 kHz,
35 kHz)
Figure 8.ADF4118 Phase Noise (1750 MHz, 30 kHz,
3 kHz)

10dB/DIVISIONRL = –40dBc/HzRMS NOISE = 2.0�
100HzFREQUENCY OFFSET FROM 1.75GHz CARRIER1MHz
PHASE NOISE
dBc/Hz
–140
Figure 9.ADF4118 Integrated Phase Noise (1750 MHz,
30 kHz, 3 kHz)
Figure 10.ADF4118 Reference Spurs (1750 MHz,
30 kHz, 3 kHz)
Figure 11.ADF4118 Phase Noise (2800 MHz, 1 MHz,
100 kHz)

Figure 12.ADF4118 Integrated Phase Noise (2800 MHz,
1 MHz, 100 kHz)
ADF4116/ADF4117/ADF4118
Figure 13.ADF4118 Reference Spurs (2800 MHz, 1 MHz,
100 kHz)
Figure 14.ADF4118 Phase Noise (Referred to CP Out-
put) vs. PFD Frequency
Figure 15.ADF4118 Phase Noise vs. Temperature
(900 MHz, 200 kHz, 20 kHz)
Figure 16.ADF4118 Reference Spurs vs. Temperature
(900 MHz, 200 kHz, 20 kHz)
Figure 17.ADF4118 Reference Spurs (200 kHz) vs.
VTUNE (900 MHz, 200 kHz, 20 kHz)
Figure 18.ADF4118 Phase Noise vs. Temperature
(836 MHz, 30 kHz, 3 kHz)
Figure 19.ADF4118 Reference Spurs vs. Temperature
(836 MHz, 30 kHz, 3 kHz)
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
The reference input stage is shown below in Figure 21. SW1
and SW2 are normally-closed switches. SW3 is normally-open.
When power-down is initiated, SW3 is closed and SW1 and SW2
are opened. This ensures that there is no loading of the REFIN
pin on power-down.
Figure 21.Reference Input Stage
RF INPUT STAGE
The RF input stage is shown in Figure 22. It is followed by a 2-
stage limiting ampliﬁer to generate the CML clock levels needed
for the prescaler.
Figure 22.RF Input Stage
PRESCALER (P/P + 1)
The dual modulus prescale (P/P + 1), along with the A and B
counters, enables the large division ratio, N, to be realized, (N =
PB + A). The dual-modulus prescaler takes the CML clock
A AND B COUNTERS
The A and B CMOS counters combine with the dual modulus
prescaler to allow a wide ranging division ratio in the PLL
feedback counter. The counters are speciﬁed to work when the
prescaler output is 200 MHz or less.
Pulse Swallow Function
The A and B counters, in conjunction with the dual modulus
prescaler make it possible to generate output frequencies which
are spaced only by the Reference Frequency divided by R. The
equation for the VCO frequency is as follows:
fVCO = [(P × B) + A] × fREFIN/R
fVCOOutput Frequency of external voltage controlled oscilla-
tor (VCO).Preset modulus of dual modulus prescaler.Preset Divide Ratio of binary 13-bit counter (3 to 8191).Preset Divide Ratio of binary 5-bit swallow counter
(0 to 31).
fREFINOutput frequency of the external reference frequency
oscillator.Preset divide ratio of binary 14-bit programmable refer-
ence counter (1 to 16383).
R COUNTER
The 14-bit R counter allows the input reference frequency to be
divided down to produce the input clock to the phase frequency
detector (PFD). Division ratios from 1 to 16,383 are allowed.
Figure 20.DIDD vs. Prescaler Output Frequency
(ADF4116, ADF4117, ADF4118)
ADF4116/ADF4117/ADF4118
PHASE FREQUENCY DETECTOR (PFD) AND CHARGE
PUMP
The PFD takes inputs from the R counter and N counter and
produces an output proportional to the phase and frequency
difference between them. Figure 24 is a simpliﬁed schematic.
The PFD includes a ﬁxed delay element which sets the width of
the antibacklash pulse. This is typically 3 ns. This pulse ensures
that there is no dead zone in the PFD transfer function and
gives a consistent reference spur level.
Figure 24.PFD Simpliﬁed Schematic and Timing (In Lock)
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4116 family allows the
user to access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2 and M1 in the function
latch. Table VI shows the full truth table. Figure 25 shows the
MUXOUT section in block diagram form.
DVDD
MUXOUT
DGND
ANALOG LOCK DETECT
DIGITAL LOCK DETECT
R COUNTER OUTPUT
N COUNTER OUTPUT
SDOUT
Figure 25. MUXOUT Circuit
Lock Detect
MUXOUT can be programmed for two types of lock detect:
Digital Lock Detect and Analog Lock Detect.
Digital Lock Detect is active high. It is set high when the phase
error on three consecutive phase detector cycles is less than 15 ns.
It will stay set high until a phase error of greater than 25 ns is
detected on any subsequent PD cycle.
The N-channel open-drain analog lock detect should be oper-
ated with an external pull-up resistor of 10 kΩ nominal. When
lock has been detected it is high with narrow low-going pulses.
INPUT SHIFT REGISTER
The ADF4116 family digital section includes a 21-bit input shift
register, a 14-bit R counter and a˙`-bit N counter, comprising
a 5-bit A counter and a 13-bit B counter. Data is clocked into
the 21-bit shift register on each rising edge of CLK. The data is
clocked in MSB ﬁrst. Data is transferred from the shift register
to one of four latches on the rising edge of LE. The destination
latch is determined by the state of the two control bits (C2, C1)
in the shift register. These are the two LSBs DB1, DB0 as
shown in the timing diagram of Figure 1. The truth table for
these bits is shown in Table VII. Table II shows a summary
of how the latches are programmed.
Table II.C2, C1 Truth Table
Control Bits

Partno	Mfg	Dc	Qty	Available	Descript
ADF4116BRU	AD	N/a	378	avai	RF PLL Frequency Synthesizers
ADF4117BRU	ADI	N/a	10	avai	RF PLL Frequency Synthesizers
ADF4118BRU	AD	N/a	801	avai	RF PLL Frequency Synthesizers