ADF4110BCP-ADF4110BRU-ADF4111BRU-ADF4112BRU-ADF4113BCP-ADF4113BRU Fast Delivery |IC PHOENIX CO.,LIMITED

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ADF4110BCP-ADF4110BRU-ADF4111BRU-ADF4112BRU-ADF4113BCP-ADF4113BRU
RF PLL Frequency Synthesizers
REV.0
RF PLL Frequency Synthesizers
FEATURES
ADF4110:550 MHz
ADF4111:1.2 GHz
ADF4112:3.0 GHz
ADF4113:4.0 GHz
2.7 V to 5.5 V Power Supply
Separate Charge Pump Supply (VP) Allows Extended
Tuning Voltage in 3 V Systems
Programmable Dual Modulus Prescaler 8/9, 16/17,
32/33, 64/65
Programmable Charge Pump Currents
Programmable Antibacklash Pulsewidth
3-Wire Serial Interface
Analog and Digital Lock Detect
Hardware and Software Power-Down Mode
APPLICATIONS
Base Stations for Wireless Radio (GSM, PCS, DCS,
CDMA, WCDMA)
Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA)
Wireless LANS
Communications Test Equipment
CATV Equipment
GENERAL DESCRIPTION
The ADF4110 family of frequency synthesizers can be used
to implement local oscillators in the upconversion and down-
conversion sections of wireless receivers and transmitters. They
consist of a low-noise digital PFD (Phase Frequency Detector),
a precision charge pump, a programmable reference divider,
programmable A and B counters and a dual-modulus prescaler
(P/P+1). The A (6-bit) and B (13-bit) counters, in conjunction
with the dual modulus prescaler (P/P+1), implement an N
divider (N = BP + A). In addition, the 14-bit reference counter
(R Counter), allows selectable REFIN frequencies at the PFD
input. A complete PLL (Phase-Locked Loop) can be imple-
mented if the synthesizer is used with an external loop ﬁlter and
VCO (Voltage Controlled Oscillator).
Control of all the on-chip registers is via a simple 3-wire interface.
The devices operate with a power supply ranging from 2.7 V to
5.5 V and can be powered down when not in use.
FUNCTIONAL BLOCK DIAGRAM
REFERENCEM2M1
HIGH ZMUXOUT
AVDD
SDOUT
SDOUT
FROM
FUNCTION
DGNDAGNDCE
RFINB
RFINA
DATA
CLK
REFIN
CPGNDVPDVDDAVDD
ADF4110/ADF4111
ADF4112/ADF4113
RSET
CPI3CPI2CPI1CPI6CPI5CPI4
ADF4110/ADF4111/ADF4112/ADF4113–SPECIFICATIONS1
(AVDD = DVDD = 3 V � 10%, 5 V � 10%; AVDD ≤ VP ≤ 6.0 V; AGND = DGND = CPGND = 0 V; RSET = 4.7 k�; TA = TMIN to TMAX unless otherwise noted)
ADF4110/ADF4111/ADF4112/ADF4113
NOTES
1Operating temperature range is as follows: B Version: –40°C to +85°C.
2The B Chip specifications are given as typical values.
3This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency
which is less than this value.
4AVDD = DVDD = 3 V; For AVDD = DVDD = 5 V, use CMOS-compatible levels.
5Guaranteed by design.
6TA = 25°C; AVDD = DVDD = 3 V; P = 16; SYNC = 0; DLY = 0; RFIN for ADF4110 = 540 MHz; RFIN for ADF4111, ADF4112, ADF4113 = 900 MHz.
7The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 logN (where N is the N divider value).The phase noise is measured with the EVAL-ADF411XEB1 Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for
the synthesizer (fREFOUT = 10 MHz @ 0 dBm). SYNC = 0; DLY = 0 (See Table III).fREFIN = 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; fRF = 540 MHz; N = 2700; Loop B/W = 20 kHz.fREFIN = 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; fRF = 900 MHz; N = 4500; Loop B/W = 20 kHz.fREFIN = 10 MHz; fPFD = 30 kHz; Offset frequency = 300 Hz; fRF = 836 MHz; N = 27867; Loop B/W = 3 kHz.
12fREFIN = 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; fRF = 1750 MHz; N = 8750; Loop B/W = 20 kHz.fREFIN = 10 MHz; fPFD = 10 kHz; Offset frequency = 200 Hz; fRF = 1750 MHz; N = 175000; Loop B/W = 1 kHz.
14fREFIN = 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; fRF = 1960 MHz; N = 9800; Loop B/W = 20 kHz.fREFIN = 10 MHz; fPFD = 1 MHz; Offset frequency = 1 kHz; fRF = 3100 MHz; N = 3100; Loop B/W = 20 kHz.
Specifications subject to change without notice.
TIMING CHARACTERISTICS1
NOTES
1Guaranteed by design but not production tested.
Speciﬁcations subject to change without notice.
(AVDD = DVDD = 3 V � 10%, 5 V � 10%; AVDD ≤ VP ≤ 6.0 V; AGND = DGND = CPGND = 0 V;
RSET = 4.7 k�; TA = TMIN to TMAX unless otherwise noted)
ADF4110/ADF4111/ADF4112/ADF4113
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily accumu-
late on the human body and test equipment and can discharge without detection. Although the
ADF4110/ADF4111/ADF4112/ADF4113 features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS1, 2
(TA = 25°C unless otherwise noted)
AVDD to GND3 . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
VP to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
VP to AVDD . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.5 V
Digital I/O Voltage to GND . . . . . . . . –0.3 V to VDD + 0.3 V
Analog I/O Voltage to GND . . . . . . . . . –0.3 V to VP + 0.3 V
REFIN, RFINA, RFINB to GND . . . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C
TSSOP θJA Thermal Impedance . . . . . . . . . . . . . 150.4°C/W
CSP θJA Thermal Impedance (Paddle Soldered) . . . 122°C/W
CSP θJA Thermal Impedance
(Paddle Not Soldered) . . . . . . . . . . . . . . . . . . . . . 216°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this speciﬁcation is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.This device is a high-performance RF integrated circuit with an ESD rating of
< 2 kV and it is ESD sensitive. Proper precautions should be taken for handling
and assembly.GND = AGND = DGND = 0 V.
TRANSISTOR COUNT
6425 (CMOS) and 303 (Bipolar).
ORDERING GUIDE
Figure 1.Timing Diagram
PIN FUNCTION DESCRIPTIONS
PIN CONFIGURATIONS
TSSOP
CHIP SCALE PACKAGE
CPGND
AGND
AGND
RFINB
RFINA
MUXOUT
DATA
CLKR
SET
REF
DGNDDGND
ADF4110/ADF4111/ADF4112/ADF4113
–Typical Performance Characteristics
Figure 2.S-Parameter Data for the ADF4113 RF Input (Up
to 1.8 GHz)

Figure 3.Input Sensitivity (ADF4113)

Figure 4.ADF4113 Phase Noise (900 MHz, 200 kHz, 20 kHz)

Figure 5.ADF4113 Phase Noise (900 MHz, 200 kHz,
20 kHz) with DLY and SYNC Enabled
10dB/DIVISIONRL = –40dBc/HzRMS NOISE = 0.52�
100HzFREQUENCY OFFSET FROM 900MHz CARRIER1MHz
PHASE NOISE
dBc/Hz
–140
Figure 6.ADF4113 Integrated Phase Noise (900 MHz,
200 kHz, 20 kHz, Typical Lock Time: 400 µs)
10dB/DIVISIONRL = –40dBc/HzRMS NOISE = 0.62�
100HzFREQUENCY OFFSET FROM 900MHz CARRIER1MHz
PHASE NOISE
dBc/Hz
–140
Figure 7.ADF4113 Integrated Phase Noise (900 MHz,
200 kHz, 35 kHz, Typical Lock Time: 200 µs)
Figure 8.ADF4113 Reference Spurs (900 MHz, 200 kHz,
20 kHz)
Figure 9.ADF4113 Reference Spurs (900 MHz, 200 kHz,
35 kHz)
Figure 10.ADF4113 Phase Noise (1750 MHz, 30 kHz,
3 kHz)
Figure 11.ADF4113 Integrated Phase Noise (1750 MHz,
30 kHz, 3 kHz)
Figure 12.ADF4113 Reference Spurs (1750 MHz, 30 kHz,
3 kHz)
Figure 13.ADF4113 Phase Noise (3100 MHz, 1 MHz,
100 kHz)
ADF4110/ADF4111/ADF4112/ADF4113
10dB/DIVISIONRL = –40dBc/HzRMS NOISE = 1.7�
100HzFREQUENCY OFFSET FROM 3100MHz CARRIER1MHz
PHASE NOISE
dBc/Hz
–140
Figure 14.ADF4113 Integrated Phase Noise (3100 MHz,
1 MHz, 100 kHz)
Figure 15.ADF4113 Reference Spurs (3100 MHz, 1 MHz,
100 kHz)
Figure 16.ADF4113 Phase Noise (Referred to CP Output)
vs. PFD Frequency
TEMPERATURE – �C
PHASE NOISE
dBc/Hz
–20
Figure 17.ADF4113 Phase Noise vs. Temperature
(900 MHz, 200 kHz, 20 kHz)
TEMPERATURE – �C
FIRST REFERENCE SPUR
dBc–70
–20
Figure 18.ADF4113 Reference Spurs vs. Temperature
(900 MHz, 200 kHz, 20 kHz)
TUNING VOLTAGE – Volts0234–105
FIRST REFERENCE SPUR
dBc
–25
Figure 19.ADF4113 Reference Spurs (200 kHz) vs.
VTUNE (900 MHz, 200 kHz, 20 kHz)
TEMPERATURE – �C
PHASE NOISE
dBc/Hz
–20
Figure 20.ADF4113 Phase Noise vs. Temperature
(836 MHz, 30 kHz, 3 kHz)
TEMPERATURE – �C
FIRST REFERENCE SPUR
dBc–70
–20
Figure 21.ADF4113 Reference Spurs vs. Temperature
(836 MHz, 30 kHz, 3 kHz)
Figure 22.AIDD vs. Prescaler Value
PRESCALER OUTPUT FREQUENCY – MHz
mA
10050
Figure 23.DIDD vs. Prescaler Output Frequency
(ADF4110, ADF4111, ADF4112, ADF4113)
ADF4110/ADF4111/ADF4112/ADF4113
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 24. SW1 and SW2
are normally-closed switches. SW3 is normally-open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REFIN pin
on power-down.
Figure 24.Reference Input Stage
RF INPUT STAGE
The RF input stage is shown in Figure 25. It is followed by a
2-stage limiting ampliﬁer to generate the CML (Current Mode
Logic) clock levels needed for the prescaler.
Figure 25.RF Input Stage
PRESCALER (P/P+1)
The dual-modulus prescaler (P/P+1), along with the A and B
counters, enables the large division ratio, N, to be realized
(N = BP + A). The dual-modulus prescaler, operating at CML
levels, takes the clock from the RF input stage and divides it
down to a manageable frequency for the CMOS A and B counters.
The prescaler is programmable. It can be set in software to 8/9,
16/17, 32/33, or 64/65. It is based on a synchronous 4/5 core.
A AND B COUNTERS
The A and B CMOS counters combine with the dual modulus
prescaler to allow a wide ranging division ratio in the PLL feed-
back counter. The counters are specified to work when the
prescaler output is 200 MHz or less. Thus, with an RF input
frequency of 2.5 GHz, a prescaler value of 16/17 is valid but a
value of 8/9 is not valid.
Pulse Swallow Function
The A and B counters, in conjunction with the dual modulus
prescaler, make it possible to generate output frequencies that
are spaced only by the Reference Frequency divided by R. The
equation for the VCO frequency is as follows:
fVCO = [(P × B) + A] × fREFIN/R
fVCOOutput frequency of external voltage controlled oscilla-
tor (VCO).Preset modulus of dual modulus prescalerPreset Divide Ratio of binary 13-bit counter (3 to 8191).Preset Divide Ratio of binary 6-bit swallow counter (0 to
63).
fREFINOutput frequency of the external reference frequency
oscillator.Preset divide ratio of binary 14-bit programmable refer-
ence counter (1 to 16383).
R COUNTER
The 14-bit R counter allows the input reference frequency to be
divided down to produce the reference clock to the phase fre-
quency detector (PFD). Division ratios from 1 to 16,383 are
allowed.
Figure 26.A and B Counters
PHASE FREQUENCY DETECTOR (PFD) AND CHARGE
PUMP
The PFD takes inputs from the R counter and N counter
(N = BP + A) and produces an output proportional to the phase
and frequency difference between them. Figure 27 is a simpli-
ﬁed schematic. The PFD includes a programmable delay element
which controls the width of the antibacklash pulse. This pulse
ensures that there is no dead zone in the PFD transfer function
and minimizes phase noise and reference spurs. Two bits in the
Reference Counter Latch, ABP2 and ABP1 control the width
of the pulse. See Table III.
HIR DIVIDER
N DIVIDER
CP OUTPUT
CPGND
Figure 27.PFD Simpliﬁed Schematic and Timing
(In Lock)
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4110 family allows the
user to access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2 and M1 in the function
latch. Table V shows the full truth table. Figure 28 shows the
MUXOUT section in block diagram form.
Lock Detect
MUXOUT can be programmed for two types of lock detect:
digital lock detect and analog lock detect.
Digital lock detect is active high. When LDP in the R counter
latch is set to 0, digital lock detect is set high when the phase
error on three consecutive Phase Detector cycles is less than 15 ns.
With LDP set to 1, five consecutive cycles of less than 15 ns
are required to set the lock detect. It will stay set high until a
phase error of greater than 25 ns is detected on any subsequent
PD cycle.
The N-channel open-drain analog lock detect should be oper-
ated with an external pull-up resistor of 10 kΩ nominal. When
lock has been detected this output will be high with narrow low-
going pulses.
DVDD
MUXOUT
DGND
ANALOG LOCK DETECT
DIGITAL LOCK DETECT
R COUNTER OUTPUT
N COUNTER OUTPUT
SDOUT
Figure 28.MUXOUT Circuit
INPUT SHIFT REGISTER
The ADF4110 family digital section includes a 24-bit input shift
register, a 14-bit R counter and a 19-bit N counter, comprising
a 6-bit A counter and a 13-bit B counter. Data is clocked into
the 24-bit shift register on each rising edge of CLK. The data is
clocked in MSB ﬁrst. Data is transferred from the shift register
to one of four latches on the rising edge of LE. The destination
latch is determined by the state of the two control bits (C2, C1)
in the shift register. These are the two LSBs DB1, DB0 as
shown in the timing diagram of Figure 1. The truth table for
these bits is shown in Table VI. Table I shows a summary of
how the latches are programmed.
Table I.C2, C1 Truth Table
ADF4110/ADF4111/ADF4112/ADF4113
Table II.ADF4110 Family Latch Summary

Partno	Mfg	Dc	Qty	Available	Descript
ADF4110BCP	ADI	N/a	2	avai	RF PLL Frequency Synthesizers
ADF4110BRU	AD	N/a	50	avai	RF PLL Frequency Synthesizers
ADF4111BRU	AD	N/a	72	avai	RF PLL Frequency Synthesizers
ADF4112BRU	AD	N/a	500	avai	RF PLL Frequency Synthesizers
ADF4113BCP	ADI	N/a	1	avai	RF PLL Frequency Synthesizers
ADF4113BRU	ANALOG	N/a	115	avai	RF PLL Frequency Synthesizers