ADF4107BCP Fast Delivery |IC PHOENIX CO.,LIMITED

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ADF4107BCP
PLL Frequency Synthesizer
PLL Frequency SynthesizerFEATURES
7.0 GHz bandwidth
2.7 V to 3.3 V power supply
Separate charge pump supply (VP) allows extended tuning
voltage in 3 V systems
Programmable dual-modulus prescaler
8/9, 16/17, 32/33, 64/65
Programmable charge pump currents
Programmable antibacklash pulsewidth
3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode
APPLICATIONS
Broadband wireless access
Satellite systems
Instrumentation
Wireless LANs
Base stations for wireless radio
GENERAL DESCRIPTION
The ADF4107 frequency synthesizer can be used to implement
local oscillators in the up-conversion and down-conversion
sections of wireless receivers and transmitters. It consists of a
low-noise digital PFD (phase frequency detector), a precision
charge pump, a programmable reference divider, programmable
A and B counters, and a dual-modulus prescaler (P/P + 1). The
A (6-bit) and B (13-bit) counters, in conjunction with the dual-
modulus prescaler (P/P + 1), implement an N divider
(N = BP + A). In addition, the 14-bit reference counter
(R counter), allows selectable REFIN frequencies at the PFD
input. A complete PLL (phase-locked loop) can be implemented
if the synthesizer is used with an external loop filter and VCO
(voltage controlled oscillator). Its very high bandwidth means
that frequency doublers can be eliminated in many high
frequency systems, simplifying system architecture and
reducing cost.
FUNCTIONAL BLOCK DIAGRAM
CLK
DATA
REFIN
RFINA
RFINB
AVDDDVDDAGNDDGND
MUXOUT
CPGNDRSETVP
Figure 1.
Rev. 0
TABLE OF CONTENTS
ADF4107—Specifications................................................................3
Timing Characteristics.....................................................................5
Absolute Maximum Ratings............................................................5
Pin Configurations and Functional Descriptions........................6
Typical Performance Characteristics.............................................7
Functional Description....................................................................9
Reference Input Stage...................................................................9
RF Input Stage...............................................................................9
Prescaler (P/P + 1)........................................................................9
A and B Counters.........................................................................9
R Counter......................................................................................9
Phase Frequency Detector and Charge Pump........................10
MUXOUT and Lock Detect......................................................10
Input Shift Register.....................................................................10
Latch Summary...........................................................................11
Reference Counter Latch Map..................................................12
AB Counter Latch Map.............................................................13
Function Latch Map...................................................................14
Initialization Latch Map............................................................15
Function Latch............................................................................16
Initialization Latch.....................................................................17
Applications.....................................................................................18
Local Oscillator for LMDS Base Station Transmitter............18
Interfacing...................................................................................19
PCB Design Guidelines for Chip Scale Package....................19
Outline Dimensions.......................................................................20
ESD Caution....................................................................................20
Ordering Guide...............................................................................20
REVISION HISTORY
Revision 0: Initial Version
ADF4107—SPECIFICATIONS
Table 1. (AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω, TA =
TMAX to TMIN, unless otherwise noted.)
Operating temperature range (B Version) is –40°C to +85°C. 2 The B Chip specifications are given as typical values. Use a square wave for lower frequencies, below the minimum stated.
4 This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that
is less than this value.
5 AVDD = DVDD = 3 V. Guaranteed by design. Sample tested to ensure compliance.
7 TA = 25°C; AVDD = DVDD = 3 V; P = 32; RFIN = 7.0 GHz. TA = 25°C; AVDD = DVDD = 3.3 V; R = 16383; A = 63; B = 891; P = 32; RFIN = 7.0 GHz.
9 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value). The phase noise is measured with the EVAL-ADF4107EB1 Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for the
synthesizer (fREFOUT = 10 MHz @ 0 dBm). fREFIN = 10 MHz; fPFD = 200 kHz; Offset Frequency = 1 kHz; fRF = 900 MHz; N = 4500; Loop B/W = 20 kHz.
12 fREFIN = 10 MHz; fPFD = 200 kHz; Offset Frequency = 1 kHz; fRF = 6400 MHz; N = 32000; Loop B/W = 20 kHz. fREFIN = 10 MHz; fPFD = 1 MHz; Offset Frequency = 1 kHz; fRF = 6400 MHz; N = 6400; Loop B/W = 100 kHz.
TIMING CHARACTERISTICS
Table 2. (AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω,
TA = TMAX to TMIN, unless otherwise noted.) 1 Guaranteed by design but not production tested.
2 Operating temperature range (B Version) is –40°C to +85°C.
CLOCKDATA
Figure 2. Timing Diagram
ABSOLUTE MAXIMUM RATINGS
Table 3. (TA = 25°C, unless otherwise noted.)
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
This device is a high performance RF integrated circuit with an
ESD rating of <2 kV, and it is ESD sensitive. Proper precautions
should be taken for handling and assembly. GND = AGND = DGND = 0 V.
PIN CONFIGURATIONS AND FUNCTIONAL DESCRIPTIONS
RSET
CPGND
AGND
DATA
CLK
DGND
RFINB
RFINA
AVDD
REFIN
DVDD
Figure 3. ADF4107 TSSOP (Top View)
15 MUXOUTLE
13 DATA
12 CLK
CPGND 1
AGND 2
AGND 3
20 C
11 CE
6 7 8
ND 9
ND 1181716
RFINB
RFINA
SET
PIN 1INDICATOR
TOP VIEW
ADF4107
REF
CSP
(Chip Scale Package)
Figure 4. ADF4107 Chip Scale Package
Table 4. Pin Functional Descriptions
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 5. Parameter Data for the RF Input
RF INPUT FREQUENCY– GHz
INPUT
POWER
Figure 6. Input Sensitivity
FREQUENCY
OUTPUT POWER
dB
Figure 7. Phase Noise (900 MHz, 200 kHz, 20 kHz)
100Hz
FREQUENCY OFFSET FROM 900MHz CARRIER
HAS
NOIS
dBc/Hz
Figure 8. Integrated Phase Noise (900 MHz, 200 kHz, 20 kHz)
OUTPUT POWER
dB
FREQUENCY
Figure 9. Reference Spurs (900 MHz, 200 kHz, 20 kHz)
OUTPUT POWER
dB
FREQUENCY
Figure 10. Phase Noise (6.4 GHz, 1 MHz, 100 kHz)
FREQUENCY OFFSET FROM 6400MHz CARRIER
HAS
NOIS
dBc/Hz
Figure 11. Integrated Phase Noise (6.4 GHz, 1 MHz, 100 kHz)
OUTP
UT P
dB
FREQUENCY
Figure 12. Reference Spurs (6.4 GHz, 1 MHz, 100 kHz)
TEMPERATURE–oC
HAS
NOIS
dBc/Hz
Figure 13. Phase Noise (6.4 GHz, 1 MHz, 100 kHz) vs. Temperature
TUNING VOLTAGE– V
FIRS
T RE
NCE
dBc
–95
Figure 14. Reference Spurs vs. VTUNE (6.4 GHz, 1 MHz, 100 kHz)
–18010k100M100k1M10M
PHASE DETECTOR FREQUENCY– Hz
HAS
NOIS
dBc/Hz
Figure 15. Phase Noise (referred to CP output) vs. PFD Frequency 2.00.51.01.5
VCP– V
– mA
4.02.53.03.55.04.5
Figure 16. Charge Pump Output Characteristics
FUNCTIONAL DESCRIPTION
Reference Input Stage
The Reference Input stage is shown in Figure 17. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REFIN pin
on power-down.
POWER-DOWN
CONTROL
Figure 17. Reference Input Stage
RF Input Stage
The RF input stage is shown in Figure 18. It is followed by a
2-stage limiting amplifier to generate the CML clock levels
needed for the prescaler.
AGND
RFINA
RFINB
Figure 18. RF Input Stage
Prescaler (P/P + 1)
The dual-modulus prescaler (P/P + 1), along with the A and B
counters, enables the large division ratio, N, to be realized
(N = BP + A). The dual-modulus prescaler, operating at CML
levels, takes the clock from the RF input stage and divides it
down to a manageable frequency for the CMOS A and B
synchronous 4/5 core. A minimum divide ratio is possible for
fully contiguous output frequencies. This minimum is
determined by P, the prescaler value, and is given by: (P2 – P).
A and B Counters
The A and B CMOS counters combine with the dual-modulus
prescaler to allow a wide ranging division ratio in the PLL
feedback counter. The counters are specified to work when the
prescaler output is 300 MHz or less. Thus, with an RF input
frequency of 4.0 GHz, a prescaler value of 16/17 is valid but a
value of 8/9 is not valid.
Pulse Swallow Function
The A and B counters, in conjunction with the dual-modulus
prescaler, make it possible to generate output frequencies that
are spaced only by the reference frequency divided by R. The
equation for the VCO frequency is as follows: ()[]ABPfREFINVCO×+×=
fVCO Output frequency of external voltage controlled
oscillator (VCO). Preset modulus of dual-modulus prescaler
(8/9, 16/17, etc.). Preset divide ratio of binary 13-bit counter
(3 to 8191). Preset divide ratio of binary 6-bit swallow counter
(0 to 63).
fREFIN External reference frequency oscillator.
FROM RF
INPUT STAGE
TO PFD
Figure 19. A and B Counters
R Counter
The 14-bit R counter allows the input reference frequency to be
divided down to produce the reference clock to the phase
frequency detector (PFD). Division ratios from 1 to 16,383 are
Phase Frequency Detector and Charge
Pump
The phase frequency detector (PFD) takes inputs from the R
counter and N counter (N = BP + A) and produces an output
proportional to the phase and frequency difference between
them. Figure 20 is a simplified schematic. The PFD includes a
programmable delay element that controls the width of the
antibacklash pulse. This pulse ensures that there is no dead zone
in the PFD transfer function and minimizes phase noise and
reference spurs. Two bits in the reference counter latch, ABP2
and ABP1, control the width of the pulse. See Figure 23.
CPGND
Figure 20. PFD Simplified Schematic and Timing (in Lock)
MUXOUT and Lock Detect
The output multiplexer on the ADF4107 allows the user to
access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2, and M1 in the function
latch. Figure 25 shows the full truth table. Figure 21 shows the
MUXOUT section in block diagram form.
Lock Detect
MUXOUT can be programmed for two types of lock detect:
digital lock detect and analog lock detect.
Digital lock detect is active high. When the lock detect precision
(LDP) bit in the R counter latch is set to 0, digital lock detect is
set high when the phase error on three consecutive phase
detector (PD) cycles is less than 15 ns. With LDP set to 1, five
consecutive cycles of less than 15 ns are required to set the lock
detect. It will stay set high until a phase error of greater than
25 ns is detected on any subsequent PD cycle.
The N-channel open-drain analog lock detect should be
operated with an external pull-up resistor of 10 kΩ nominal.
When lock has been detected, this output will be high with
narrow, low-going pulses.
DGND
DVDD
ANALOG LOCK DETECT
DIGITAL LOCK DETECT
R COUNTER OUTPUT
N COUNTER OUTPUT
SDOUT
MUXOUT
Figure 21. MUXOUT Circuit
Input Shift Register
The ADF4107 digital section includes a 24-bit input shift
register, a 14-bit R counter, and a 19-bit N counter, comprising a
6-bit A counter and a 13-bit B counter. Data is clocked into the
24-bit shift register on each rising edge of CLK. The data is
clocked in MSB first. Data is transferred from the shift register
to one of four latches on the rising edge of LE. The destination
latch is determined by the state of the two control bits (C2, C1)
in the shift register. These are the two LSBs, DB1 and DB0, as
shown in the timing diagram of Figure 2. The truth table for
these bits is shown in Table 5. Figure 22 shows a summary of
how the latches are programmed.
Table 5. C2, C1 Truth Table
Control Bits Data Latch

Partno	Mfg	Dc	Qty	Available	Descript
ADF4107BCP	AD	N/a	1	avai	PLL Frequency Synthesizer