ADF4106 Fast Delivery |IC PHOENIX CO.,LIMITED

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ADF4106
PLL Frequency Synthesizer
REV.0
PLL Frequency Synthesizer
FEATURES
6.0 GHz Bandwidth
2.7 V to 3.3 V Power Supply
Separate Charge Pump Supply (VP) Allows Extended
Tuning Voltage in 3 V Systems
Programmable Dual Modulus Prescaler
8/9, 16/17, 32/33, 64/65
Programmable Charge Pump Currents
Programmable Anti-Backlash Pulsewidth
3-Wire Serial Interface
Analog and Digital Lock Detect
Hardware and Software Power-Down Mode
APPLICATIONS
Broadband Wireless Access
Instrumentation
Wireless LANS
Base Stations For Wireless Radio
FUNCTIONAL BLOCK DIAGRAM
REFIN
CLK
DATA
AVDDDVDDCPGNDRSET
MUXOUT
RFINA
RFINBAGNDDGND
GENERAL DESCRIPTION
The ADF4106 frequency synthesizer can be used to implement
local oscillators in the up-conversion and down-conversion
sections of wireless receivers and transmitters. It consists of a
low-noise digital PFD (Phase Frequency Detector), a precision
charge pump, a programmable reference divider, programmable
A and B counters and a dual-modulus prescaler (P/P+ 1). The
A (6-bit) and B (13-bit) counters, in conjunction with the dual
modulus prescaler (P/P+ 1), implement an N divider (N= BP+ A).
In addition, the 14-bit reference counter (R Counter), allows
selectable REFIN frequencies at the PFD input. A complete
PLL (Phase-Locked Loop) can be implemented if the synthe-
sizer is used with an external loop filter and VCO (Voltage
Controlled Oscillator). Its very high bandwidth means that
frequency doublers can be eliminated in many high-frequency
systems, simplifying system architecture and lowering cost.
ADF4106–SPECIFICATIONS1
RF CHARACTERISTICS
REFIN CHARACTERISTICS
PHASE DETECTOR
CHARGE PUMP
LOGIC INPUTS
(AVDD = DVDD = 3 V � 10%; AVDD ≤ VP ≤ 5.5 V; AGND = DGND = CPGND = 0 V;
RSET = 5.1 k�; dBm referred to 50 �; TA = TMIN to TMAX unless otherwise noted.)
NOISE CHARACTERISTICS
NOTES
1Operating temperature range (B Version) is –40°C to +85°C.
2The BChip specifications are given as typical values.
3Use a square wave for lower frequencies, below the mimimum stated.
4This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency
that is less than this value.
5AVDD = DVDD = 3 V
6Guaranteed by design. Sample tested to ensure compliance.
7TA = 25°C; AVDD = DVDD = 3 V; P = 16; RFIN = 6.0 GHz
8TA = 25°C; AVDD = DVDD = 3.3 V; R = 16383; A = 63; B = 891; P = 32; RFIN = 6.0 GHz
9The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value).The phase noise is measured with the EVAL-ADF4106EB1 Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for
the synthesizer (fREFOUT = 10 MHz @ 0 dBm).fREFIN = 10 MHz; fPFD = 200 kHz; Offset Frequency = 1 kHz; fRF = 900 MHz; N = 4500; Loop B/W = 20 kHzfREFIN = 10 MHz; fPFD = 200 kHz; Offset Frequency = 1 kHz; fRF = 5800 MHz; N = 29000; Loop B/W = 20 kHzfREFIN = 10 MHz; fPFD = 1 MHz; Offset Frequency = 1 kHz; fRF = 5800 MHz; N = 5800; Loop B/W = 100 kHz
Specifications subject to change without notice.
(AVDD = DVDD = 3 V � 10%; AVDD ≤ VP ≤ 5.5 V; AGND = DGND = CPGND = 0 V; RSET = 5.1 k�;
TA = TMIN to TMAX unless otherwise noted.)
TIMING CHARACTERISTICS
Guaranteed by design but not production tested.
ADF4106
ADF4106
ABSOLUTE MAXIMUM RATINGS1, 2
(TA = 25°C unless otherwise noted.)
AVDD to GND3 . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +3.6 V
AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
VP to GND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.3 V
VP to AVDD . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.5 V
Digital I/O Voltage to GND . . . . . . . . –0.3 V to VDD + 0.3 V
Analog I/O Voltage to GND . . . . . . . . . –0.3 V to VP + 0.3 V
REFIN, RFINA, RFINB to GND . . . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C
TSSOP �JA Thermal Impedance . . . . . . . . . . . . . 150.4°C/W
CSP �JA Thermal Impedance . . . . . . . . . . . . . . . . . . 122°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2This device is a high-performance RF integrated circuit with an ESD rating ofkV and it is ESD sensitive. Proper precautions should be taken for handling and
assembly.
3GND= AGND= DGND= 0V
ORDERING GUIDE
*RU = Thin Shrink Small Outline Package (TSSOP)
CP = Chip Scale Package
Contact the factory for chip availability.
Note that aluminum bond wire should not be used with the ADF4106 die.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADF4106 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
PIN CONFIGURATIONS
PIN FUNCTION DESCRIPTIONS
RFINA
AVDD
TSSOP
Chip Scale Package
15 MUXOUT
14 LE
13 DATA
12 CLK
CPGND 1
AGND 2
AGND 3
20 CP
11 CE
6
7
REF
8
DGND 9DGND 10
RFINB 4
RFINA 5
19 R
SET
18 V
17 D
16 D
PIN 1
INDICATOR
TOP VIEW
ADF4106
NOTE: TRANSISTOR COUNT 6425 (CMOS), 303 (BIPOLAR)
ADF4106–Typical Performance Characteristics

TPC 1.S-Parameter Data for the RF Input
TPC 2.Input Sensitivity
TPC 3.Phase Noise (900MHz, 200kHz, and 20kHz)
TPC 4.Integrated Phase Noise (900 MHz,
200kHz, and 20 kHz)
TPC 5.Reference Spurs (900 MHz, 200kHz, and 20 kHz)
TPC 6.Phase Noise (5.8GHz, 1MHz, and 100kHz)
TPC 7.Integrated Phase Noise (5.8 GHz, 1 MHz, and
100 kHz)
TPC 8.Reference Spurs (5.8 GHz, 1 MHz, and 100 kHz)
TPC 9.Phase Noise (5.8 GHz, 1 MHz, and 100kHz) vs.
Temperature
TPC 10.Reference Spurs vs. VTUNE (5.8 GHz, 1MHz, and
100 kHz)
TPC 11.Phase Noise (referred to CP output) vs.
PFD Frequency
TPC 12.AIDD vs. Prescaler Value
ADF4106
TPC 13.DIDD vs. Prescaler Output Frequency
TPC 14.Charge Pump Output Characteristics
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
The Reference Input stage is shown in Figure 2. SW1 and SW2
are normally-closed switches. SW3 is normally-open. When
Powerdown is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REFIN pin
on power-down.
Figure 2.Reference Input Stage
RF INPUT STAGE
The RF input stage is shown in Figure 3. It is followed by a 2-stage
limiting amplifier to generate the CML clock levels needed for the
prescaler.
PRESCALER (P/P + 1)
The dual modulus prescaler (P/P + 1), along with the A and
B counters, enables the large division ratio, N, to be realized= BP+ A). The dual-modulus prescaler, operating at CML
levels, takes the clock from the RF input stage and divides it
down to a manageable frequency for the CMOS A and B
counters. The prescaler is programmable. It can be set in soft-
ware to 8/9, 16/17, 32/33 or 64/65. It is based on a synchronous
4/5 core. There is a minimum divide ratio possible for fully
contiguous output frequencies. This minimum is determined by
P, the prescaler value and is given by: (P2– P).
A AND B COUNTERS
The A and B CMOS counters combine with the dual modulus
prescaler to allow a wide ranging division ratio in the PLL feed-
back counter. The counters are specified to work when the
prescaler output is 300MHz or less. Thus, with an RF input
frequency of 4.0GHz, a prescaler value of 16/17 is valid but a
value of 8/9 is not valid.
Pulse Swallow Function
The A and B counters, in conjunction with the dual modulus
prescaler make it possible to generate output frequencies which
are spaced only by the Reference Frequency divided by R. The
equation for the VCO frequency is as follows:
fVCOOutput Frequency of external voltage controlled
oscillator (VCO).Preset modulus of dual modulus prescaler
(8/9, 16/17, etc.,).Preset Divide Ratio of binary 13-bit counter
(3 to 8191).Preset Divide Ratio of binary 6-bit swallow
counter (0 to 63).
fREFINExternal reference frequency oscillator.
Figure 4.A and B Counters
R COUNTER
The 14-bit R counter allows the input reference frequency to
be divided down to produce the reference clock to the phase
frequency detector (PFD). Division ratios from 1 to 16,383
are allowed.
PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP
The PFD takes inputs from the R counter and N counter (N=+ A) and produces an output proportional to the phase and
frequency difference between them. Figure 5 is a simplified
schematic. The PFD includes a programmable delay element
which controls the width of the anti-backlash pulse. This pulse
ensures that there is no deadzone in the PFD transfer function
and minimizes phase noise and reference spurs. Two bits in the
Reference Counter Latch, ABP2 and ABP1 control the width of
the pulse. See Table III.
Figure 5. PFD Simplified Schematic and Timing (In Lock)
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4110 family allows the user
to access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2, and M1 in the Function
Latch. Table V shows the full truth table. Figure 6 shows the
MUXOUT section in block diagram form.
Lock Detect
MUXOUT can be programmed for two types of lock detect:
digital lock detect and analog lock detect.
Digital lock detect is active high. When LDP in the R counter
latch is set to 0, digital lock detect is set high when the phase
error on three consecutive Phase Detector cycles is less thanns. With LDP set to “1,” five consecutive cycles of less thanns are required to set the lock detect. It will stay set high
until a phase error of greater than 25ns is detected on any sub-
sequent PD cycle.
The N-channel open-drain analog lock detect should be oper-
ated with an external pull-up resistor of 10k� nominal. When
lock has been detected this output will be high with narrow low-
going pulses.
ANALOG LOCK DETECT
MUXOUT
DIGITAL LOCK DETECT
R COUNTER OUTPUT
N COUNTER OUTPUT
SDOUT
DVDD
DGND
Figure 6.MUXOUT Circuit
INPUT SHIFT REGISTER
The ADF4110 family digital section includes a 24-bit input shift
register, a 14-bit R counter and a 19-bit N counter, comprising a
6-bit A counter and a 13-bit B counter. Data is clocked into the
24-bit shift register on each rising edge of CLK. The data is
clocked in MSB first. Data is transferred from the shift register
to one of four latches on the rising edge of LE. The destina-
tion latch is determined by the state of the two control bits
(C2, C1) in the shift register. These are the two LSBs, DB1 and
DB0, as shown in the timing diagram of Figure 1. The truth table
for these bits is shown in Table VI. Table I shows a summary
of how the latches are programmed.
Table I.C2, C1 Truth Table
ADF4106
Table II.Latch Summary

Partno	Mfg	Dc	Qty	Available	Descript
ADF4106	AD	N/a	16	avai	PLL Frequency Synthesizer