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ADF4007BCP
High Frequency Divider/PLL Frequency Synthesizer
High Frequency Divider/PLL SynthesizerRev. 0
FEATURES
7.5 GHz bandwidth
Maximum PFD frequency of 120 MHz
Divide ratios of 8, 16, 32, or 64
2.7 V to 3.3 V power supply
Separate charge pump supply (VP) allows
extended tuning voltage in 3 V systems
RSET contol of charge pump current
Hardware power-down mode
APPLICATIONS
Satellite communications
Broadband wireless access
CATV
Instrumentation
Wireless LANs
GENERAL DESCRIPTION The ADF4007 is a high frequency divider/PLL synthesizer that
can be used in a variety of communications applications. It can
operate to 7.5 GHz on the RF side and to 120 MHz at the PFD.
It consists of a low noise digital PFD (phase frequency
detector), a precision charge pump, and a divider/prescaler. The
divider/ prescaler value can be set by two external control pins
to one of four values (8, 16, 32, or 64). The reference divider is
permanently set to 2, allowing an external REFIN frequency of
up to 240 MHz.
A complete PLL (phase-locked loop) can be implemented if the
synthesizer is used with an external loop filter and a VCO
(voltage controlled oscillator). Its very high bandwidth means
that frequency doublers can be eliminated in many high
frequency systems, simplifying system architecture and
reducing cost.
FUNCTIONAL BLOCK DIAGRAM
REFIN
RFINA
RFINB
VDDN1GNDMUXOUT
CPGNDRSETVPM1Figure 1.
TABLE OF CONTENTS Specifications.....................................................................................3
Absolute Maximum Ratings............................................................4
ESD Caution..................................................................................4
Pin Configuration and Function Descriptions.............................5
Typical Performance Characteristics.............................................7
Theory of Operation........................................................................9
Reference Input Section...............................................................9
RF Input Stage...............................................................................9
Prescaler P.....................................................................................9
R Counter.......................................................................................9
Phase Frequency Detector (PFD) and Charge Pump...............9
MUXOUT...................................................................................10
Applications.....................................................................................11
Fixed High Frequency Local Oscillator...................................11
Using the ADF4007 as a Divider..............................................12
PCB Design Guidelines for Chip Scale Package.........................13
Outline Dimensions.......................................................................14
Ordering Guide..........................................................................14
REVISION HISTORY Revision 0: Initial Version
SPECIFICATIONS AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω,
TA = TMAX to TMIN, unless otherwise noted.
Table 1. Operating temperature range (B version) is −40°C to +85°C.
2 AC coupling ensures AVDD/2 bias. See for typical circuit. Figure 13 Guaranteed by design. Characterized to ensure compliance. TA = 25°C; AVDD = DVDD = 3 V; N = 64; RFIN = 7.5 GHz. The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO, PNTOT, and subtracting 20logN (where N is the N divider
value) and 10logFPFD. PNSYNTH = PNTOT − 10logFPFD − 20logN. The in-band phase noise (PNTOT) is measured using the HP8562E Spectrum Analyzer from Agilent.
ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted.
Table 2. Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
This device is a high performance RF integrated circuit with an
ESD rating of <2 kV, and it is ESD sensitive. Proper precautions
should be taken for handling and assembly.
1 GND = AGND = DGND = 0 V.
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
15MUXOUT
14M1
13M2
12N1
CPGND1
AGND2
AGND3
11N2
DGND
DGND
RFINB4
RFINA5
PIN1
INDICATOR
TOPVIEW
ADF400704537-0-002
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions Table 4. N Truth Table
Table 5. M Truth Table Active VDD+ve Three-state R divider output +ve Active N divider output +ve
TYPICAL PERFORMANCE CHARACTERISTICS
Table 6. S-Parameter Data for the RF Input 1Frequency unit: GHz; parameter type: s; data format: MA; keyword: R;
impedance: 50.
RF INPUT FREQUENCY (GHz)
RF INP
T P
R (dBm)04537-0-003
Figure 3. Input Sensitivity
FREQUENCY (Hz)
OUTPUT POWER (dB)Figure 4. Phase Noise (6.78 GHz RFOUT, 106 MHz PFD,
and 1 MHz Loop Bandwidth)
10k
FREQUENCY OFFSET FROM CARRIER (Hz)
SE N
ISE (Figure 5. Integrated Phase Noise (6.78 GHz RFOUT, 106 MHz PFD,
and 1 MHz Loop Bandwidth)
OUTP
UT P
R (dB)
FREQUENCY (MHz)Figure 6. Reference Spurs (6.78 GHz RFOUT, 106 MHz PFD,
and 1 MHz Loop Bandwidth)
–18010k120M100k1M10M
PHASE DETECTOR FREQUENCY (Hz)
SE N
ISE (Figure 7. Phase Noise (Referred to CP Output) vs. PFD Frequency
2.00.51.01.5
VCP (V)
ICP
(mA)0
4.02.53.03.55.04.5Figure 8. Charge Pump Output Characteristics
