ADF4001 Fast Delivery |IC PHOENIX CO.,LIMITED

ADF4001 ,200MHz Clock Generator PLLSpecifications subject to change without notice.t t3 4CLOCKt t1 2DB20 DB1 DB0 (LSB)DATA DB2DB19(MSB ..
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ADF4001
200MHz Clock Generator PLL
REV.0
200 MHz Clock Generator PLL
FUNCTIONAL BLOCK DIAGRAM
RFINA
RFINB
REFIN
CLK
DATA
AVDDDVDDVPCPGNDRSET
MUXOUTAGNDDGND
FEATURES
200 MHz Bandwidth
2.7 V to 5.5 V Power Supply
Separate Charge Pump Supply (VP) Allows Extended
Tuning Voltage in 5 V Systems
Programmable Charge Pump Currents
3-Wire Serial Interface
Hardware and Software Power-Down Mode
Analog and Digital Lock Detect
Hardware-Compatible to the ADF4110/ADF4111/
ADF4112/ADF4113
Typical Operating Current 4.5 mA
Ultralow Phase Noise
16-Lead TSSOP
20-Lead Chip Scale Package
APPLICATIONS
Clock Generation
Low Frequency PLLs
Low Jitter Clock Source
Clock Smoothing
Frequency Translation
SONET, ATM, ADM, DSLAM, SDM
GENERAL DESCRIPTION
The ADF4001 clock generator can be used to implement clock
sources for PLLs that require very low noise, stable refer-
ence signals. It consists of a low-noise digital PFD (Phase
Frequency Detector), a precision charge pump, a programmable
reference divider, and a programmable 13-bit N counter. In
addition, the 14-bit reference counter (R Counter) allows
selectable REFIN frequencies at the PFD input. A complete
PLL (Phase-Locked Loop) can be implemented if the synthesizer
is used with an external loop filter and VCO (Voltage Controlled
Oscillator) or VCXO (Voltage Controlled Crystal Oscillator).
The N min value of 1 allows flexibility in clock generation.
ADF4001–SPECIFICATIONS1
(AVDD = DVDD = 3 V � 10%, 5 V � 10%; AVDD ≤ VP ≤ 6.0 V ; AGND = DGND =
CPGND = 0 V; RSET = 4.7 k�; TA = TMIN to TMAX unless otherwise noted; dBm referred to 50 �)
NOTES
1Operating temperature range is as follows: B Version: –40°C to +85°C.AVDD = DVDD = 3 V; for AVDD = DVDD = 5 V, use CMOS-compatible levels.
3Guaranteed by design. Sample tested to ensure compliance.TA = 25°C; AVDD = DVDD = 3 V; RFIN = 100 MHz.
(AVDD = DVDD = 3 V � 10%, 5 V � 10%; AVDD ≤ VP ≤ 6.0 V ; AGND = DGND = CPGND= 0 V; RSET =
4.7 k�; TA = TMIN to TMAX unless otherwise noted; dBm referred to 50 �.)
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
Figure 1.Timing Diagram
TIMING CHARACTERISTICS
NOTES
Guaranteed by design but not production tested.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS1, 2
(TA = 25°C unless otherwise noted)
AVDD to GND3 . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to + 0.3 V
VP to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
VP to AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.5 V
Digital I/O Voltage to GND . . . . . . . . . –0.3 V to VDD + 0.3 V
Analog I/O Voltage to GND . . . . . . . . . . –0.3 V to VP + 0.3 V
REFIN, RFINA, RFINB to GND . . . . . . .–0.3 V to VDD + 0.3 V
RFINA to RFINB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±320 mV
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . . .150°C
TSSOP θJA Thermal Impedance . . . . . . . . . . . . . . 150.4°C/W
CSP θJA Thermal Impedance (Paddle Soldered) . . . . 122°C/W
CSP θJA Thermal Impedance (Paddle Not Soldered) . . 216°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.This device is a high-performance RF integrated circuit with an ESD rating of
< 2 kΩ and it is ESD sensitive. Proper precautions should be taken for handling
and assembly.GND = AGND = DGND = 0 V.
ORDERING GUIDE
*Contact factory for chip availability.
ADF4001
PIN FUNCTION DESCRIPTIONS
PIN CONFIGURATIONS
TRANSISTOR COUNT
6425 (CMOS) and 50 (Bipolar).
RSET
MUXOUT
DVDD
CPGND
AGND
CLK
DATARFINB
RFINA
AVDD
REFINDGND
15 MUXOUT
14 LE
13 DATA
12 CLK
CPGND 1
AGND 2
AGND 3
20 CP
11 CE
6
7
REF
8
DGND 9DGND 10
RFINB 4
RFINA 5
19 R
SET
18 V
17 D
16 D
PIN 1
INDICATOR
TOP VIEW
ADF4001
TPC 1.Input Sensitivity. VDD = 3.3 V; 100 pF on RFIN
TPC 2.Input Sensitivity. VDD = 3.3 V; 100 pF on RFIN
TPC 3.Phase Noise (200 MHz, 200 kHz, 20 kHz)
FREQUENCY OFFSET FROM 200MHz CARRIER – Hz
PHASE NOISE
dBc/Hz
–14010k100k1M
10dB/DIVISIONRL = –40dBc/Hzrms NOISE = 0.229 DEGREES
TPC 4.Integrated Phase Noise (200 MHz, 200 kHz, 20 kHz)
TPC 5.Reference Spurs (200 MHz, 200 kHz, 20 kHz)
ADF4001
CIRCUIT DESCRIPTION
Reference Input Section
The reference input stage is shown in Figure 2. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REFIN pin
on power-down.
Figure 2.Reference Input Stage
RF Input Stage
The RF input stage is shown in Figure 3. It is followed by a
two-stage limiting amplifier to generate the CML clock levels
needed for the N Counter buffer.

Figure 3.RF Input Stage
N Counter
The N CMOS counter allows a wide ranging division ratio
in the PLL feedback counter. Division ratios of 1 to 8191
are allowed.
N and R Relationship
The N counter, in conjunction with the R Counter make it
possible to generate output frequencies that are spaced only by
the Reference Frequency divided by R. The equation for the
VCO frequency is as follows:
fVCO = N/R × fREFIN
fVCOOutput Frequency of external voltage-controlled oscil-
lator (VCO).Preset Divide Ratio of binary 13-bit counter (1 to 8,191).

Figure 4.N Counter
R Counter
The 14-bit R counter allows the input reference frequency to be
divided down to produce the reference clock to the phase frequency
detector (PFD). Division ratios from 1 to 16,383 are allowed.
PHASE FREQUENCY DETECTOR (PFD) AND CHARGE
PUMP
The PFD takes inputs from the R counter and N counter and
produces an output proportional to the phase and frequency
difference between them. Figure 5 is a simplified schematic. The
PFD includes a programmable delay element which controls the
width of the antibacklash pulse. This pulse ensures that there is
no deadzone in the PFD transfer function and minimizes phase
noise and reference spurs. Two bits in the Reference Counter
Latch, ABP2 and ABP1 control the width of the pulse. See
Table III.
Figure 5.PFD Simplified Schematic and Timing (In Lock)
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4110 family allows the
user to access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2, and M1 in the Function
Latch. Table V shows the full truth table. Figure 6 shows the
ANALOG LOCK DETECT
DIGITAL LOCK DETECT
R COUNTER OUTPUT
N COUNTER OUTPUT
SDOUT
DGND
DVDDMUXOUT
Figure 6.MUXOUT Circuit
Lock Detect
MUXOUT can be programmed for two types of lock detect:
digital lock detect and analog lock detect. Digital lock detect is
active high. When LDP in the R counter latch is set to “0,” digital
lock detect is set high when the phase error on three consecutive
Phase Detector cycles is less than 15 ns. With LDP set to “1,” five
consecutive cycles of less than 15 ns are required to set the lock
detect. It will stay set high until a phase error of greater than
25 ns is detected on any subsequent PD cycle. The N-channel
open-drain analog lock detect should be operated with an external
pull-up resistor of 10 kΩ nominal. When lock has been detected,
this output will be high with narrow low-going pulses.
INPUT SHIFT REGISTER
The ADF4001 digital section includes a 24-bit input shift regis-
ter, a 14-bit R counter, and a 13-bit N counter. Data is clocked
into the 24-bit shift register on each rising edge of CLK. The
data is clocked in MSB first. Data is transferred from the shift
register to one of four latches on the rising edge of LE. The
destination latch is determined by the state of the two control
bits (C2, C1) in the shift register. These are the two LSBs DB1,
DB0 as shown in the timing diagram of Figure 1. The truth
table for these bits is shown in Table I. Table II shows a sum-
mary of how the latches are programmed.
Table I.C2, C1 Truth Table
Table II.ADF4001 Family Latch Summary
REFERENCE COUNTER LATCH
ADF4001
Table III.Reference Counter Latch Map

Partno	Mfg	Dc	Qty	Available	Descript
ADF4001	AD	N/a	120	avai	200MHz Clock Generator PLL