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ADE7759ARS
Active Energy Metering IC with di/dt Sensor Interface
REV.0
Active Energy Metering IC with
di/dt Sensor Interface
FUNCTIONAL BLOCK DIAGRAM
AVDDRESETDVDDDGND
SAG
V1P
V1N
V2N
V2P
CLKINCLKOUTDINDOUTSCLKREFIN/OUTCSIRQAGND
FEATURES
High Accuracy, Supports IEC 687/1036
On-Chip Digital Integrator Allows Direct Interface with
Current Sensors with di/dt Output Such as Rogowski Coil
Less Than 0.1% Error over a Dynamic Range of 1000 to 1
On-Chip User-Programmable Threshold for Line Voltage
SAG Detection and PSU Supervisory
The ADE7759 Supplies Sampled Waveform Data and
Active Energy (40 Bits)
Digital Power, Phase and Input DC Offset Calibration
On-Chip Temperature Sensor (Typical 1 LSB/�C Resolution)
SPI-Compatible Serial Interface
Pulse Output with Programmable Frequency
Interrupt Request Pin (IRQ) and IRQ Status Register
Proprietary ADCs and DSP provide High Accuracy over
Large Variations in Environmental Conditions and Time
Reference 2.4V � 8% (20 ppm/�C Typical) with External
Overdrive Capability
Single 5V Supply, Low Power Consumption (25mW
Typical)
GENERAL DESCRIPTIONThe ADE7759 is an accurate active power and energy measurement
IC with a serial interface and a pulse output. The ADE7759 incor-
porates two second order Σ-∆ ADCs, a digital integrator (on CH1),
reference circuitry, temperature sensor, and all the signal processing
required to perform active power and energy measurement.
An on-chip digital integrator allows direct interface to di/dt
current sensors such as a Rogowski coil. The digital integrator
eliminates the need for an external analog integrator and pro-
vides excellent long-term stability and precise phase matching
between the current and the voltage channels. The integrator
can be switched off if the ADE7759 is used with conventional
current sensors.
The ADE7759 contains a sampled Waveform register and an Active
Energy register capable of holding at least 11.53 seconds of accumu-
lated power at full ac load. Data is read from the ADE7759 via the
serial interface. The ADE7759 also provides a pulse output (CF)
with frequency that is proportional to the active power.
In addition to active power information, the ADE7759 also
provides various system calibration features, i.e., channel offset
correction, phase calibration, and power offset correction. The
part also incorporates a detection circuit for short duration
voltage drop (SAG). The voltage threshold and the duration (in
number of half-line cycles) of the drop are user programmable.
An open drain logic output (SAG) goes active low when a sag
event occurs.
A zero crossing output (ZX) produces an output that is synchro-
nized to the zero crossing point of the line voltage. This output
can be used to extract timing or frequency information from the
line. The signal is also used internally to the chip in the line
cycle energy accumulation mode; i.e., the number of half-line
cycles in which the energy accumulation occurs can be con-
trolled. Line cycle energy accumulation enables a faster and
more precise energy accumulation and is especially useful dur-
ing calibration. This signal is also useful for synchronization of
relay switching with a voltage zero crossing.
The interrupt request output is an open drain, active low logic
output. The Interrupt Status Register indicates the nature of the
interrupt, and the Interrupt Enable Register controls which
event produces an output on the IRQ pin. The ADE7759 is
available in a 20-lead SSOP package.
*U.S. Patents 5,745,323; 5,760,617; 5,862,069; 5,872,469; others pending.
ADE7759
TABLE OF CONTENTSFEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1
FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . 1
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . 5
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 6
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . .7
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . .7
TERMINOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
MEASUREMENT ERROR . . . . . . . . . . . . . . . . . . . . . . . . . 8
PHASE ERROR BETWEEN CHANNELS . . . . . . . . . . . . . 8
POWER SUPPLY REJECTION . . . . . . . . . . . . . . . . . . . . . . 8
ADC OFFSET ERROR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
GAIN ERROR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
GAIN ERROR MATCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
TYPICAL PERFORMANCE CHARACTERISTICS (TPC) . .9
TEST CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
ANALOG INPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
di/dt CURRENT SENSOR AND DIGITAL
INTEGRATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
ZERO CROSSING DETECTION . . . . . . . . . . . . . . . . . . .13
LINE VOLTAGE SAG DETECTION . . . . . . . . . . . . . . . .14
Sag Level Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
POWER SUPPLY MONITOR . . . . . . . . . . . . . . . . . . . . . .14
INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Using the ADE7759 Interrupts with an MCU . . . . . . . . .15
Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
TEMPERATURE MEASUREMENT . . . . . . . . . . . . . . . .16
ANALOG-TO-DIGITAL CONVERSION . . . . . . . . . . . . .16
Antialias Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
ADC Transfer Function . . . . . . . . . . . . . . . . . . . . . . . . . .17
Reference Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
CHANNEL 1 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Channel 1 ADC Gain Adjust . . . . . . . . . . . . . . . . . . . . . .18
Channel 1 Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
CHANNEL 1 AND CHANNEL 2 WAVEFORM
SAMPLING MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
CHANNEL 2 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Channel 2 Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
PHASE COMPENSATION . . . . . . . . . . . . . . . . . . . . . . . .19
ACTIVE POWER CALCULATION . . . . . . . . . . . . . . . . .20
ENERGY CALCULATION . . . . . . . . . . . . . . . . . . . . . . . .21
Integration Time under Steady Load . . . . . . . . . . . . . . . .22
POWER OFFSET CALIBRATION . . . . . . . . . . . . . . . . . .22
ENERGY-TO-FREQUENCY CONVERSION . . . . . . . . .22
LINE CYCLE ENERGY ACCUMULATION MODE . . .24
CALIBRATING THE ENERGY METER . . . . . . . . . . . . .24
Calculating the Average Active Power . . . . . . . . . . . . . . .24
Calibrating the Frequency at CF . . . . . . . . . . . . . . . . . . .25
Energy Meter Display . . . . . . . . . . . . . . . . . . . . . . . . . . .25
CLKIN FREQUENCY . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
SUSPENDING THE ADE7759 FUNCTIONALITY . . . .26
APPLICATION INFORMATION . . . . . . . . . . . . . . . . . . .26
SERIAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Serial Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Serial Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . .27
CHECKSUM REGISTER . . . . . . . . . . . . . . . . . . . . . . . . .28
REGISTER DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . .29
Communications Register . . . . . . . . . . . . . . . . . . . . . . . .29
Mode Register (06H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Interrupt Status Register (04H) . . . . . . . . . . . . . . . . . . . . 31
Reset Interrupt Status Register (05H) . . . . . . . . . . . . . . . 31
CH1OS Register (08H) . . . . . . . . . . . . . . . . . . . . . . . . . . 32
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . .32
ADE7759
SPECIFICATIONS1ANALOG INPUTS
(AVDD = DVDD = 5 V � 5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 3.579545 MHz XTAL,
TMIN to TMAX = –40�C to +85�C unless otherwise noted.)
ADE7759–SPECIFICATIONSPOWER SUPPLY
NOTESSee Terminology section for explanation of specifications.See plots in Typical Performance Characteristics.See Analog Inputs section.
Specifications subject to change without notice.
(continued)
TIMING CHARACTERISTICS1, 2Read Timing
NOTESSample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5ns
(10% to 90%) and timed from a voltage level of 1.6V.See Figures 2 and 3 and Serial Interface section of this data sheet.Measured with the load circuit in Figure 1 and defined as the time required for the output to cross 0.8V or 2.4V.Derived from the measured time taken by the data outputs to change 0.5V when loaded with the circuit in Figure 1. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50pF capacitor. This means that the time quoted in the timing characteristics is the true bus relinquish time of
the part and is independent of the bus loading.
(AVDD = DVDD = 5 V � 5%, AGND = DGND = 0V, On-Chip Reference, CLKIN = 3.579545MHz
XTAL, TMIN to TMAX = –40�C to +85�C unless otherwise noted.)Figure 2.Serial Write Timing
Figure 1.Load Circuit for Timing Specifications
ADE7759
ABSOLUTE MAXIMUM RATINGS*(TA = 25°C unless otherwise noted)
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3V to +7V
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3V to +7V
DVDD to AVDD . . . . . . . . . . . . . . . . . . . . . . . –0.3V to +0.3V
Analog Input Voltage to AGND
V1P, V1N, V2P, and V2N . . . . . . . . . . . . . . . . . –6 V to +6 V
Reference Input Voltage to AGND . . –0.3 V to AVDD + 0.3V
Digital Input Voltage to DGND . . . . –0.3 V to DVDD + 0.3 V
Digital Output Voltage to DGND . . . –0.3 V to DVDD + 0.3 V
Operating Temperature Range
Industrial (A, B Versions) . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . .150°C
20-Lead SSOP, Power Dissipation . . . . . . . . . . . . . . .450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . .112°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . .215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADE7759 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE*RS = Shrink Small Outline Package in tubes; RSRL = Shrink Small
Outline Package in reel.
PIN FUNCTION DESCRIPTIONS2DVDD
PIN CONFIGURATION
ADE7759
TERMINOLOGY
MEASUREMENT ERRORThe error associated with the energy measurement made by the
ADE7759 is defined by the following formula:
PHASE ERROR BETWEEN CHANNELSThe digital integrator and the HPF1 (High-Pass Filter) in Channel
1 have nonideal phase response. To offset this phase response
and equalize the phase response between channels, two phase
correction networks are placed in Channel 1: one for the digital
integrator and the other for the HPF1. Each phase correction
network corrects the phase response of the corresponding com-
ponent and ensures a phase match between Channel 1 (current)
and Channel 2 (voltage) to within ±0.1° over a range of 45Hz
to 65Hz and ±0.2° over a range 40Hz to 1kHz.
POWER SUPPLY REJECTIONThis quantifies the ADE7759 measurement error as a percent-
age of reading when the power supplies are varied.
For the ac PSR measurement a reading at nominal suppliesV) is taken. A second reading is obtained with the same input
signal levels when an ac (175mV rms/120Hz) signal is intro-
nominal supplies (5V) is taken. A second reading is obtained
with the same input signal levels when the supplies are varied ±5%.
Any error introduced is again expressed as a percentage of reading.
ADC OFFSET ERRORThis refers to the dc offset associated with the analog inputs to the
ADCs. It means that with the analog inputs connected to AGND
the ADCs still see a dc analog input signal. The magnitude of the
offset depends on the gain and input range selection—see
characteristic curves. However, when HPF1 is switched on, the
offset is removed from Channel 1 (current) and the power calcu-
lation is not affected by this offset. The offsets may be removed
by performing an offset calibration—see Analog Inputs section.
GAIN ERRORThe gain error in the ADE7759 ADCs is defined as the difference
between the measured ADC output code (minus the offset) and
the ideal output code—see Channel 1 ADC and Channel 2
ADC. It is measured for each of the input ranges on Channel 1
(0.5V, 0.25V and 0.125V). The difference is expressed as a
percentage of the ideal code.
GAIN ERROR MATCHThe Gain Error Match is defined as the gain error (minus the offset)
obtained when switching between a gain of 1 (for each of the
input ranges) and a gain of 2, 4, 8, or 16. It is expressed as a
PIN FUNCTION DESCRIPTIONS (continued)
TPC 1.Error as a % of Reading (Integrator OFF, Power
Factor=1, Internal Reference, Gain=1)
TPC 2.Error as a % of Reading (Integrator OFF, Power
Factor=1, External Reference, Gain=1)
TPC 3.Error as a % of Reading (Integrator OFF, Power
Factor=1, Internal Reference, Gain=4)
TPC 4.Error as a % of Reading (Integrator OFF, Power
Factor=0.5, Internal Reference, Gain=1)
TPC 5.Error as a % of Reading (Integrator OFF, Power
Factor=0.5, External Reference, Gain=1)
TPC 6.Error as a % of Reading (Integrator OFF, Power
Factor=0.5, Internal Reference, Gain=4)
ADE7759TPC 7.Error as a % of Reading (Integrator OFF, Power
Factor=1, External Reference, Gain=4)
TPC 8.Error as a % of Reading (Integrator ON, Power
Factor=1, Internal Reference, Gain=4)
TPC 9.Error as a % of Reading (Integrator ON, Power
Factor=1, External Reference, Gain=4)
TPC 10.Error as a % of Reading (Integrator OFF,
Power Factor=0.5, External Reference, Gain=4)
TPC 11.Error as a % of Reading (Integrator ON, Power
Factor=0.5, Internal Reference, Gain=4)
TPC 12.Error as a % of Reading (Integrator ON, Power
Factor=0.5, External Reference, Gain=4)
Test Circuit 1.Performance Curve (Integrator OFF)
Test Circuit 2.Performance Curve (Integrator ON)
ANALOG INPUTSThe ADE7759 has two fully differential voltage input channels.
The maximum differential input voltage for input pairs V1P/V1N
and V2P/V2N are ±0.5 V. In addition, the maximum signal level
on analog inputs for V1P/V1N and V2P/V2N are ±0.5V with
respect to AGND.
Each analog input channel has a PGA (Programmable Gain
Amplifier) with possible gain selections of 1, 2, 4, 8, and 16.
The gain selections are made by writing to the Gain register—
see Figure 5. Bits 0 to 2 select the gain for the PGA in Channel1
and the gain selection for the PGA in Channel 2 is made via
Bits5 to 7. Figure 4 shows how a gain selection for Channel1made using the Gain register.
In addition to the PGA, Channel 1 also has a full-scale input
range selection for the ADC. The ADC analog input range
selection is also made using the Gain register—see Figure 2. As
mentioned previously the maximum differential input voltage is
0.5V. However, by using Bits 3 and 4 in the Gain register, the
maximum ADC input voltage can be set to 0.5V, 0.25V, or
0.125V. This is achieved by adjusting the ADC reference—see
Reference Circuit section. Table I summarizes the maximum
differential input signal level on Channel 1 for the various ADC
range and gain selections.
Table I.Maximum Input Signal Levels for Channel 1
GAIN REGISTER*
CHANNEL 1 AND CHANNEL 2 PGA CONTROL
7 6 5 4 3 2 1 0ADDR:
0AH
PGA 2 GAIN SELECT
000 = �1
001 = �2
010 = �4
011 = �8
100 = �16
PGA 1 GAIN SELECT
000 = �1
001 = �2
010 = �4
011 = �8
100 = �16
CHANNEL 1 FULL SCALE SELECT
Test Circuits
ADE7759It is also possible to adjust offset errors on Channel 1 and Channel2
by writing to the Offset Correction registers (CH1OS and CH2OS
respectively). These registers allow channel offsets in the range
±24mV to ±50mV (depending on the gain setting) to be removed.
Note that it is not necessary to perform an offset correction in an
energy measurement application if HPF1 Channel 1 is switched
on. Figure 6 shows the effect of offsets on the real power calcula-
tion. As seen in Figure 6, an offset on Channel 1 and Channel2
will contribute a dc component after multiplication. Since this
dc component is extracted by LPF2 to generate the Active (Real)
Power information, the offsets will have contributed an error to
the Active Power calculation. This problem is easily avoided by
enabling HPF1 in Channel 1. By removing the offset from at
least one channel, no error component is generated at dc by the
multiplication. Error terms at cos(ω t) are removed by LPF2 and
by integration of the Active Power signal in the Active Energy
register (AENERGY[39:0])—see Energy Calculation section.
VOS � IOS
V � I�
2�Figure 6.Effect of Channel Offsets on the Real
Power Calculation
The contents of the Offset Correction registers are 6-bit, sign,
and magnitude coded. The weighting of the LSB size depends
on the gain setting, i.e., 1, 2, 4, 8, or 16. Table II shows the
correctable offset span for each of the gain settings and the LSB
weight (mV) for the Offset Correction registers. The maximum
value that can be written to the offset correction registers is ±31
decimal—see Figure 7.
Table II.Offset Correction RangeFigure 7 shows the relationship between the Offset Correction
register contents and the offset (mV) on the analog inputs for a
gain setting of one. In order to perform an offset adjustment, the
analog inputs should be first connected to AGND, and there
should be no signal on either Channel 1 or Channel 2. A read
from Channel 1 or Channel 2 using the Waveform register will
give an indication of the offset in the channel. This offset can be
canceled by writing an equal but opposite offset value to the
relevant offset register. The offset correction can be confirmed by
performing another read. Note that when adjusting the offset of
CH1OS[5:0]Figure 7.Channel Offset Correction Range (Gain = 1)
di/dt CURRENT SENSOR AND DIGITAL INTEGRATORdi/dt sensor detects changes in magnetic field caused by ac
current. Figure 8 shows the principle of a di/dt current sensor.
Figure 8.Principle of a di/dt Current Sensor
The flux density of a magnetic field induced by a current is directly
proportional to the magnitude of the current. The changes in
the magnetic flux density passing through a conductor loop
generate an electromotive force (EMF) between the two ends of
the loop. The EMF is a voltage signal that is proportional to the
di/dt of the current. The voltage output from the di/dt current
sensor is determined by the mutual inductance between the
current-carrying conductor and the di/dt sensor. Figure 9 shows
the mutual inductance produces a di/dt signal at the output of
the sensor.
Figure 9.Mutual Inductance Between the di/dt
Sensor and the Current Carrying Conductor
The current signal needs to be recovered from the di/dt signal
before it can be used for active power calculation. An integrator
is therefore necessary to restore the signal to its original form.
The ADE7759 has a built-in digital integrator to recover the
current signal from the di/dt sensor. The digital integrator on
Channel 1 is switched on by default when the ADE7759 is
powered up. Setting the MSB of the CH1OS register to 0 will
turn off the integrator. Figures 10 to 13 show the magnitude and
Figure 10.Gain Response of the Digital Integrator
Figure 11.Phase Response of the Digital Integrator
Figure 12.Gain Response of the Digital Integrator
(40Hz to 70Hz)
Figure 13.Phase Response of the Digital Integrator
(40Hz to 70Hz)
Note that the integrator has a –20dB/dec attenuation and approxi-
mately –90° phase shift. When combined with a di/dt sensor, the
resulting magnitude and phase response should be a flat gain
over the frequency band of interest. However, the di/dt sensor has
a 20dB/dec gain associated with it, and generates significant high
frequency noise. A more effective antialiasing filter is needed to
avoid noise due to aliasing—see Antialias Filter section.
When the digital integrator is switched off, the ADE7759 can be
used directly with a conventional current sensor such as current
transformer (CT) or a low resistance current shunt.
ZERO CROSSING DETECTIONThe ADE7759 has a zero crossing detection circuit on Channel2.
This zero crossing is used to produce an external zero cross
signal (ZX) and it is also used in the calibration mode—see
Energy Calibration section. The zero crossing signal is also used
to initiate a temperature measurement on the ADE7759—see
Temperature Measurement section. Figure 14 shows how the
zero cross signal is generated from the output of LPF1.
Figure 14.Zero Cross Detection on Channel 2
ADE7759The ZX signal will go logic high on a positive going zero crossing
and logic low on a negative going zero crossing on Channel 2.
The zero crossing signal ZX is generated from the output of LPF1.
LPF1 has a single pole at 156Hz (CLKIN = 3.579545MHz).
As a result there will be a phase lag between the analog input
signal V2 and the output of LPF1. The phase response of this
filter is shown in the Channel 2 Sampling section of this data
sheet. The phase lag response of LPF1 results in a time delay of
approximately 0.97ms (@ 60Hz) between the zero crossing on
the analog inputs of Channel 2 and the rising or falling edge of ZX.
The zero crossing detection also has an associated time-out register,
ZXTOUT. This unsigned, 12-bit register is decremented 1 LSB
every 128/CLKIN seconds. The register is reset to its user pro-
grammed full-scale value every time a zero crossing on Channel2
is detected. The default power on value in this register is FFFh.
If the register decrements to zero before a zero crossing is detected
and the DISSAG bit in the Mode register is logic zero, the SAG
pin will go active low. The absence of a zero crossing is also
indicated on the IRQ output if the SAG enable bit in the Inter-
rupt Enable register is set to Logic 1. Irrespective of the enable
bit setting, the SAG flag in the Interrupt Status register is always
set when the ZXTOUT register is decremented to zero—see Inter-
rupts section. The zero cross timeout register can be written/read
by the user and has an address of 0Eh—see Serial Interface section.
The resolution of the register is 128/CLKIN seconds per LSB.
Thus the maximum delay for an interrupt is 0.15 second
(128/CLKIN× 212).
LINE VOLTAGE SAG DETECTIONIn addition to the detection of the loss of the line voltage signal
(zero crossing), the ADE7759 can also be programmed to detect
when the absolute value of the line voltage drops below a certain
peak value, for a number of half cycles. This condition is illus-
trated in Figure 15.
Figure 15. Sag Detection
Figure 15 shows the line voltage fall below a threshold that is set
in the Sag Level register (SAGLVL[7:0]) for nine half cycles.
Since the Sag Cycle register (SAGCYC[7:0]) contains 06h, the
SAG pin will go active low at the end of the sixth half cycle for
which the line voltage falls below the threshold, if the DISSAG
bit in the Mode register is logic zero. As is the case when zero
crossings are no longer detected, the sag event is also recorded
by setting the SAG flag in the Interrupt Status register. If the
The SAG pin will go logic high again when the absolute value of
the signal on Channel 2 exceeds the sag level set in the Sag
Level register. This is shown in Figure 15 when the SAG pin
goes high during the tenth half cycle from the time when the
signal on Channel 2 first dropped below the threshold level.
Sag Level SetThe contents of the Sag Level register (1 byte) are compared to
the absolute value of the most significant byte output from LPF1,
after it is shifted left by one bit. For example, the nominal maximum
code from LPF1 with a full-scale signal on Channel 2 is 257F6h
or (0010, 0101, 0111, 1111, 0110b)—see Channel 2 Sampling
section. Shifting one bit left will give 0100, 1010,1111,1110,
1100b or 4AFECh. Therefore writing 4Ah to the Sag Level
register will put the sag detection level at full scale. Writing 00h
will put the sag detection level at zero. The Sag Level register is
compared to the most significant byte of a waveform sample
after the shift left, and detection is made when the contents of
the Sag Level register are greater.
POWER SUPPLY MONITORThe ADE7759 also contains an on-chip power supply monitor. The
Analog Supply (AVDD) is continuously monitored by the ADE7759.
If the supply is less than 4V ± 5%, the ADE7759 will go into an
inactive state, i.e., no energy will be accumulated when the supply
voltage is below 4V. This is useful to ensure correct device operation
at power-up and during power-down. The power supply monitor
has built-in hysteresis and filtering. This gives a high degree of
immunity to false triggering due to noisy supplies.
Figure 16. On-Chip Power Supply Monitor
As seen in Figure 16, the trigger level is nominally set at 4V.
The tolerance on this trigger level is about ±5%. The SAG pin
can also be used as a power supply monitor input to the MCU.
The SAG pin will go logic low when the ADE7759 is reset. The
power supply and decoupling for the part should be such that
the ripple at AVDD does not exceed 5 V± 5% as specified for
normal operation.
Bit 6 of the Interrupt Status register (STATUS[7:0]) will be set to
Logic High upon power-up or every time the analog supply (AVDD)
dips below the power supply monitor threshold (4V ± 5%) and
recovers. However, no interrupt can be generated because the corre-
sponding bit (Bit 6) in the Interrupt Enable register (IRQEN[7:0])
INTERRUPTSADE7759 Interrupts are managed through the Interrupt Status
register (STATUS[7:0]) and the Interrupt Enable register
(IRQEN[7:0]). When an interrupt event occurs in the ADE7759,
the corresponding flag in the Status register is set to a Logic1
—see Interrupt Status register. If the enable bit for this interrupt
in the Interrupt Enable register is Logic 1, then the IRQ logic output
goes active low. The flag bits in the Status register are set irre-
spective of the state of the enable bits.
In order to determine the source of the interrupt, the system
master (MCU) should perform a read from the Status register
with reset (RSTATUS[7:0]). This is achieved by carrying out a
read from address 05h. The IRQ output will go logic high on
completion of the Interrupt Status register read command—see
Interrupt Timing section. When carrying out a read with reset, the
ADE7759 is designed to ensure that no interrupt events are
missed. If an interrupt event occurs just as the Status register is
being read, the event will not be lost and the IRQ logic output is
guaranteed to go high for the duration of the Interrupt Status
register data transfer before going logic low again to indicate the
pending interrupt. See the following section for a more detailed
description.
Using the ADE7759 Interrupts with an MCUFigure 17 shows a timing diagram with a suggested implementa-
tion of ADE7759 interrupt management using an MCU. At time t1
the IRQ line will go active low, indicating that one or more
interrupt events have occurred in the ADE7759. The IRQ logic
output should be tied to a negative edge-triggered external inter-
rupt on the MCU. On detection of the negative edge, the MCU
should be configured to start executing its Interrupt Service
Routine (ISR). On entering the ISR, all interrupts should be
disabled using the global interrupt enable bit. At this point the
MCU external interrupt flag can be cleared to capture interrupt
events that occur during the current ISR.
When the MCU interrupt flag is cleared, a read from the Status
register with reset is carried out. This will cause the IRQ line to
be reset logic high (t2)—see Interrupt Timing section. The Sta-
tus register contents are used to determine the source of the
interrupt(s) and hence the appropriate action to be taken. If a
subsequent interrupt event occurs during the ISR, that event will
be recorded by the MCU external interrupt flag being set again
(t3). On returning from the ISR, the global interrupt mask will be
cleared (same instruction cycle) and the external interrupt flag will
cause the MCU to jump to its ISR once again. This will ensure
that the MCU does not miss any external interrupts.
Interrupt TimingThe Serial Interface section should be reviewed first, before the
interrupt timing. As previously described, when the IRQ output
goes low the MCU ISR must read the Interrupt Status register
to determine the source of the interrupt. When reading the
Status register contents, the IRQ output is set high on the last
falling edge of SCLK of the first byte transfer (read Interrupt
Status register command). The IRQ output is held high until the
last bit of the next 8-bit transfer is shifted out (Interrupt Status
register contents)—see Figure 18. If an interrupt is pending at
this time, the IRQ output will go low again. If no interrupt is
pending, the IRQ output will stay high.
Figure 17.Interrupt Management
Figure 18.Interrupt Timing
ADE7759
TEMPERATURE MEASUREMENTADE7759 also includes an on-chip temperature sensor. A tem-
perature measurement can be made by setting Bit 5 in the Mode
register. When Bit 5 is set logic high in the Mode register, the
ADE7759 will initiate a temperature measurement on the next
zero crossing. When the zero crossing on Channel 2 is detected,
the voltage output from the temperature sensing circuit is con-
nected to ADC1 (Channel 1) for digitizing. The resultant code is
processed and placed in the Temperature register (TEMP[7:0])
approximately 26µs later (24 CLKIN cycles). If enabled in the
Interrupt Enable register (Bit 5), the IRQ output will go active
low when the temperature conversion is finished. Please note that
temperature conversion will introduce a small amount of noise
in the energy calculation. If temperature conversion is performed
frequently (i.e., multiple times per second), a noticeable error
will accumulate in the resulting energy calculation over time.
The contents of the Temperature register are signed (two’s
complement) with a resolution of approximately 1 LSB/°C. The
temperature register will produce a code of 00h when the ambient
temperature is approximately 70°C. The temperature mea-
surement is uncalibrated in the ADE7759 and has an offset
tolerance that could be as high as ±20°C.
ANALOG-TO-DIGITAL CONVERSIONThe analog-to-digital conversion in the ADE7759 is carried out
using two second order sigma-delta ADCs. The block diagram
in Figure 19 shows a first order (for simplicity) sigma-delta ADC.
The converter is made up of two parts, first the sigma-delta
modulator and second the digital low-pass filter.
A sigma-delta modulator converts the input signal into a con-
tinuous serial stream of 1s and 0s at a rate determined by the
sampling clock. In the ADE7759, the sampling clock is equal to
CLKIN/4. The 1-bit DAC in the feedback loop is driven by the
serial data stream. The DAC output is subtracted from the
input signal. If the loop gain is high enough, the average value of
the DAC output (and therefore the bitstream) will approach that
of the input signal level. For any given input value in a single sam-
pling interval, the data from the 1-bit ADC is virtually meaningless.
Only when a large number of samples are averaged will a meaningful
result be obtained. This averaging is carried out in the second
part of the ADC, the digital low-pass filter. By averaging a large
number of bits from the modulator, the low-pass filter can produce
20-bit data words that are proportional to the input signal level.
Figure 19.First Order Sigma-Delta (Σ-∆) ADC
The sigma-delta converter uses two techniques to achieve high
resolution from what is essentially a one-bit conversion technique.
than the bandwidth of interest. For example, the sampling rate
in the ADE7759 is CLKIN/4 (894kHz) and the band of interest
is 40Hz to 2kHz. Oversampling has the effect of spreading the
quantization noise (noise due to sampling) over a wider bandwidth.
With the noise spread more thinly over a wider bandwidth, the
quantization noise in the band of interest is lowered—see Figure
20. However, oversampling alone is not an efficient enough
method to improve the signal to noise ratio (SNR) in the band
of interest. For example, an oversampling ratio of 4 is required
just to increase the SNR by only 6dB (one bit). To keep the
oversampling ratio at a reasonable level, it is possible to shape the
quantization noise so that the majority of the noise lies at the higher
frequencies. This is what happens in the sigma-delta modulator:
the noise is shaped by the integrator, which has a high-pass type
response for the quantization noise. The result is that most of
the noise is at the higher frequencies, where it can be removed
by the digital low-pass filter. This noise shaping is also shown in
Figure 20.
SIGNAL
ANTIALIAS
FILTER (RC)
SIGNAL
FREQUENCY – kHz
FREQUENCY – kHzFigure 20.Noise Reduction Due to Oversampling
and Noise Shaping in the Analog Modulator
Antialias FilterFigure 20 also shows an analog low-pass filter (RC) on the input
to the modulator. This filter is present to prevent aliasing.
Aliasing is an artifact of all sampled systems. Basically it means
that frequency components in the input signal to the ADC that
are higher than half the sampling rate of the ADC will appear in
the sampled signal at a frequency below half the sampling rate.
Figure 21 illustrates the effect. Frequency components (arrows
shown in black) above half the sampling frequency (also known as
the Nyquist frequency, i.e., 447kHz) get imaged or folded back
down below 447kHz (arrows shown in grey). This will happen
with all ADCs regardless of the architecture. In the example
shown, it can be seen that only frequencies near the sampling
frequency (894kHz) will move into the band of interest for
metering, i.e., 40Hz–2kHz. This allows us to use a very simple
LPF (low-pass filter) to attenuate these high frequencies (near
900kHz) and to prevent distortion in the band of interest. For a
conventional current sensor, a simple RC filter (single pole) with
a corner frequency of 10kHz will produce an attenuation of
approximately 40dBs at 894kHz—see Figure 20. The 20dB per
